JPH07230073A - Liquid crystal display system and method of supplying power source - Google Patents

Abstract

PURPOSE:To provide a power supply method optimum for the case when ranges of source voltages applied to a scan driver, a signal driver are different from each other. CONSTITUTION:A power source supply part 5 supplies source voltage group V11, VC1, V12 of the same polarity provided with a narrow source voltage range to the signal driver 2, and supplies the source voltage group V10, VC2, V15 of the same polarity provided with a wide source voltage range to the scan driver 3. Then, central voltages VC1, VC2 are equal. The power source supply part 5 is provided with a means for adjusting the value of the supplied source voltage. A control signal, etc., from a control part 1 is level changed by a potential change part 6. When display off is realized, the outputs of the signal driver 2, the scan driver 3 are made a VC level. By such a manner, the adjustment of a liquid crystal driving voltage is realized by a simple adjustment means while holding a precise voltage ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply method in a liquid crystal display system including a signal driver (signal electrode drive circuit) and a scan driver (scan electrode drive circuit).

[0002]

2. Description of the Related Art A liquid crystal driving method based on a voltage averaging method is known as one of conventional liquid crystal driving technologies. In this liquid crystal driving method, scanning electrodes are sequentially selected line by line to apply a scanning voltage, and a signal voltage corresponding to each pixel is applied to each signal electrode depending on whether each pixel on the selected scanning electrode is on or off. By doing so, liquid crystal driving is performed.

FIG. 19 shows the potential relationship of the power supply voltage when the voltage averaging method is used. V0, V1, V2, V
3, V4, V5 are liquid crystal driving power supply voltage groups used in the voltage averaging method, V0, V2, V3, V5 are supplied to the signal driver, and V0, V1, V4, V5 are supplied to the scan driver. To be done. The relationship of the potentials of these power supply voltages is V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5. G
The ND is a ground common to the signal driver, the scan driver, and the control unit (system side) that controls the signal driver and the scan driver. Also, VD is about 3
This is a logic power supply voltage of ˜5 V, and this VD is also a logic power supply voltage common to the signal driver, the scan driver, and the control section. Therefore, the control signal output from the control unit can be directly connected to the signal driver and the scan driver. In FIG. 19, the lowest potential V5 of the liquid crystal drive voltage and the ground potential GND are set to the same potential, and the highest potential V0 and VDDH of the liquid crystal drive voltage are set to the same potential. As is apparent from FIG. 19, power supply voltage groups V0, V2, V3, and V5 applied to the signal driver.
The power supply voltage range A1 of 1 is equal to the power supply voltage range A2 of the power supply voltage groups V0, V1, V4, and V5 given to the scan driver.

In a conventional liquid crystal display system using the voltage averaging method, a function called display off or LCD off is known. This function is to force the voltage applied to the liquid crystal element to "0".
As a result, it is possible to prevent the voltage from being applied to the liquid crystal for a certain period after the power is turned on when the output voltage of the driver becomes indefinite. In addition, the voltage applied to the liquid crystal element is set to “0” while the power of the liquid crystal display system is turned on,
It becomes possible to save power at the same time as turning off the display. The display off function in the conventional driver using the voltage averaging method is V5 (= GND), which is a common potential of the scan driver, the signal driver, and the control unit (system side).
Are simultaneously output from the signal driver and the scan driver, and the voltage applied to the liquid crystal element is set to “0”.

[0005]

By the way, in recent years, multiple line simultaneous selection (multip
le Lines Selection) A driving method has been proposed. Regarding the method for simultaneously selecting a plurality of lines, Japanese Patent Application No. 5-515
531, Japanese Patent Application No. 5-152533. According to this method, it is possible to realize a liquid crystal display system which has higher contrast and less flicker than the conventional one. Then, the drive voltage of the signal driver can be suppressed low while realizing the same on / off ratio as the voltage averaging method which is a conventional method of selecting and driving each line one by one. As a result, it is possible to adopt a manufacturing process having a lower breakdown voltage as a semiconductor process for manufacturing the signal driver, and it is possible to increase the integration degree of the signal driver and reduce the chip area. This leads to higher performance of the signal driver and cost reduction.

However, in this multiple line simultaneous selection drive method, the scan driver requires a high drive voltage equivalent to that in the conventional technique, and the drive voltage range differs between the signal driver and the scan driver. For this reason, it is necessary to make the range of the power supply voltage supplied to the signal driver and the scan driver different, and there is a problem that the concept of the conventional power supply method cannot be applied as it is.

Further, a liquid crystal element that constitutes a liquid crystal panel, a semiconductor device that constitutes a driver, etc., has a problem of characteristic variations due to variations in the manufacturing process. Therefore, after assembling the liquid crystal display system in a factory, it is necessary to perform an adjusting operation for optimizing the values of the drive voltages applied to the signal electrodes and the scan electrodes. Further, some liquid crystal display systems are capable of adjusting the contrast of liquid crystal display, and this contrast adjustment is realized by adjusting the drive voltage applied to the signal electrodes and the scanning electrodes. As described above, the liquid crystal display system needs a function of adjusting the drive voltage in order to optimize the drive voltage or adjust the contrast. However, in the multiple line simultaneous selection drive method, it is necessary to make the range of the power supply voltage supplied to the signal driver and the scan driver different as described above, and the drive voltage used in the liquid crystal display system of the conventional voltage averaging method is different. There is a problem that the adjustment method cannot be applied as it is.

Further, in the conventional liquid crystal driver using the voltage averaging method, the signal dry and the output of the scan driver are both the power supply voltage V5 (= GN) on the low potential side (or high potential side).
D) The display off function was realized by setting the level. However, when the drive voltage range of the signal driver is different from that of the scan driver, the power supply voltage on the low potential side does not match, so that the voltage applied to the liquid crystal cannot be set to "0" and the display-off function cannot be realized. There's a problem.

The present invention has been made in order to solve the problems described above, and an object of the present invention is to provide an optimum power supply when the range of the power supply voltage applied to the scan driver and the signal driver is different. To provide a method.

Another object of the present invention is to provide a power supply method capable of arbitrarily adjusting the drive voltage applied to the liquid crystal element even when the range of the power supply voltage applied to the scan driver and the signal driver is different. .

Another object of the present invention is to realize a display-off function in a liquid crystal display system in which the range of power supply voltage applied to the scan driver and the signal driver is different.

[0012]

In order to solve the above-mentioned problems, the present invention provides a matrix panel in which display pixels are arranged in a matrix and a plurality of signal electrodes and scanning electrodes are arranged so as to intersect with each other. A signal driver that applies a drive voltage to the signal electrode, a scan driver that applies a drive voltage to the scan electrode, and a power supply unit that supplies a power supply voltage to the signal driver and the scan driver. A liquid crystal display system including the first power supply means having a first power supply voltage range and having a first polarity;
Means for supplying the power supply voltage group to one of the signal driver or the scan driver, and a second power supply voltage group having a second power supply voltage range wider than the first power supply voltage range and having the same polarity. Means for supplying a power supply voltage group to another driver different from the one, a first center voltage that is the center voltage of the first power supply voltage range, and a center voltage of the second power supply voltage range. Means for making a certain second center voltage the same.

According to the present invention, the first power supply voltage group of the same polarity having a narrow power supply voltage range is applied to one of the signal driver and the scan driver, and the power supply voltage range is supplied to the other driver. A second power supply voltage group of the same polarity having a wide range. Then, the power supply voltage is supplied so that the center voltages of these power supply voltage ranges are equal. According to the present invention, since the power supply voltage group has the same polarity, each voltage value of the power supply voltage group can be adjusted by the adjusting means having a simple structure. Then, when the voltage is adjusted, the voltage ratio of the power supply voltage can be accurately maintained regardless of whether the power supply voltage is on the positive polarity side or the negative polarity side of the center voltage.

Further, according to the present invention, the power supply means divides the fixed potential and the reference potential for generating the liquid crystal drive voltage and generates a divided voltage at the divided terminals, whereby the first and second power supplies are generated. Means for generating a voltage group, and means for making the first and second center voltages the same by generating the first and second center voltages based on a division voltage generated at one of the division terminals. It is characterized by including.

According to the present invention, the voltage dividing means having a simple structure using a resistor, a transistor, etc. is used, and the first and second voltage dividing means are used.
The power supply voltage group of can be generated. Moreover, the first and second center voltages can be made the same with a simple configuration in which the first and second center voltages are generated based on the division voltage generated at one division terminal.

Further, according to the present invention, means for adjusting the value of the divided voltage by adjusting the value of the reference potential for generating the liquid crystal drive voltage and adjusting the voltage values of the first and second power supply voltage groups. It is characterized by including.

According to the present invention, the voltage values of the first and second power supply voltage groups are adjusted while maintaining an accurate voltage division ratio by a simple method of adjusting the value of the reference potential for generating the liquid crystal drive voltage. it can.

Further, according to the present invention, the power supply means supplies a voltage within the first power supply voltage range as a logic power supply voltage of the one driver to which the first power supply voltage group is supplied. It is characterized by including.

According to the present invention, the first power source has a narrow power supply voltage range.
The logic power supply voltage of one of the drivers to which the power supply voltage group is supplied is set within the first power supply voltage range. As a result, it is not necessary to widen the operating power supply voltage width of one driver in order to operate the logic circuit built in one driver, and it is possible to narrow the operating power supply voltage width of one driver. .

According to the present invention, the fixed potential power source on the low potential side or the high potential side of the one driver to which the first power source voltage group is supplied and the second power source voltage group are supplied. It is characterized in that the fixed potential power source on the low potential side or the high potential side of the other driver is separated.

According to the present invention, the fixed potential power source of one driver and the fixed potential power source of the other driver are separated. This eliminates the need to widen the operating power supply voltage width of one driver to which a narrow power supply voltage group is applied in accordance with the operating power supply voltage width of the other driver, and to narrow the operating power supply voltage width of one driver. Is possible.

Further, the present invention includes means for outputting at least a control signal to the signal driver and the scan driver, and is output to the one driver to which the first power supply voltage group is supplied. It is characterized by including potential conversion means for converting the potential level of the control signal into a level within the first power supply voltage range.

According to the present invention, the control signal and the like are converted in potential level and input into one of the drivers. As a result, the control signal or the like can be normally transmitted to one of the drivers operating in a narrow power supply voltage range.

Further, the invention is characterized in that the potential converting means includes a capacitive coupling capacitor for cutting a DC component.

According to the present invention, only the amount of change in the control signal can be taken out by the capacitive coupling capacitor, which facilitates the conversion of the potential level.

Further, according to the present invention, when a predetermined external signal is input, the drive voltage output from the signal driver and the scan driver is set to the same voltage as the first and second center voltages. It is characterized by including a means for doing.

According to the present invention, when an external signal such as a display-off signal is input, the output voltages of the signal driver and the scan driver become the same voltage, that is, the same center voltage. As a result, the voltage applied to the liquid crystal element is "0".
Therefore, it is possible to realize a display-off function in liquid crystal display.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) 1. Description of Overall Configuration FIG. 1 is a block diagram showing the overall configuration of a liquid crystal display system according to a first embodiment. This embodiment includes a control unit (system side) 1, a signal driver 2, a scan driver 3, a liquid crystal panel 4, a power supply unit 5, and a plurality of potential conversion units 6. Here, the control unit 1 outputs a control signal, signal data, and scan data to the signal driver 2 and the scan driver 3. The signal driver 2 outputs the drive voltage 10 to the signal electrode of the liquid crystal panel 4 based on the control signal and the signal data from the control unit 1. The scanning driver 3 includes the control unit 1
The drive voltage 11 is output to the scan electrodes of the liquid crystal panel 4 based on the control signal and the scan data from. The liquid crystal panel 4 has a plurality of signal electrodes, scanning electrodes intersecting with the signal electrodes, and liquid crystal elements arranged in the intersecting regions, and a display operation is performed by driving the signal driver 2 and the scanning driver 3. The power supply unit 5 generates a power supply voltage group to be supplied to the signal driver 2 and the scan driver 3 based on the voltage VLCD that is supplied from the control unit 1 and serves as a reference for liquid crystal drive voltage generation. The potential converter 6 includes a capacitive coupling capacitor (capacitor) 1
2. The DC level transfer unit 58 is included to convert the potential levels of the control signal, signal data, and scan data from the control unit 1.

From the control unit 1 to the signal driver 2,
DOFF signal for turning off the display of the liquid crystal panel, FR signal for AC driving the liquid crystal, LP signal as a latch pulse, tX signal as a data transfer clock, DXm signal as a 2-bit data signal, sampling start The ST signal which is a signal is output. In this case, in this embodiment, the ground potential GND and the logic potential VD of the controller 1 are not supplied to the signal driver 2. That is, in the control unit 1 and the signal driver 2, the reference potential (GND in the control unit 1, VS1 in the signal driver 2) and the logic potential (VD in the control unit 1, VD1 in the signal driver 2) on the lowest potential side are It is not standardized.

From the control unit 1 to the scan driver 3,
DOFF signal, FR signal, t which is a data transfer clock
Y signal, DYn which is scanning data of 2 bits × 2 lines
m signal is output. Further, in this embodiment, the ground potential GND and the logic potential VD of the control unit 1 are supplied to the scan driver 3. That is, the control unit 1 and the scan driver 3
In and, the reference potential GND and the logic potential VD on the lowest potential side are shared.

A VLCD, which is a reference for generating a liquid crystal drive voltage, is input to the power supply section 5. Then, for the signal driver 2, V11, VC1 (= VC), V12, V
A power supply voltage group of D1 and VS1 is supplied, and a power supply voltage group of V10, VC2 (= VC) and V15 is supplied to the scan driver 3.

2. Description of Power Supply Unit FIG. 2 shows an example of the configuration of the power supply unit 5, and FIG. 3 shows a power supply voltage group V1 supplied from the power supply unit 5.
1, VC, V12, VD1, VS1, V10, VC, V
15 and power supply voltage groups VD and GN supplied from the control unit 1.
The relationship of the potential of D is shown. The power supply unit 5 includes a variable resistor 70 for adjusting the power supply voltage and a resistor 7 connected in series.
A voltage dividing unit 90 that generates a plurality of voltages required for the multiple line simultaneous selection driving method by 1, 72, 73, 74, and 75.
And voltage follower-connected operational amplifiers 76, 77, 78, 79, 80 for impedance-converting the voltage generated at the division terminals of the voltage division unit 90. Where V
10 (= VDDH), a P-type operational amplifier 76 for V11,
77 is connected, VC and VD1 are connected to PN switching type operational amplifiers 78 and 79, and V12 (= VS1) is connected to an N type operational amplifier 80. Here, in the P-type operational amplifiers 76 and 77, as shown in FIG.
The output 210 of 06 is input to the P-type drive transistor 204 in the drive unit 200. On the other hand, the N-type operational amplifier 80
Then, as shown in FIG. 4B, the output 2 of the differential unit 206
10 is an N-type drive transistor 212 in the drive unit 201.
Entered in. Impedance conversion is performed by the P-type operational amplifier for the power supply voltage (the power supply voltage in which the negative load is dominant) in which the polarity of the charge amount that needs to be moved from the liquid crystal element to the operational amplifier in one frame is negative. In addition, for the power supply voltage (the power supply voltage where the positive load is dominant) in which the polarity of the amount of charge that needs to be moved from the liquid crystal element to the operational amplifier within one frame is positive, impedance conversion is performed by the N-type operational amplifier. Be seen. Further, impedance conversion is performed by a PN switching operational amplifier for power supply voltages in which positive and negative loads are equal to each other. In this way, by making the type of the operational amplifier that performs impedance conversion different for each power supply voltage, it is possible to suppress the power consumption consumed by the operational amplifier without lowering the quality of the liquid crystal display.

A semiconductor device that constitutes a liquid crystal element, a signal driver, or the like has a problem of variations in characteristics due to variations in the manufacturing process. Therefore, after assembling the liquid crystal display system in a factory,
Adjustment work for optimizing the drive voltage for the liquid crystal element is required. Further, it is necessary to adjust the driving voltage in order to realize the contrast adjustment in the liquid crystal display. Therefore,
In this embodiment, the value of the power supply voltage such as V10 and V11 is adjusted by adjusting the resistance value of the variable resistor 70, and thereby the drive voltage for the liquid crystal element is adjusted. Variable resistor 7
According to the method of adjusting the resistance value of 0, the drive voltage can be adjusted while accurately maintaining the voltage division ratio in the voltage dividing section 90.

Further, for example, the variable resistor 70 can be constructed by connecting resistors R1 to R4 and switches S1 to S4 as shown in FIG. By doing so, the adjustment signals are controlled by the external CPU or the like, and the switches S1 to S
The resistance value of the variable resistor 70 can be adjusted by turning on and off 4. This also makes it possible to adjust the contrast of the liquid crystal display. Further, it is possible to adjust the power supply voltage by providing the voltage adjusting unit 300 having the configuration shown in FIG. 6 and adjusting the voltage of VDDH which is a reference for generating the liquid crystal drive voltage by the voltage adjusting unit 300. is there. The voltage adjusting unit 300 includes an operational amplifier 302, resistors 304, 30.
6, reference voltage source 308, constant current source 310, switch unit 3
Including 12. According to this configuration, the resistance values R10 and R1
1. The center value of the voltage adjustment is determined by the reference voltage Vref, and a constant current is flown into the resistor 306 using the switch unit 312 and the constant current source 310, so that the voltage adjustment centering on the center value is possible. Become.

The resistors 71 to 75 and the like can be constructed by using transistors in which the drain region and the gate electrode are short-circuited.

Next, the potential relationship of the power supply voltage will be described with reference to FIG. In the present embodiment, since the driving method of simultaneously selecting a plurality of lines is adopted, the power supply voltage range B1 required for the signal driver can be narrowed.
Therefore, as shown in FIG. 3, the power supply voltage range B1 of the signal driver is narrower than the power supply voltage range B2 of the scan driver. Further, in this embodiment, the center voltage VC1 of the voltage range B1 = (V11 + V12) / 2 and the voltage range B1.
Power is supplied so that the center voltage VC2 of 2 = (V10 + V15) / 2 becomes equal. This is realized by generating the center voltage VC = VC1 = VC2 based on the division voltage generated at one division terminal 69, as shown in FIG. Further, in this embodiment, the control unit 1 and the scan driver 3 share the logic power supply voltage VD and the fixed potential GND on the low potential side. On the other hand, the logic power supply voltage of the signal driver 2 is VD1, the fixed potential on the low potential side is VS1 (= V12), and the V of the control unit 1 is V1.
Not common with D and GND. That is, in this embodiment, the logic power supply voltage VD1 of the signal driver is set within the power supply voltage range B1 separately from VD. Specifically, this is realized by generating VD1 based on the division voltage generated at the division terminal 68 of the voltage division unit 90 in FIG. 2, for example.

The power source configuration shown in FIG. 3 is used in the present embodiment for the following reason. First, the center voltage VC1 = V
The reason why C2 is used is to make the characteristics of the PMOS transistor outputting V11 and the characteristics of the NMOS transistor outputting V12 symmetrical so as to facilitate the design. Also, the rising waveform and the falling waveform of the driver output are made substantially symmetrical to reduce the direct current component which is harmful for driving the liquid crystal. When VC1 = VC2, the potential of the power supply voltage may have the relationship shown in FIG. 7, for example. In this case, VC1 = VC2 = GND and V
The polarities of 11 and V12 and the polarities of V10 and V15 are different. However, with the power supply configuration shown in FIG. 7, it is not possible to employ a power supply unit having a simple configuration as shown in FIG. 2 (or FIGS. 5 and 6) to generate the power supply voltage group. Further, in the power supply configuration of FIG. 3, the power supply voltage can be adjusted while maintaining the voltage division ratio accurately by a simple method of adjusting the resistance value of the variable resistor 70. However, in the power supply configuration of FIG. Power supply voltage cannot be adjusted by various methods. This is shown in Figure 3.
Then, the power supply voltage groups supplied to the signal driver 2 and the scan driver 3 all have the same polarity. That is,
When all the power supply voltage groups have the same polarity, the power supply voltage groups V10, V are simply divided by dividing the high-potential-side reference potential VLCD and the low-potential-side fixed potential GND as shown in FIG.
11 and the like can be obtained. Further, only by adjusting the variable resistor 70, the levels of V10, V11, etc. can be adjusted while keeping the voltage division ratio accurately. However, in FIG. 7, since the positive power supply voltage and the negative power supply voltage have to be generated separately, positive and negative polarities are required as reference potentials corresponding to VLCD in FIG. become. In addition, voltage adjustment is also possible with a variable resistor for the positive polarity side,
It is necessary to separately provide a variable resistance on the negative polarity side and separately adjust the voltage on the positive polarity side and the negative polarity side. But,
The characteristics of the variable resistance and the resistance for voltage division may fluctuate due to fluctuations in the manufacturing process, etc., and due to this fluctuation, the voltage division ratio on the positive polarity side and the voltage division ratio on the negative polarity side cannot be kept the same. Occurs. This leads to deterioration of the display quality of the liquid crystal. In this embodiment, such a situation is unlikely to occur because all the power supply voltage groups have the same polarity.

In this embodiment, the logic power supply potential VD1 of the signal driver and the fixed potential VS1 on the low potential side are set to V
The reason why it is not shared with D and GND is as follows.
That is, if the logic power supply potential of the signal driver is VD and the fixed potential on the low potential side is GND, the power supply voltage range of the signal driver becomes wider than in the case of FIG. 3, as shown in FIG. The widening of the power supply voltage range means that the signal driver has to be manufactured by a process having a higher withstand voltage, resulting in an increase in chip area and an increase in cost. In this embodiment, VD1 is set to B
Such a situation is prevented by setting the fixed potential VS1 on the low potential side and separating the fixed potential VS1 from GND.

In this case, the interface of the control signal, the signal data and the scanning data between the control section 1 and the signal driver 2 becomes a problem. From control unit 1 to GND to VD
This is because the logic circuit in the signal driver 2 on the receiving side operates in the voltage range of VS1 to VD1 even though the signal is sent in the voltage range of. Therefore, in this embodiment, this problem is solved by providing the potential converting section 6 as shown in FIG. FIG. 8A shows an example of the configuration of the potential conversion unit 6, and FIG. 8B shows a voltage waveform diagram for explaining the operation. The potential conversion unit 6 includes a capacitor (capacitor) 12 that is capacitively coupled and a DC level transfer unit 58, and the DC level transfer unit 58 is the inverter 3.
Including 20, 322, 324 and a resistor 326. The capacitor 12 cuts the DC component of the input signal A. For example, considering the case where the signal A rises as shown in FIG. 8B, the voltage difference VA = VD−GND is the inverter 320.
Be transmitted to. Then, the output C of the inverter 320 falls and the output D of the inverter 324 rises, and this output D is fed back to the input of the inverter 320 via the resistor 326. The drive capacity of the inverter 324 is set smaller than that of the inverter 320, and
0, 324, and the resistor 326 form a latch circuit. This is because only the AC component (voltage difference VA) of the signal A can be transmitted through the capacitor 12, so it is necessary to hold the voltage obtained by adding this VA to VS1. From the above, VS1 to VD as shown in FIG.
A signal B having an amplitude of 1 is obtained, and a signal E obtained by buffering the signal B with the inverter 322 is obtained.

The problem here is that the VD is the control unit 1
The voltage VD1 is supplied from the voltage supply unit 5 and is constantly constant, whereas the voltage VD1 is supplied from the voltage supply unit 5 and fluctuates by adjusting the variable resistor 70. For example, in 1/240 duty driving which is generally used for a large liquid crystal panel, the voltage range B2 shown in FIG. 3 is about 25V. The voltage adjustment range in this case is about 3V. Therefore, when the voltage is changed by about 3V by the voltage adjustment by the variable resistor 70,
The logic power supply voltage VD1 of the signal driver 2 is 3V / 2.
It changes about 5V = 0.6V. Then, a voltage difference of about 0.6 V occurs between VD1 and VD. Thus V
Even if a voltage difference occurs between D1 and VD, the presence of the capacitor 12 prevents a DC current from flowing between the control unit 1 and the signal driver 2. Further, even if the voltage of the control signal, the signal data, and the scanning data from the control unit 1 becomes lower than VD1 by about 0.6V due to the influence of the voltage adjustment, the voltage difference is provided at the input terminal of the signal driver 2. Threshold voltage of MOS transistor (0.7V)
Lower than). Therefore, a signal can be sufficiently transmitted, and a through current flowing from VD1 to VS1 does not occur in the inverter or the like provided at the input terminal.

As described above, according to the present embodiment, the optimum power supply method can be provided when the range of the power supply voltage applied to the scan driver and the signal driver is different, as in the multiple line simultaneous selection drive method. Further, even when the range of the power supply voltage is different as described above, the drive voltage applied to the liquid crystal element can be arbitrarily adjusted by using the power supply unit 5 having a simple structure.

3. Description of Scan Driver FIG. 9 shows an example of the configuration of the scan driver 3 of the present embodiment using the multiple line simultaneous selection drive method. The scan driver 3 includes a shift register section 36, a combination circuit (drive signal determination circuit) 37, a level shifter section 38, and a voltage selector section 39. The scan driver 3 is based on the FR, DOFF, tY, and DYnm signals from the control unit 1, and supplies the power supply voltages VC, V10, and V15 from the power supply unit 5.
Select either of the three, and output 3 as shown in FIG.
To get 5. Here, the shift register unit 36
Is a D-type flip-flop (hereinafter referred to as DFF)
Is a 4-bit parallel type shift register having the function of simultaneously transferring 4 sets of 2-bit data. The combinational circuit 37 receives the output of the shift register section 36, the FR and DOFF signals, and then receives
The control signal for generating the driver output 35 shown in FIG. This control signal is transmitted to the voltage selector unit 39 via the level shifter unit 38. Then, the voltage selector unit 39 selects one power supply voltage from the three power supply voltage groups VC, V10, and V15 based on the control signal, and the driver output 35 is thereby generated.

The upper bit DY12 of the scan data of 2 bits × 2 lines transferred from the controller 1 is latched by the DFF 20 at the falling edge of the data transfer clock tY, and D
The output of the FF 20 is input to the DFF of the shift register unit at the next stage (not shown) on the right side by 2 bits. Similarly, the lower bit DY11 of the scan data is latched by the DFF21 at the falling edge of the data transfer clock tY, and the output of the DFF21 is input to the DFF of the shift register section at the next stage. With this configuration, as shown in the timing chart of FIG. 11A, the scan data DY of 2 bits × 2 lines is sequentially transferred to the shift register section (36Q1 → 36Q2 → 36) of the next stage.
Can be transferred to Q3). Combination circuit 37
Is EX-OR22, EXNOR23, inverter 2
4, NAND25, NOR26, 27 are included, and D
OFF signal to NAND25, FR signal to EX-NOR
23 is input.

The level shifters 28, 29, 30 included in the level shifter unit 38 have a function of converting the voltage level of the control signal input from the combination circuit 37 from VD to V15 (GND) to V10 to V15. in this case,
Since the voltage difference between V10 and V15 and the voltage difference between VD and V15 are significantly different (see FIG. 3), the level shifter having the configuration shown in FIG. 12A is adopted.

The voltage selector section 39 includes N-channel transistors 31, 33 and P-channel transistors 32, 34.
including. The N-channel transistor 31 is driven by the normal output of the level shifter 29 to select the V15 level, and the P-channel transistor 32 is driven by the inverted output of the level shifter 30 to select the V10 level. Further, the N-channel transistor 33 is driven by the non-inverted output of the level shifter 28 to select the VC level, and the P-channel transistor 34 is connected to the level shifter 2
It is driven by the inverted output of 8 to select the VC level.

In this embodiment, as shown in FIG. 10A, the lower bit DYn1 = H and the upper bit DYn2.
= L, V10 is selected by FR = L, and V15 is selected by FR = H. V15 is VC as shown in FIG.
Is a voltage at a position symmetrical with V10 with respect to the center. When DYn1 = L and DYn2 = H, FR = L and V
15 is selected, and if FR = H, V10 is selected. On the other hand, DYn1 = L, DYn2 = L and DYn1 = H, D
When Yn2 = H, VC is selected regardless of the FR signal. In the present embodiment, the AC drive with VC as the central voltage is realized as described above. Further, in this embodiment, FIG.
As shown in (A), when DOFF = L, FR,
The driver output 35 regardless of the DYn1 and DYn2 signals
Is forced to the VC level. This is because when DOFF = L, the output of the NAND 25 is forced to H, which causes the inputs of the level shifters 28, 29, and 30 to be H,
This is because L and L are set, the transistors 33 and 34 are selected, and the transistors 31 and 32 are unselected. As a result, the display-off function of the liquid crystal display system is realized, as will be described later.

4. Description of Signal Driver FIG. 13 shows an example of the configuration of the signal driver 2 of the present embodiment using the multiple line simultaneous selection driving method. The signal driver 2 includes a shift register unit 59, a data register unit 60, a data latch unit 61, a combination circuit 62, a level shifter unit 63, and a voltage selector unit 67. The signal driver 2 includes FR, DOFF, and L from the control unit 1.
Based on the P, DX, ST and tX signals, one of the power supply voltages VC, V11 and V12 from the power supply unit 5 is selected to obtain the output 57 as shown in FIG. 10 (B). Here, the shift register unit 59 is configured by connecting DFFs in cascade, and has a function of generating a sampling signal. The data register unit 60 samples the signal data DX in DFF according to the sampling signal generated in the shift register unit 59. The data latch unit 61 latches the data sampled by the data register unit 60 based on the LP signal. The combinational circuit 62 receives the output of the data latch section 61 and the FR and DOFF signals and generates a control signal for obtaining the driver output 57 shown in FIG. This control signal is transmitted to the voltage selector unit 67 via the level shifter unit 63. Then, the voltage selector 67 selects one power supply voltage from the power supply voltage groups VC, V11, and V12 based on this control signal, and the driver output 57 is thereby generated.

All the control signals and signal data transferred from the control unit 1 are level-converted from VD to GND to VD1 to VS1 by the capacitive coupling capacitor 12 and the DC level transfer unit 58 and input into the signal driver. The sampling start signal ST is sampled by the DFF 40 at the rising edge of the data transfer clock tX,
Is input to the DFF in the next stage. With this configuration, as shown in the timing chart of FIG.
The ST signal is sequentially transferred to the DFF in the next stage. DFF40
Of the DFF 41, 42 of the data latch unit 60
Input to the K terminal. Then, as shown in FIG. 11B, the lower bit DX1 of the signal data is Q of the DFF 40.
The output is sampled by the DFF 42 at the rising edge.
Similarly, the upper bit DX2 is sampled by the DFF 41 at the rising edge of the Q output of the DFF 40. After that, as shown in FIG. 11B, at the rising edge of the latch pulse signal LP from the control unit 1, the outputs of the DFFs 41 and 42 are D
It is latched by the FFs 43 and 44. Combination circuit 62
Includes EX-NOR 45, 47, EX-OR 46, inverter 48, NAND 49, NOR 50, OR 51. The DOFF signal is NAND 49, and the FR signal is E.
It is input to the X-NOR 47.

The level shifters 64, 65, 66 included in the level shifter unit 63 change the voltage level of the control signal input from the combinational circuit 62 from VD1 to V12 (VS1).
From V11 to V12. In this case, the voltage difference between V11 and V12 and the voltage difference between VD1 and V12 are not so different from each other (see FIG. 3).
The level shifter having the structure shown in FIG. 2 (B) is adopted.

The voltage selector 67 includes N-channel transistors 53 and 55 and P-channel transistors 54 and 56.
including. The N-channel transistor 53 is driven by the normal output of the level shifter 65 to select the V12 level, and the P-channel transistor 54 is driven by the normal output of the level shifter 66 to select the V11 level. The N-channel transistor 55 is driven by the non-inverted output of the level shifter 64 to select the VC level, and the P-channel transistor 56 is connected to the level shifter 6.
It is driven by the inverted output of 4 to select the VC level.

Now, in this embodiment, as shown in FIG. 10B, the lower bit DX1 = L and the upper bit DX2 = L.
In case of, FR = L selects V11, and FR = H selects V1
2 is selected. V12 is a voltage at a position symmetrical to V11 about VC as shown in FIG. Also,
When DX1 = L and DX2 = H, V12 is selected when FR = L, and V11 is selected when FR = H. On the other hand, DX
When 1 = H, DX2 = L and DX1 = H, DX2 = H, VC is selected regardless of the FR signal. In the present embodiment, the AC drive with VC as the central voltage is realized as described above. Further, in this embodiment, as shown in FIG. 10B, when DOFF = L, the driver output 57 is forcibly set to the VC level regardless of the FR, DX1 and DX2 signals. This is because when DOFF = L, the output of the NAND 49 is forced to H, which causes the level shifter 6
The inputs of 4, 65, and 66 are H, L, and H, respectively, and the transistors 55 and 56 are selected.
Is not selected. As mentioned above, DOFF =
In the case of L, the driver output 35 of the scan driver 3 is also forced to the VC level. Therefore, when DOFF = L, the outputs 35, 3 of the signal driver 2 and the scan driver 3
7 becomes the VC level, whereby the voltage applied to the liquid crystal element can be set to "0", and as a result, the display-off function of the liquid crystal display system can be realized.

In the conventional example using the voltage averaging method shown in FIG. 19, the high-potential-side power source voltages GND and V5 are used.
(Or VDDH and V10) can be matched, and the display-off function outputs both the driver output and GN.
It was realized by setting D (V5). On the other hand, in the case of the power supply configuration in which the widths of the voltage ranges B1 and B2 are different as shown in FIG. 3, the power supply voltages V12 and V1 on the high potential side are set.
5 (or V11 and V10) cannot be matched, and the conventional method cannot be used. Therefore, in this embodiment, when DOFF = L, the display-off function is realized by setting the outputs of the drivers to the central voltage VC. In this case, VC is originally a power supply voltage used for driving the liquid crystal, and it is not necessary to generate a new power supply voltage for realizing the display off function.

Further, in the present embodiment, as shown in FIG. 3, the fixed potential on the low potential side of the signal driver is set to V instead of GND.
12 (VS1). This is because the potential converter 6 changes the levels of the control signal and the signal data from VD to
It is realized by converting from GND to VD1 to V12 (VS1). By setting the fixed potential on the low potential side to V12, for example, the substrate potential of the N-channel transistor 53 can also be set to V12, which causes a substrate bias effect (body effect) in the N-channel transistor 53. It can be prevented. When the substrate bias effect occurs, the threshold voltage of the N-channel transistor 53 becomes high, and the characteristics of the N-channel transistor 53 that outputs the V12 level and the P that outputs the V11 level.
The characteristics of the channel transistor 54 are no longer symmetrical. Therefore, in this embodiment, the fixed potential on the low potential side is set to V
By setting the level to 12 levels, the generation of the substrate bias is prevented, the characteristics of the transistors 53 and 54 are made symmetrical, and the design is facilitated. As a result, the rising and falling waveforms of the driver output can be made substantially symmetrical, and the DC component that is harmful for driving the liquid crystal can be reduced. Further, in the present embodiment, since VC is driven by the transistors 55 and 56 having the T-type gate structure, the on resistance can be reduced and the driving capability can be increased.

FIG. 14 shows an example of another configuration of the signal driver. This signal driver is a signal driver with a built-in RAM. In the RAM built-in signal driver, it is not necessary to transfer the signal data when there is no display change, so that the power consumption can be kept low. This signal driver includes a chip enable control circuit 103, a timing circuit 104, a data input control circuit 105, an input register 106, a write register 107, a level shifter unit 108, a frame memory (built-in RAM) 109, a row address register 110, a combinational circuit (driving circuit). Signal determination circuit) 111, latch circuit 112, voltage selector unit 1
Including 13. In this signal driver, the circuits arranged in the low-voltage amplitude operation unit 101 have power supply voltages VD1 to V12 (V
It operates in S1). In this case, the signals such as LP and FR are
Since the level is in the range of VD to GND, the potential conversion unit 5
8 converts the levels to VD1 to V12. Also,
Frame memory 1 arranged in the high voltage amplitude operation unit 102
09, the combinational circuit 111, and the latch circuit 112 operate with the power supply voltages VC to V12, and thus the voltage level of the signal input from the low voltage amplitude operation unit 101 is converted by the level shifter unit 108. With this configuration, the frame memory 109 can be configured to operate in the low-voltage operation amplitude unit 101.
Since it can be operated with a power supply voltage having a voltage difference larger than the power supply voltage of, the frame memory 109 can be configured by a high registration type (high resistance load type) RAM. This makes it possible to significantly reduce the chip area.

(Second Embodiment) Next, a power supply method according to a second embodiment of the present invention will be described. FIG. 15 shows an example of the power supply configuration in the second embodiment. In FIG. 15, the control unit 1, the signal driver 2, the scan driver 3
The fixed potential on the low potential side of is all GND and is common. In this case, since the signal driver 2 operates in the power supply voltage range of V15 to V11, the voltage of the signal driver 2 cannot be lowered as much as that shown in FIG. However, also in the case of FIG. 15, the signal driver 2 operates at a voltage about 2/3 of the power supply voltage of the scan driver 3. Therefore, a semiconductor process having a lower breakdown voltage and higher integration than that of the scan driver 3 can be used, which is advantageous in terms of cost. Also in the case of FIG. 15, the center voltage VC1 of the voltage range D1
And the center voltage VC2 of the voltage range D2 is equal. Therefore, in the display-off function, the outputs of the signal driver 2 and the scan driver 3 are both VC (= VC1, VC
2) It is realized by setting the level. In the case of FIG. 15, the logic circuits in the signal driver 2 are VD to GND.
Therefore, the potential converter 6 as shown in FIG. 1 is unnecessary. Further, in the power supply section shown in FIG. 2, the split terminal 68 and the operational amplifier 79 are unnecessary.

(Third Embodiment) FIG. 16 shows an example of the power supply configuration of the power supply method according to the third embodiment of the present invention. In the case of FIG. 3, the signal driver 2 and the scan driver 3
The power supply voltage of 10 is all positive, but in FIG. 16, V10 (GND), which is the power supply on the high potential side, has a fixed potential, and the power supply voltages are all negative. Then, in the potential conversion unit 6, the level of the control signal or the like is VD (GND) to VSS.
From VD1 (V11) to VS1. Further, in the power supply unit 5, the high potential side is the GND potential, the low potential side is VLCD, and the variable resistor 70 is the low potential side VLC.
Connected to D. The logic power supply voltage VS1 is provided within the voltage range E1 (may be shared with VSS as in FIG. 15).

As described above, VD is fixed potential (GN
D) and when the power supply voltage of the signal driver 2 and the scan driver 3 is set to the negative polarity, the high potential side of the signal driver and the scan driver has a fixed potential.
The semiconductor device will be a P substrate.

(Fourth Embodiment) FIG. 17 shows an example of the power supply configuration of the power supply method according to the fourth embodiment of the present invention. In FIG. 17, as in FIG. 3, the power supply voltages of the signal driver and the scan driver are all positive. However, in the fourth embodiment, the signal driver uses the power supply V11 (V
D1) has a fixed potential, so that the scan driver is configured by a semiconductor device on a P substrate, and the scan driver is a power source V1 on the low potential side.
Since 5 (GND) is set to a fixed potential, the semiconductor device is formed of an N substrate. As described above, the present invention can be applied without any problem even when the polarities of the substrates of the semiconductor devices forming the signal driver and the scan driver are different. Therefore, contrary to FIG. 17, the present invention can be applied to the case where the signal driver is composed of the semiconductor device of the N substrate and the scanning driver is composed of the semiconductor device of the P substrate.

(Fifth Embodiment) FIG. 18 shows an example of the power supply configuration of the power supply method according to the fifth embodiment of the present invention. FIG. 18 is an example of a power supply configuration in the case of simultaneously driving four lines. In the multiple line simultaneous selection driving method, when the number of simultaneous selections is h, the signal driver requires a power supply voltage of (h + 1) level. In FIG. 18, since four lines are simultaneously driven, V11, V12, VC, V
A power supply voltage of 5 levels of 13 and V14 is required. Further, the scan driver requires three-level power supply voltages of V10, VC, and V15. As described above, the present invention can be naturally applied even when the number of lines selected simultaneously is different. When the number of lines to be selected at the same time is increased, it is possible to reduce the voltage difference between the power supply voltages of the signal driver and the scan driver, the driver can be manufactured in a process with a lower breakdown voltage, and the chip area can be reduced.

When three lines are simultaneously selected, the power supply voltage of the signal driver is V11, V12, V13, V1.
It becomes 4. Therefore, in the present invention, in this case, the power supply voltage VC is used only when the display is off. Also, when the number of simultaneously selected lines increases, the required power supply voltage level also increases, but in this case, the number of voltage divisions of the power supply unit is increased to increase the number of division terminals and operational amplifiers connected to them. You can increase it.

The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the gist of the present invention.

For example, in the above embodiment, the case where the liquid crystal driving is performed by the plural line simultaneous selection driving method has been described, but the present invention is not limited to this driving method, and the liquid crystal driving voltage of the signal driver and the scanning driver. It can be widely applied when different.

In the present embodiment, the case where the signal driver has a narrow power supply voltage range and the scan driver has a wide power supply voltage range has been described, but the present invention can be applied to the opposite case.

Further, the structure of the power supply voltage supply means (power supply unit) is not limited to that described in the present embodiment, and various structures equivalent to this can be adopted. For example, the means for adjusting the voltage is not limited to the variable resistor described in the above embodiment.

Further, the position of the logic power supply voltage is not limited to the positions of VD1 and VS1 described in the present embodiment, but can be set to various positions. In this case, the positions of the division terminals for extracting these logic power supply voltages also differ.

The potential converting means is not limited to the structure described in this embodiment, and various structures equivalent to this can be adopted.

[0068]

As described above, according to the present invention, each voltage value of the power supply voltage group can be adjusted by the adjusting means having a simple structure, which leads to reduction of the number of parts and improvement of reliability.
Even in this case, according to the present invention, the voltage ratio of the power supply voltage can be accurately maintained. As described above, the present invention is an optimum power supply method for, for example, a multiple line simultaneous selection drive method.

Further, according to the present invention, the first and second power supply voltage groups can be generated with a very simple structure, and the first and second center voltages can be made the same.

Further, according to the present invention, the voltage values of the first and second power supply voltage groups can be adjusted only by adjusting the value of the reference potential for generating the liquid crystal drive voltage. As a result, after assembling the system in a factory or the like, it is possible to optimize the drive voltage for the liquid crystal element and adjust the contrast in the liquid crystal display. Note that as the adjustment method in this case, for example, a method using a variable resistor or a method using a voltage adjusting unit configured by an operational amplifier or the like can be considered.

Further, according to the present invention, since the logic power supply voltage is set within the first power supply voltage range, the width of the operating power supply voltage of one driver can be narrowed. As a result, a lower withstand voltage process can be adopted as the manufacturing process of one driver, and the chip area can be reduced and the cost can be reduced.

Further, according to the present invention, the fixed potential power source of one driver and the fixed potential power source of the other driver are separated, so that the width of the operating power source voltage of one driver can be narrowed. As a result, a lower withstand voltage process can be adopted as the manufacturing process of one driver, and the chip area can be reduced and the cost can be reduced.

Further, according to the present invention, it becomes possible to normally transmit the control signal and the like to one driver.

Further, according to the present invention, the potential level can be easily converted by using the capacitive coupling capacitor.

Further, according to the present invention, the display-off function is realized by using the first and second center voltages which are always the same value even when the voltage value of the power supply voltage group is adjusted. , It is not necessary to generate a new voltage to realize this function.

[0076]

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display system according to a first embodiment.

FIG. 2 is an example of a configuration of a power supply unit.

FIG. 3 is a diagram showing a potential relationship of power supply voltage groups used in the first embodiment.

4A and 4B are examples of configurations of a P-type operational amplifier and an N-type operational amplifier.

FIG. 5 is another example of the configuration of the power supply unit.

FIG. 6 is another example of the configuration of the power supply unit.

FIG. 7 is a diagram showing a potential relationship of a power supply voltage group when a central potential is GND.

FIG. 8A is an example of a configuration of a potential conversion unit, and FIG. 8B is a voltage waveform diagram for explaining the operation.

FIG. 9 is a diagram showing an example of a configuration of a scan driver.

10A is a diagram showing a relationship between a control signal and a data signal in a scan driver and a driver output, and FIG. 10B is a relationship between a control signal and a data signal in a signal driver and a driver output. FIG.

11A and 11B are timing charts for explaining the operations of the scan driver and the signal driver.

12A and 12B are diagrams showing an example of the configuration of a level shifter.

FIG. 13 is a diagram showing an example of a configuration of a signal driver.

FIG. 14 is a diagram showing another example of the configuration of the signal driver.

FIG. 15 is a diagram showing a potential relationship among power supply voltage groups in the second embodiment.

FIG. 16 is a diagram showing a potential relationship of power supply voltage groups in the third embodiment.

FIG. 17 is a diagram showing a potential relationship among power supply voltage groups in the fourth embodiment.

FIG. 18 is a diagram showing a potential relationship among power supply voltage groups in the fifth embodiment.

FIG. 19 is a diagram showing a potential relationship of a power supply voltage group when a conventional voltage averaging method is used.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control part 2 signal driver 3 scan driver 4 liquid crystal panel 5 power supply part 6 electric potential conversion part 10 output of signal driver 11 output of scan driver 12 capacitors (capacitors) 20, 21, 40, 41 42, 43, 44 DFF 22, 46 EX-OR 23, 45, 47 EX-NOR 24, 48, 52 Inverter 25, 49 NAND 26, 27, 50, 51 NOR 28, 29, 30 Level shifter 31, 33, 53, 55 N-channel transistor 32, 34, 54, 56 P-channel transistor 35, 57 Output terminal 36, 59 Shift register section 37, 62 Combination circuit 38 Level shifter section 39, 67 Voltage selector section 58 DC level transfer section 60 Data register section 61 Data latch section 70 Variable resistance 71, 72 , 73, 74 , 75 resistance 76, 77 P-type operational amplifier 78, 79 PN switching operational amplifier 80 N-type operational amplifier

Claims (12)

[Claims] 1. A signal driver for applying a drive voltage to the signal electrode of a matrix panel in which display pixels are arranged in a matrix and a plurality of signal electrodes and scanning electrodes are arranged to intersect, and the scanning electrode. A liquid crystal display system including a scan driver that applies a drive voltage to the scan driver, and a power supply unit that supplies a power supply voltage to the signal driver and the scan driver, wherein the power supply unit includes a first power supply. Means for supplying a first power supply voltage group of the same polarity having a voltage range to one of the signal driver or the scan driver, and a second power supply voltage wider than the first power supply voltage range Means for supplying a second power supply voltage group having the same range and having the same polarity to the other driver different from the one, and a center voltage of the first power supply voltage range. The liquid crystal display system, characterized in that it comprises one center voltage and, and means for the same and a second center voltage is the center voltage of the second power supply voltage range. 2. The power supply means according to claim 1, wherein the power supply means divides a fixed potential and a reference potential for generating a liquid crystal drive voltage and generates a division voltage at a division terminal. Means for generating a group of power supply voltages,
And a means for making the first and second center voltages equal to each other by generating the first and second center voltages based on the division voltage generated at one of the division terminals. Display system. 3. The value of the divided voltage is adjusted by adjusting the value of the reference potential for generating the liquid crystal drive voltage, and the voltage values of the first and second power supply voltage groups are adjusted according to claim 2. A liquid crystal display system comprising means. 4. The logic power supply for one of the drivers according to claim 1, wherein the power supply means supplies a voltage within the first power supply voltage range to the first power supply voltage group. A liquid crystal display system comprising means for supplying a voltage. 5. The low-potential-side or high-potential-side fixed potential power source of the one driver to which the first power source voltage group is supplied, and the second power source voltage according to claim 1. A liquid crystal display system, wherein a fixed potential power source on a low potential side or a high potential side of the other driver to which the group is supplied is separated. 6. The one driver according to claim 4, further comprising a unit that outputs at least a control signal to the signal driver and the scan driver, and the first power supply voltage group is supplied. The potential level of the control signal output to the first
2. A liquid crystal display system comprising: a potential conversion means for converting the level into a power supply voltage range. 7. The liquid crystal display system according to claim 6, wherein the potential conversion means includes a capacitive coupling capacitor for cutting a DC component. 8. The drive voltage output from the signal driver and the scan driver when a predetermined external input signal is input, according to claim 1, A liquid crystal display system comprising means for setting the same voltage as the center voltage. 9. A signal driver for applying a drive voltage to the signal electrode of a matrix panel in which display pixels are arranged in a matrix and a plurality of signal electrodes and scanning electrodes are arranged to intersect, and the scanning electrode. A power supply method used in a liquid crystal display system, comprising: a scan driver for applying a drive voltage to the scan driver; and a power supply means for supplying a power supply voltage to the signal driver and the scan driver. A first power supply voltage group having the same polarity and having a power supply voltage range is supplied to one of the signal driver or the scan driver, and a second power supply voltage range wider than the first power supply voltage range. A second power supply voltage group having the same polarity to the other driver different from the first power supply voltage group, and a first center voltage that is a center voltage of the first power supply voltage range. , Power supply method characterized by the second center voltage is the center voltage of the second power supply voltage range the same. 10. The power supply according to claim 9, wherein a voltage within the first power supply voltage range is supplied as a logic power supply voltage of the one driver to which the first power supply voltage group is supplied. Method. 11. The low potential side or high potential side fixed potential power source of the one driver to which the first power source voltage group is supplied, and the second power source voltage according to claim 9. A power supply method, characterized in that the fixed potential power supply on the low potential side or the high potential side of the other driver to which the group is supplied is separated. 12. The driving voltage output from the signal driver and the scan driver when a predetermined external signal is input according to claim 9,
A power supply method characterized by setting the same voltage as the first and second center voltages.