CN113725294B - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN113725294B CN113725294B CN202111028226.9A CN202111028226A CN113725294B CN 113725294 B CN113725294 B CN 113725294B CN 202111028226 A CN202111028226 A CN 202111028226A CN 113725294 B CN113725294 B CN 113725294B
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 108091006146 Channels Proteins 0.000 description 28
- 238000001312 dry etching Methods 0.000 description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention provides a gallium nitride-based insulated gate bipolar transistor and a preparation method thereof, wherein the transistor comprises the following components: an n-type collector region; the p-type base region is arranged on the n-type collector region and exposes part of the n-type collector region; the n-type emitter region is arranged on the p-type base region and exposes part of the p-type base region; the voltage-controlled channel layer is arranged on part of the n-type collector region; the contact layer is arranged on the voltage-controlled channel layer; and the inner electrode metal layer is arranged on part of the p-type base region and part of the contact layer.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to an insulated gate bipolar transistor and a preparation method thereof.
Background
Conventional insulated gate transistors are silicon devices with performance approaching the material limit, and gallium nitride based semiconductor materials are a good choice for further device performance improvement. The gallium nitride-based semiconductor material has the characteristics of large band gap width, high critical breakdown electric field strength, high electron saturation drift speed and the like, has obvious advantages in the fields of medium and low power, radio frequency electrons, photoelectrons and the like, and is one of important research directions in the semiconductor field.
At present, the gallium nitride-based insulated gate bipolar transistor and the traditional silicon-based insulated gate bipolar transistor have the problems that the preparation difficulty of p-type materials with high carrier concentration is high, the contact of metal electrodes on the p-type materials is poor, the dislocation density of the materials is difficult to reduce and the like, and the withstand voltage and on-resistance parameters of the insulated gate bipolar transistor are seriously restricted.
Disclosure of Invention
In view of the above, the present invention provides a gan-based insulated gate bipolar transistor and a method for manufacturing the same, so as to solve at least one of the above problems.
In order to achieve the above object, the present invention provides a gallium nitride-based insulated gate bipolar transistor and a method for manufacturing the same, wherein the transistor comprises: an n-type collector region; the p-type base region is arranged on the n-type collector region and exposes part of the n-type collector region; the n-type emitter region is arranged on the p-type base region and exposes part of the p-type base region; the voltage-controlled channel layer is arranged on part of the n-type collector region; the contact layer is arranged on the voltage-controlled channel layer; and the inner electrode metal layer is arranged on part of the p-type base region and part of the contact layer.
According to an embodiment of the present invention, further comprising: a substrate; the buffer layer is arranged on the substrate, and the n-type collector region is arranged on the buffer layer; an emitter metal layer disposed on the n-type emitter region; the collector metal layer is arranged on part of the n-type collector region; the insulating layer is arranged on the side surfaces of the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer and the voltage-controlled channel layer and part of the surface of the n-type collector region; the grid metal layer is arranged on part of the insulating layer.
According to an embodiment of the invention, the inner electrode metal layer is arranged between the emitter metal layer and the gate metal layer; the grid electrode metal layer is arranged between the inner electrode metal layer and the collector electrode metal layer.
According to the embodiment of the invention, the doping elements of the n-type collector region and the n-type emitter region are Si, and the doping concentration is 1×10 16～1×1022/cm3; the doping element of the p-type base region is Mg, and the doping concentration is 1 multiplied by 10 16～1×1022/cm3; the materials of the n-type collector region, the n-type emitter region and the p-type base region comprise: gaN or AlGaN.
According to the embodiment of the invention, the thickness of the n-type collector region is 100-500 nm; the thickness of the p-type base region is 50-100 nm; the thickness of the n-type emission region is 20-200 nm.
According to an embodiment of the invention, wherein the buffer layer material comprises: alGaN or AlN.
According to an embodiment of the invention, wherein the substrate comprises one of: sapphire, silicon carbide, glass.
The invention also provides a preparation method of the insulated gate bipolar transistor, which comprises the following steps: growing a p-type base region on the n-type collector region; growing an n-type emitter region on the p-type base region; etching part of the n-type reflecting region until part of the p-type base region is exposed, so as to form a first mesa; etching part of the p-type base region until part of the n-type collector region is exposed, so as to form a second mesa; sequentially growing a voltage-controlled channel layer and a contact layer on a part of n-type collector region at one side of a part of the second mesa region; and growing an inner electrode metal layer on part of the p-type base region and part of the contact layer of part of the first mesa region.
According to an embodiment of the present invention, before growing the p-type base region on the n-type collector region, further comprises: growing a buffer layer on a substrate; growing an n-type collector region on the buffer layer; the method further comprises the following steps of growing an inner electrode metal layer on part of the p-type base region and part of the contact layer: preparing a collector metal layer on a part of the n-type collector region on the other side of the part of the first mesa region; preparing an emitter metal layer on the n-type emitter region; growing an insulating layer on the side surfaces of the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer and the voltage-controlled channel layer and part of the surface of the n-type collector region; and growing a gate electrode metal layer on a part of the insulating layer.
According to an embodiment of the invention, the inner electrode metal layer is arranged between the emitter metal layer and the gate metal layer; the grid electrode metal layer is arranged between the inner electrode metal layer and the collector electrode metal layer.
From the above technical solution, it can be seen that the insulated gate bipolar transistor provided by the present invention has at least one of the following advantages:
(1) The insulated gate bipolar transistor provided by the invention utilizes the inner electrode and the insulated gate n-type channel, so that the npn-type bipolar transistor is controlled by positive pressure, the conduction performance of the device is improved, and the on resistance and loss of the device are effectively reduced.
(2) The insulated gate bipolar transistor provided by the invention reduces the requirement on the p-type layer on the premise of ensuring the functionality of the device, and reduces the preparation difficulty of the insulated gate bipolar transistor device.
Drawings
Fig. 1 schematically illustrates a schematic structure of an insulated gate bipolar transistor according to an embodiment of the present invention;
fig. 2 schematically shows a flowchart of a method of manufacturing an insulated gate bipolar transistor according to an embodiment of the invention.
[ Reference numerals description ]
An n-type collector region 101; a p-type base region 102; an n-type emitter region 103; a voltage controlled channel layer 104; a contact layer 105; an inner electrode metal layer 106; an emitter metal layer 107; a collector metal layer 108; a gate metal layer 109; an insulating layer 110; a substrate 111; a buffer layer 112.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
In the related technology, the preparation difficulty of p-type materials of the traditional pnp silicon-based insulated gate bipolar transistor is high, and the contact of metal electrodes on the p-type materials is poor; and the gallium nitride based npn type insulated gate bipolar transistor adopts negative pressure control, so that the circuit of the device is complex, the conduction performance of the device is reduced, and the on resistance of the device is increased.
Therefore, the invention provides the gallium nitride-based npn type insulated gate bipolar transistor, which adopts a positive voltage to turn on a device, realizes the control of the npn type bipolar transistor by the n type channel insulated gate, and improves the conduction performance of the device.
Fig. 1 schematically shows a schematic structure of an insulated gate bipolar transistor according to an embodiment of the present invention.
As shown in fig. 1, the insulated gate bipolar transistor may include: the n-type collector region 101, the p-type base region 102, the n-type emitter region 103, the voltage-controlled channel layer 104, the contact layer 105, the internal electrode metal layer 106 may further include: substrate 111, buffer layer 112, emitter metal layer 107, collector metal layer 108, gate metal layer 109, and insulating layer 110. The following describes the configuration of each part of the insulated gate bipolar transistor in detail.
Substrate 111, the material of substrate 111 may include, but is not limited to, one of: sapphire, silicon carbide, glass.
The buffer layer 112 is disposed on the substrate 111.
Materials for buffer layer 112 may include, but are not limited to, according to embodiments of the present invention: alGaN or AlN.
According to the embodiment of the invention, the buffer layer is introduced to realize stress release and dislocation filtering, so that lattice mismatch is reduced, and an epitaxial layer with higher crystal quality is obtained.
The n-type collector region 101 is disposed on the buffer layer 112.
According to an embodiment of the present invention, the material of n-type collector region 101 is a gallium nitride-based material, which may include, but is not limited to: gaN or AlGaN.
According to an embodiment of the present invention, the doping element of the n-type collector region 101 may be Si, and the doping concentration may be 1×10 16～1×1022/cm3.
According to an embodiment of the present invention, the thickness of the n-type collector region 101 may be 100 to 500nm.
The p-type base region 102 is disposed on the n-type collector region 101, and exposes a portion of the n-type collector region.
According to an embodiment of the present invention, the material of the p-type base region 102 is a gallium nitride-based material, which may include, but is not limited to: gaN or AlGaN.
According to an embodiment of the present invention, the doping element of the p-type base region 102 may be Mg, and the doping concentration may be 1×10 16～1×1022/cm3.
The thickness of the p-type base region 102 may be 50-100 nm according to embodiments of the present invention.
The n-type emitter region 103 is disposed on the p-type base region 102, exposing a portion of the p-type base region.
According to an embodiment of the present invention, the material of n-type emitter region 103 is a gallium nitride-based material, which may include, but is not limited to: gaN or AlGaN.
According to an embodiment of the present invention, the doping element of the n-type emitter region 103 may be Si, and the doping concentration may be 1×10 16～1×1022/cm3.
According to an embodiment of the present invention, the thickness of the n-type emitter region 103 may be 20 to 200nm.
According to an embodiment of the present invention, the n-type collector region 101 and the p-type base region 102 form a second mesa, and a region of the second mesa includes an exposed portion of the n-type collector region; the p-type base region 102 and the n-type emitter region 103 form a first mesa whose region includes the exposed portion of the p-type base region.
The voltage controlled channel layer 104 is disposed on a portion of the n-type collector region.
According to an embodiment of the present invention, the voltage-controlled channel layer 104 is an undoped gallium nitride material, and is disposed on a portion of the n-type collector region, which may be disposed on a p-type base side surface and on a surface of an exposed portion of the n-type collector region included in the second mesa region near the p-type base side surface.
According to an embodiment of the present invention, the thickness of the voltage controlled channel layer 104 is less than the thickness of the p-type base region 102.
According to embodiments of the present invention, the voltage controlled channel layer 104 creates an inversion layer through which an electron channel is formed.
The contact layer 105 is disposed on the voltage controlled channel layer 104.
According to an embodiment of the present invention, the contact layer is made of n-type gallium nitride material, and the sum of the thickness of the contact layer 105 and the thickness of the voltage-controlled channel layer 104 may be the thickness of the p-type base region.
According to the embodiment of the invention, the contact layer 105 can be used for improving ohmic contact between the inner electrode metal layer 106 and the voltage-controlled channel layer 104, so as to realize current expansion.
And an inner electrode metal layer 106 disposed on a part of the p-type base region and a part of the contact layer.
According to an embodiment of the invention, an inner electrode metal layer is provided on a side of the first mesa region remote from the part of the p-type base region of the n-type emitter region and on a part of the contact layer.
An emitter metal layer 107 is disposed on the n-type emitter region.
According to embodiments of the present invention, the emitter metal layer 107 disposed on the n-type emitter region may include overlying a portion of the n-type emitter region, or overlying the n-type emitter region entirely. The larger the area covered on the n-type emitter region, the better the current conductivity. In connection with the actual fabrication process, it is preferable that the emitter metal layer 107 covers a portion of the n-type emitter region.
A collector metal layer 108 is disposed on a portion of the n-type collector region.
According to an embodiment of the invention, a collector metal layer 108 is provided on the other side of the second mesa region from the exposed portion of the p-type base region, the n-type collector region.
And an insulating layer 110 disposed on the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer, the voltage-controlled channel layer, and a part of the surface of the n-type collector region.
According to an embodiment of the present invention, the material of the insulating layer 110 may include, but is not limited to: si 3N4SiO2.
The gate metal layer 109 is disposed on a portion of the insulating layer.
According to the embodiment of the present invention, the gate metal layer 109 may be disposed on a portion of the surface of the insulating layer 110 covering the upper portion of the contact layer 105, a portion of the surface of the contact layer 105 and the voltage-controlled channel layer 104, and a portion of the surface of the n-type collector region, or may be disposed on a portion of the surface of the insulating layer 110 covering the surface of the contact layer 105 and the surface of the sub-controlled channel layer 104, and may be adjusted according to practical process requirements, which is not limited herein.
According to an embodiment of the present invention, the materials of the inner electrode metal layer 106, the emitter metal layer 107, the collector metal layer 108, and the gate metal layer 109 may include, but are not limited to, at least one of the following: ni, al, au, pt, ti, cr, cu, etc.
According to an embodiment of the present invention, the inner electrode metal layer 106 is disposed between the emitter metal layer 107 and the gate metal layer 109; the gate metal layer 109 is disposed between the inner electrode metal layer 106 and the collector metal layer 108.
According to an embodiment of the present invention, the collector metal layer 108, the inner electrode metal layer 106, the gate metal layer 109, and the emitter metal layer 107 have a predetermined distance from each other to avoid a short circuit.
According to the embodiment of the invention, the collector metal layer 108 of the gallium nitride-based npn type insulated gate bipolar transistor is positively charged, and the emitter metal layer 107 is grounded. When the electrode voltage of the gate metal layer 109 is 0, the device is turned off. When a sufficiently large positive voltage is applied to the gate metal layer 109, undoped gallium nitride of the voltage-controlled channel layer 104 is affected by the gate metal layer 109, creating an inversion layer, forming an electron channel. The current enters the n-type collector region 101 from the collector metal layer 108, passes through an electron channel formed by the inversion layer of the voltage-controlled channel layer 104, reaches the contact layer 105, and then enters the p-type base region 102 through the inner electrode metal layer 106 to form injection current. After enough injection current enters the p-type base region 102, the p-type base region 102 forms a bipolar channel, the current enters the n-type collector region from the collector metal layer 103, passes through the bipolar channel of the p-type base region 102, enters the n-type emitter region, finally flows out of the emitter metal layer 107, and the device is formed to be turned on.
According to the embodiment of the invention, the insulated gate bipolar transistor provided by the invention realizes the positive pressure control of the npn bipolar transistor of the n-type channel insulated gate by utilizing the fact that the n-type mobility and the carrier concentration in the gallium nitride-based material are higher than those of the p-type, so that the conduction performance of a device is improved, and the on resistance and the loss of the device are effectively reduced; on the other hand, on the premise of ensuring the functionality of the device, the requirement on a p-type layer is reduced, and the preparation difficulty of the insulated gate bipolar transistor device is reduced.
Fig. 2 schematically shows a flowchart of a method of manufacturing an insulated gate bipolar transistor according to an embodiment of the invention.
As shown in fig. 2, the method includes operations S201 to S206.
In operation S201, a p-type base region is grown on an n-type collector region.
In operation S202, an n-type emitter region is grown on a p-type base region.
According to the embodiment of the invention, a p-type base region and an n-type emitter region are sequentially epitaxially grown on an n-type collector region by a metal chemical vapor deposition method.
According to an embodiment of the present invention, the n-type collector region, the p-type base region, and the n-type emitter region are all gallium nitride-based materials, which may include, but are not limited to: gaN or AlGaN.
According to an embodiment of the present invention, the doping elements of the n-type collector region and the n-type emitter region may be Si, the doping concentrations may be 1×10 16～1×1022/cm3, the epitaxial thickness of the n-type collector region may be 100 to 500nm, and the epitaxial thickness of the n-type emitter region may be 20 to 200nm.
According to the embodiment of the invention, the doping element of the p-type base region can be Mg, the doping concentration can be 1 multiplied by 10 16～1×1022/cm3, and the epitaxial thickness of the p-type base region can be 50-100 nm.
In operation S203, a portion of the n-type reflective region is etched until a portion of the p-type base region is exposed, forming a first mesa.
In operation S204, a portion of the p-type base region is etched until a portion of the n-type collector region is exposed, forming a second mesa.
According to the embodiment of the invention, a part of the n-type reflecting region is etched until a part of the p-type base region is exposed by photoetching or etching, and a first mesa is formed in the p-type base region and the n-type emitting region; and etching part of the p-type base region until part of the n-type collector region is exposed, and forming a second mesa in the n-type collector region and the p-type base region.
According to the embodiment of the invention, the first mesa and the second mesa formed by the n-type emitter region and the p-type base region, and the p-type base region and the n-type collector region are stepped.
According to an embodiment of the invention, the etching may include, but is not limited to: dry etching and wet etching.
According to the embodiment of the invention, when wet etching is adopted, surface roughness and defects introduced by dry etching can be avoided, so that the quality of an epitaxial layer prepared on a subsequent table top is improved, but the pattern transfer precision is poor; and the dry etching pattern transfer precision is high, but etching defects are introduced. Preferably, a mixed etching method of dry etching and wet etching can be adopted, so that the pattern transfer precision is ensured, and surface roughness and defects introduced by dry etching are avoided.
In operation S205, a voltage controlled channel layer and a contact layer are sequentially grown on a portion of the n-type collector region on one side of a portion of the second mesa region.
According to the embodiment of the invention, a voltage-controlled channel layer and a contact layer are sequentially grown on a part of an n-type collector region through a selective area secondary epitaxy technology.
According to an embodiment of the invention, the voltage-controlled channel layer is an undoped gallium nitride layer; the contact layer is an n-type doped gallium nitride layer.
In operation S206, an inner electrode metal layer is grown on a portion of the p-type base region and a portion of the contact layer of a portion of the first mesa region.
According to the embodiment of the invention, an inner electrode metal layer is prepared on a part of the p-type base region and a part of the contact layer through photoetching and metal evaporation, and then high-temperature rapid annealing is carried out.
According to an embodiment of the present invention, the material of the internal electrode metal layer may include, but is not limited to, at least one of: ni, al, au, pt, ti, cr, cu.
According to an embodiment of the present invention, the annealing temperature may be 800 to 900 ℃ and the annealing time may be 30 to 60 seconds.
According to an embodiment of the present invention, before growing the p-type base region on the n-type collector region, further comprises: growing a buffer layer on a substrate; an n-type collector region is grown on the buffer layer.
According to an embodiment of the present invention, after growing the inner electrode metal layer on the part of the p-type base region and the part of the contact layer, the method further comprises:
a collector metal layer is prepared on a portion of the n-type collector region on the other side of the portion of the second mesa region.
Preparing an emitter metal layer on the n-type emitter region;
growing an insulating layer on the side surfaces of the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer and the voltage-controlled channel layer and part of the surface of the n-type collector region;
And growing a gate electrode metal layer on a part of the insulating layer.
According to the embodiment of the invention, the process parameters for preparing the collector metal layer, the emitter metal layer and the gate electrode metal layer are the same as those for preparing the inner electrode metal layer, and are not repeated here.
According to embodiments of the present invention, the materials of the electrode metal layer, the emitter metal layer, and the gate electrode metal layer may include, but are not limited to, at least one of the following: ni, al, au, pt, ti, cr, cu.
According to the embodiment of the invention, the buffer layer can be prepared by adopting a magnetron sputtering technology and is between the substrate and the n-type doped collector region, so as to relieve lattice mismatch and thermal mismatch of the heterogeneous substrate and the n-type doped collector region and promote the growth of a subsequent epitaxial layer.
According to the embodiment of the invention, the insulated gate bipolar transistor provided by the invention realizes the positive pressure control of the npn bipolar transistor of the n-type channel insulated gate by utilizing the fact that the n-type mobility and the carrier concentration in the gallium nitride-based material are higher than those of the p-type, so that the conduction performance of a device is improved, and the on resistance and the loss of the device are effectively reduced; on the other hand, on the premise of ensuring the functionality of the device, the requirement on a p-type layer is reduced, and the preparation difficulty of the insulated gate bipolar transistor device is reduced.
It should be noted that, in the embodiments, directional terms, such as "upper", "lower", "front", "rear", "left", "right", etc., refer to the directions of the drawings only, and are not intended to limit the scope of the present invention. Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present invention.
And the shapes and dimensions of the various elements in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of embodiments of the present invention. Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the method of the invention should not be interpreted as reflecting the intention: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present invention, and are not meant to limit the scope of the invention, but to limit the invention thereto.
Claims (10)
1. An insulated gate bipolar transistor comprising:
An n-type collector region;
the p-type base region is arranged on the n-type collector region, and part of the n-type collector region is exposed;
The n-type emitter region is arranged on the p-type base region and exposes part of the p-type base region; the n-type collector region, the p-type base region and the n-type emitter region are all made of gallium nitride-based materials; the n-type collector region and the p-type base region form a second table top, the p-type base region and the n-type emitter region form a first table top, and a step shape is formed between the first table top and the second table top;
The voltage-controlled channel layer is arranged on the side surface of the p-type base region and part of the n-type collector region included in the second mesa region close to the side surface of the p-type base region, wherein the voltage-controlled channel layer is made of undoped gallium nitride material;
The contact layer is arranged on the voltage-controlled channel layer, wherein the contact layer is made of n-type gallium nitride material;
The inner electrode metal layer is arranged on part of the p-type base region and part of the contact layer of the first mesa region, which are far away from the n-type emitter region;
an emitter metal layer disposed on the n-type emitter region;
A collector metal layer disposed on a portion of the n-type collector region;
The insulating layer is arranged on the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer, the side surface of the voltage-controlled channel layer and part of the surface of the n-type collector region;
And the grid metal layer is arranged on part of the insulating layer.
2. The insulated gate bipolar transistor of claim 1, further comprising:
A substrate;
And the buffer layer is arranged on the substrate, and the n-type collector region is arranged on the buffer layer.
3. The insulated gate bipolar transistor of claim 1, wherein,
The inner electrode metal layer is arranged between the emitter metal layer and the grid metal layer;
the gate metal layer is disposed between the inner electrode metal layer and the collector metal layer.
4. The insulated gate bipolar transistor according to any one of claim 1 to 2, wherein,
The doping elements of the n-type collector region and the n-type emitter region are Si, and the doping concentration is 1 multiplied by 10 16~1×1022/cm3;
the doping element of the p-type base region is Mg, and the doping concentration is 1 multiplied by 10 16~1×1022/cm3;
the materials of the n-type collector region, the n-type emitter region and the p-type base region all comprise: gaN or AlGaN.
5. The insulated gate bipolar transistor according to any one of claim 1 to 2, wherein,
The thickness of the n-type collector region is 100-500 nm; the thickness of the p-type base region is 50-100 nm; the thickness of the n-type emission region is 20-200 nm.
6. The insulated gate bipolar transistor of claim 2, wherein the buffer layer material comprises: alGaN or AlN.
7. The insulated gate bipolar transistor of claim 2, wherein the substrate comprises one of: sapphire, silicon carbide, glass.
8. A method for manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 7, comprising:
Growing a p-type base region on the n-type collector region;
Growing an n-type emitter region on the p-type base region;
etching part of the n-type emitter region until part of the p-type base region is exposed, so as to form a first mesa;
etching part of the p-type base region until part of the n-type collector region is exposed, so as to form a second mesa;
Sequentially growing a voltage-controlled channel layer and a contact layer on part of the n-type collector region at one side of part of the second mesa region;
And growing an inner electrode metal layer on part of the p-type base region and part of the contact layer of part of the first mesa region.
9. The method of manufacturing according to claim 8, further comprising, before growing the p-type base region on the n-type collector region:
Growing a buffer layer on a substrate;
Growing the n-type collector region on the buffer layer;
the method further comprises the following steps of growing an inner electrode metal layer on part of the p-type base region and part of the contact layer:
preparing a collector metal layer on a part of the n-type collector region on the other side of a part of the second mesa region;
preparing an emitter metal layer on the n-type emitter region;
Growing an insulating layer on the n-type emitter region, the p-type base region, the inner electrode metal layer, the contact layer, the side surface of the voltage-controlled channel layer and part of the surface of the n-type collector region;
And growing a gate metal layer on part of the insulating layer.
10. The manufacturing method according to claim 9, wherein the internal electrode metal layer is provided between the emitter metal layer and the gate metal layer; the gate metal layer is disposed between the inner electrode metal layer and the collector metal layer.
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