CN113725160A - Ultrathin wafer front cutting process - Google Patents
Ultrathin wafer front cutting process Download PDFInfo
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- CN113725160A CN113725160A CN202111021765.XA CN202111021765A CN113725160A CN 113725160 A CN113725160 A CN 113725160A CN 202111021765 A CN202111021765 A CN 202111021765A CN 113725160 A CN113725160 A CN 113725160A
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- wafer
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- glass carrier
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- 238000005520 cutting process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000011521 glass Substances 0.000 claims abstract description 21
- 238000003698 laser cutting Methods 0.000 claims abstract description 15
- 239000012790 adhesive layer Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 abstract description 4
- 239000010432 diamond Substances 0.000 abstract description 4
- 238000013467 fragmentation Methods 0.000 abstract description 3
- 238000006062 fragmentation reaction Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 47
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/70—Auxiliary operations or equipment
- B23K26/702—Auxiliary equipment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Mechanical Engineering (AREA)
- Laser Beam Processing (AREA)
Abstract
The invention discloses an ultrathin wafer front cutting process, which comprises the following steps: s1, completing the high temperature process of the wafer, bonding the front surface of the wafer with the glass carrier plate, and then performing the back wafer process; s2, bonding the back of the wafer with the glass carrier plate, then debonding the front glass carrier plate, and removing the adhesive layer; s3, completing the front wafer process; s4, etching the front surface of the wafer by plasma, and etching and removing Si at the cutting lines to the back metal by utilizing the different etching rates of the metal and the Si; and S5, performing laser cutting on the front surface of the wafer to finish the cutting of the ultrathin wafer. According to the invention, the etching rate of the plasma to the Si sheet and the metal is different, the cutting channel is etched on the front surface of the wafer until the back metal is exposed, and then the back metal is cut off by laser cutting, so that the cutting of the ultrathin metal is completed, and the problems of the fragmentation of the ultrathin metal and the low efficiency and poor accuracy of laser cutting caused by the cutting of the diamond cutter wheel are solved.
Description
Technical Field
The invention relates to the technical field of wafer processing, in particular to a front cutting process of an ultrathin wafer.
Background
In a semiconductor process, a wafer (wafer) is cut into individual chips (die), and the die are then formed into different semiconductor package structures. With the development of the semiconductor industry, in order to meet the requirements of miniaturization, multifunctionality and intellectualization of electronic devices, the demand for ultra-thin wafers is increasing day by day.
The wafer cutting method in the prior art generally comprises a half-cutting and half-cracking process mainly comprising a back water jet and a laser process. When the existing process operates an ultrathin wafer, the wafer is easy to warp after being ground, and the wafer is easy to crack during subsequent processing operation. Particularly, when a traditional diamond knife is used for cutting ultra-thin wafers with low dielectric constants, the phenomenon of layering among metal layers is easy to occur. Although the laser cutting process is adopted, the generated broken edges are neat and not easy to cause the wafer breakage, the speed of laser cutting the Si sheet and the metal is low, the production efficiency is low, and meanwhile, if the metal exists on the back surface of the wafer, the front pattern cannot be seen in the laser cutting process, so that double-sided exposure is needed, and the production cost is increased by the process steps.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a front-side cutting process for an ultra-thin wafer, in which etching rates of plasma on a Si wafer and a metal are different, a scribe line is etched on the front side of the wafer until the back metal is exposed, and then the back metal is cut off by laser cutting, so as to complete the cutting of the ultra-thin metal, thereby solving the problems of ultra-thin metal fragmentation and low precision of laser cutting caused by cutting with a diamond cutter wheel.
The purpose of the invention can be realized by the following technical scheme:
a front cutting process of an ultrathin wafer comprises the following steps:
s1, completing the high temperature process of the wafer, bonding the front surface of the wafer with the glass carrier plate, and then performing the back wafer process;
s2, bonding the back of the wafer with the glass carrier plate, then debonding the front glass carrier plate, and removing the adhesive layer;
s3, completing the front wafer process;
s4, etching the front surface of the wafer by plasma, and etching and removing Si at the cutting lines to the back metal by utilizing the different etching rates of the metal and the Si;
s5, performing laser cutting on the front surface of the wafer, and cutting off the back metal;
s6, placing the cut wafer on a UV mold frame, enabling the laser to penetrate through the glass carrier plate to enable the release agent to decompose the viscosity between the glass carrier plate and the adhesive, removing the glass carrier plate, cleaning and removing the adhesive layer, and finishing wafer cutting.
Further preferably, the back side wafer process in the step S1 includes a photolithography process, an ion implantation process, and a metal process.
Further preferably, the front wafer processing in step S3 includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
Further preferably, in step S3, the dielectric layer at the scribe line is removed simultaneously when the via is opened in the LID process of the front surface of the wafer, and the metal layer at the scribe line is removed simultaneously when the metal pattern is formed in the metal process of the front surface of the wafer, so as to ensure that the wafer at the scribe line is always exposed.
Further preferably, the etching selectivity ratio of the plasma to Si to metal or Si to the insulating layer in step S4 is greater than 100: 1, the plasma is SF6Plasma or CF4Plasma is generated.
Further preferably, the laser cutting in step S5 cuts off the back metal along the etched channel in step S4.
The invention has the beneficial effects that:
according to the invention, the etching rate of the plasma to the Si sheet and the metal is different, the cutting channel is etched on the front surface of the wafer until the back metal is exposed, and then the back metal is cut off by laser cutting, so that the cutting of the ultrathin wafer is completed, and the problems of the fragmentation of the ultrathin metal, low laser cutting efficiency and poor positioning accuracy caused by the cutting of the diamond cutter wheel are solved.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the process of step S1 according to the present invention;
FIG. 2 is a schematic process flow diagram of step S2 according to the present invention;
FIG. 3 is a schematic diagram of the process of step S3 according to the present invention;
FIG. 4 is a schematic diagram of the process of step S4 according to the present invention;
FIG. 5 is a schematic diagram of the process of step S5 according to the present invention;
fig. 6 is a schematic view of the process of step S6 according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
As shown in fig. 1-6, a process for cutting the front surface of an ultra-thin wafer includes the following steps:
s1, completing the high temperature process of the wafer, bonding the front surface of the wafer with the glass carrier plate, and then performing the back surface wafer process including the yellow light process, the ion implantation process and the metal process;
s2, bonding the back of the wafer with the glass carrier plate, then debonding the front glass carrier plate, and removing the adhesive layer;
s3, completing front wafer process including yellow light process, ILD process, ion implantation process, metal process and etching process, wherein the dielectric layer at the cutting path is removed when the front LID process of the wafer is used for making a through hole and opening a window, and the metal layer at the cutting path is removed when the metal pattern is made in the front metal process of the wafer, so as to ensure that the wafer at the cutting path is always exposed;
s4, etching the front side of the wafer by plasma, and etching and removing Si at the cutting channel to the back metal by using different etching rates of metal and Si, wherein the Si at the cutting channel on the front side of the wafer is directly exposed during etching, and other parts are covered by the dielectric layer and the metal, and the etching speed of the etching plasma to the Si is higher than that to the dielectric layer and the metal, so that the Si at the cutting channel can be quickly etched;
s5, performing laser cutting on the front surface of the wafer, wherein the laser cutting cuts off the back metal along the channel etched in the step S4;
s6, placing the cut wafer on a UV mold frame, enabling the laser to penetrate through the glass carrier plate to enable the release agent to decompose the viscosity between the glass carrier plate and the adhesive, removing the glass carrier plate, cleaning and removing the adhesive layer, and finishing wafer cutting.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (6)
1. The ultra-thin wafer front surface cutting process is characterized by comprising the following steps of:
s1, completing the high temperature process of the wafer, bonding the front surface of the wafer with the glass carrier plate, and then performing the back wafer process;
s2, bonding the back of the wafer with the glass carrier plate, then debonding the front glass carrier plate, and removing the adhesive layer;
s3, completing the front wafer process;
s4, etching the front surface of the wafer by plasma, and etching and removing Si at the cutting lines to the back metal by utilizing the different etching rates of the metal and the Si;
s5, performing laser cutting on the front surface of the wafer, and cutting off the back metal;
s6, placing the cut wafer on a UV mold frame, enabling the laser to penetrate through the glass carrier plate to enable the release agent to decompose the viscosity between the glass carrier plate and the adhesive, removing the glass carrier plate, cleaning and removing the adhesive layer, and finishing wafer cutting.
2. The ultra-thin wafer front side dicing process of claim 1, wherein the back side wafer process of step S1 includes a photolithography process, an ion implantation process, and a metal process.
3. The ultra-thin front side dicing process of claim 1, wherein the front side wafer process in step S3 includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
4. The ultra-thin front side dicing process for wafer of claim 1, wherein in step S3, the dielectric layer at the scribe line is removed simultaneously when the LID process of the front side of the wafer is performed with via opening, and the metal layer at the scribe line is removed simultaneously when the metal pattern is performed with metal pattern on the front side of the wafer, so as to ensure that the wafer at the scribe line is always exposed.
5. The ultra-thin wafer front side dicing process of claim 1, wherein the etching selectivity ratio of the plasma to Si to metal or Si to insulating layer in step S4 is greater than 100: 1, the plasma is SF6Plasma or CF4Plasma is generated.
6. The ultra-thin wafer front side dicing process of claim 1, wherein the laser dicing in step S5 cuts off the back metal along the etched channel of step S4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111021765.XA CN113725160A (en) | 2021-09-01 | 2021-09-01 | Ultrathin wafer front cutting process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111021765.XA CN113725160A (en) | 2021-09-01 | 2021-09-01 | Ultrathin wafer front cutting process |
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| CN113725160A true CN113725160A (en) | 2021-11-30 |
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| CN202111021765.XA Pending CN113725160A (en) | 2021-09-01 | 2021-09-01 | Ultrathin wafer front cutting process |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200608500A (en) * | 2004-08-17 | 2006-03-01 | Lightuning Tech Inc | Wafer level chip size package of a CMOS image sensor and method for manufacturing the same |
| US20110217826A1 (en) * | 2010-03-03 | 2011-09-08 | Elpida Memory, Inc. | Method of fabricating semiconductor device |
| CN103703554A (en) * | 2011-06-24 | 2014-04-02 | 伊雷克托科学工业股份有限公司 | Etching laser-cut semiconductor before dicing die attach film (daf) or other material layer |
| TW201535501A (en) * | 2014-01-29 | 2015-09-16 | Applied Materials Inc | Wafer dicing using hybrid laser scribing and plasma etch approach with mask plasma treatment for improved mask etch resistance |
| US20180096877A1 (en) * | 2016-09-30 | 2018-04-05 | International Business Machines Corporation | Multi-chip package assembly |
| CN111599754A (en) * | 2020-06-19 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ultrathin wafer processing technology |
| CN111710648A (en) * | 2020-07-07 | 2020-09-25 | 绍兴同芯成集成电路有限公司 | Ultra-thin wafer back and double-side processing technology for bonded glass carrier plate |
| CN111799178A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Double-sided copper-plating thick film process for ultrathin wafer |
| CN112234016A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Manufacturing process of wafer thick film metal layer and PAD metal pattern |
| CN113053798A (en) * | 2021-03-30 | 2021-06-29 | 绍兴同芯成集成电路有限公司 | Ultrathin crystal thinning and cutting process utilizing tempered glass |
-
2021
- 2021-09-01 CN CN202111021765.XA patent/CN113725160A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200608500A (en) * | 2004-08-17 | 2006-03-01 | Lightuning Tech Inc | Wafer level chip size package of a CMOS image sensor and method for manufacturing the same |
| US20110217826A1 (en) * | 2010-03-03 | 2011-09-08 | Elpida Memory, Inc. | Method of fabricating semiconductor device |
| CN103703554A (en) * | 2011-06-24 | 2014-04-02 | 伊雷克托科学工业股份有限公司 | Etching laser-cut semiconductor before dicing die attach film (daf) or other material layer |
| TW201535501A (en) * | 2014-01-29 | 2015-09-16 | Applied Materials Inc | Wafer dicing using hybrid laser scribing and plasma etch approach with mask plasma treatment for improved mask etch resistance |
| US20180096877A1 (en) * | 2016-09-30 | 2018-04-05 | International Business Machines Corporation | Multi-chip package assembly |
| CN111599754A (en) * | 2020-06-19 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ultrathin wafer processing technology |
| CN111710648A (en) * | 2020-07-07 | 2020-09-25 | 绍兴同芯成集成电路有限公司 | Ultra-thin wafer back and double-side processing technology for bonded glass carrier plate |
| CN111799178A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Double-sided copper-plating thick film process for ultrathin wafer |
| CN112234016A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Manufacturing process of wafer thick film metal layer and PAD metal pattern |
| CN113053798A (en) * | 2021-03-30 | 2021-06-29 | 绍兴同芯成集成电路有限公司 | Ultrathin crystal thinning and cutting process utilizing tempered glass |
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