CN113703507B - Circuit for improving response speed of LDO (low dropout regulator) - Google Patents
Circuit for improving response speed of LDO (low dropout regulator) Download PDFInfo
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- CN113703507B CN113703507B CN202010444915.7A CN202010444915A CN113703507B CN 113703507 B CN113703507 B CN 113703507B CN 202010444915 A CN202010444915 A CN 202010444915A CN 113703507 B CN113703507 B CN 113703507B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The utility model provides an improve LDO response speed circuit, through set up the auxiliary loop that directly detects output voltage VOUT change through third resistance R0 on LDO main loop, the auxiliary loop includes second amplifier module A2, sixth NMOS pipe M0 and first current source I0, can realize quick response when improving LDO output voltage stability to be favorable to better mediating the contradiction of LDO between response speed and stability.
Description
Technical Field
The invention relates to a technology for improving the LDO low dropout linear regulator, in particular to a circuit for improving the response speed of the LDO, wherein an auxiliary loop for directly detecting the change of output voltage VOUT through a third resistor R0 is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module A2, a sixth NMOS pipe M0 and a first current source I0, so that the stability of the output voltage of the LDO can be improved, and meanwhile, the quick response can be realized, thereby being beneficial to better harmonizing the contradiction between the response speed and the stability of the LDO.
Background
LDO (low dropout regulator) is widely used in many fields, but there is often a compromise problem between response speed and stability, that is, increasing response speed reduces stability, and increasing stability reduces response speed. For example, as shown in fig. 1, fig. 1 is a schematic diagram of a circuit structure in which the response speed of the LDO is to be improved. The LDO main loop is composed of a first amplification module A1, a second amplification module A2, a power NMOS tube M1, a first resistor R1 and a second resistor R2, an input voltage end IN is connected to a drain end of the M1, an output end and a negative input end of the A2 are respectively connected to a grid end of the M1, an output voltage end OUT is connected to a source end of the M1, the OUT is connected with a feedback node FB through the R1, the FB is connected with a grounding end GND through the R2, an output end of the A1 is connected to a positive input end of the A2, a reference voltage end REF is connected to a positive input end of the A1, and the FB is connected to the negative input end of the A1. As shown in fig. 1, the unit gain buffer formed by A2 blocks the direct connection between the output resistance of A1 and the gate end capacitance of the power output MOS transistor M1, otherwise, the pole formed by the output resistance of A1 and the gate end capacitance of the power output MOS transistor M1 affects the system stability and reduces the small signal bandwidth. Although the circuit arrangement of fig. 1 can solve the stability problem well, it has the disadvantage of slow response speed in some applications, for example, it cannot respond to output changes quickly when there is a large signal. The inventor believes that if an auxiliary loop for directly detecting the change of the output voltage VOUT through the third resistor R0 is disposed on the main loop of the LDO, and the auxiliary loop includes the second amplification module A2, the sixth NMOS transistor M0 and the first current source I0, the fast response can be achieved while the stability of the output voltage of the LDO is improved. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a circuit for improving the response speed of an LDO (low dropout regulator). By arranging an auxiliary loop which directly detects the change of an output voltage VOUT through a third resistor R0 on a main loop of the LDO, wherein the auxiliary loop comprises a second amplification module A2, a sixth NMOS (N-channel metal oxide semiconductor) tube M0 and a first current source I0, the stability of the output voltage of the LDO can be improved, and meanwhile, the quick response can be realized, so that the contradiction between the response speed and the stability of the LDO can be better regulated.
The technical scheme of the invention is as follows:
a circuit for improving the response speed of an LDO (low dropout regulator) is characterized in that an auxiliary loop for directly detecting the change of an output voltage through a third resistor is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module, a sixth NMOS (N-channel metal oxide semiconductor) tube and a first current source.
The drain terminal of the sixth NMOS tube is connected with the input voltage terminal, the gate terminal of the sixth NMOS tube is respectively connected with the output terminal of the second amplification module and the gate terminal of the power NMOS tube, the first path of the source terminal of the sixth NMOS tube is connected with the output voltage terminal through the third resistor, the second path is connected with the grounding terminal through the first current source, and the third path is connected with the negative input terminal of the second amplification module.
The LDO main loop comprises a first amplification module, a second amplification module, a power NMOS tube, a first resistor and a second resistor, wherein the drain end of the power NMOS tube is connected with an input voltage end, the source end of the power NMOS tube is connected with an output voltage end, the output voltage end passes through a first resistor connection feedback node, the feedback node passes through a second resistor connection grounding end, the positive input end of the second amplification module is connected with the output end of the first amplification module, the positive input end of the first amplification module is connected with a reference voltage end, and the negative input end of the first amplification module is connected with the feedback node.
The second amplification module comprises a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a second current source.
The gate terminal of the second NMOS transistor is connected to the ground terminal through the first current source, the drain terminal of the second NMOS transistor is connected to the drain terminal of the fourth PMOS transistor and then to the gate terminal of the power NMOS transistor and the charge pump, the source terminal of the second NMOS transistor is connected to the source terminal of the third NMOS transistor and then to the ground terminal through the second current source, the gate terminal of the third NMOS transistor is connected to the output terminal of the first amplification module, the drain terminal of the third NMOS transistor is connected to the drain terminal of the fifth PMOS transistor and then to the gate terminal of the fourth PMOS transistor and the gate terminal of the fifth PMOS transistor, and the source terminal of the fourth PMOS transistor is connected to the source terminal of the fifth PMOS transistor and then to the input voltage terminal.
The auxiliary loop circuit plays a role in blocking the electric connection between the first amplification module and the power NMOS tube in a steady state, namely, the output resistor of the first amplification module cannot form a low-resistance pole with the gate capacitor of the power NMOS tube, so that the circuit stability is improved, and the bandwidth is enlarged.
The variable quantity of the output voltage is transmitted to the negative input end of the second amplification module through the third resistor, so that the auxiliary loop responds earlier than the LDO main loop so as to inhibit the change of the output voltage by influencing the grid-source voltage of the power NMOS tube in time.
The invention has the following technical effects: according to the circuit for improving the response speed of the LDO, the auxiliary loop for directly detecting the change of the output voltage through the third resistor is arranged on the main loop of the LDO, so that the response speed and the stability can be improved by utilizing the auxiliary loop. For example, the first amplifying module and the power NMOS transistor are electrically disconnected in a steady state, that is, the output resistor of the first amplifying module and the gate capacitor of the power NMOS transistor cannot form a low-resistance pole, so that the circuit stability is improved and the bandwidth is enlarged; when the output voltage VOUT changes suddenly, the change quantity of the output voltage is transmitted to the negative input end of the second amplification module through the third resistor, so that the auxiliary loop responds earlier than the LDO main loop so as to inhibit the change of the output voltage by influencing the grid-source voltage of the power NMOS tube in time.
Drawings
Fig. 1 is a schematic diagram of a circuit structure in which the response speed of the LDO is to be improved. The LDO (low dropout regulator) in fig. 1 cannot respond quickly to output changes when the signal is large.
FIG. 2 is a schematic diagram of a circuit for increasing the response speed of LDO according to the present invention.
Fig. 3 is a schematic structural diagram of a circuit for increasing the response speed of the LDO, in which the second amplification module A2 in fig. 2 is shown by element composition.
The reference numbers are listed below: OUT-output voltage terminal (corresponding to output voltage VOUT); IN-input voltage terminal (corresponding to input voltage VIN); REF-reference voltage terminal; GND-ground; a1-a first amplification module; a2-a first amplification module; R1-R2-first to second resistors; r0-a third resistance; a FB-feedback node; i0-a first current source; i1-a second current source; m1-a first NMOS transistor or power NMOS transistors M2-M3-second to third NMOS transistors; M4-M5-fourth to fifth PMOS tubes; m0-sixth NMOS transistor.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 2-3).
FIG. 2 is a schematic diagram of a circuit for increasing the response speed of LDO according to the present invention. Fig. 3 is a schematic structural diagram of a circuit for increasing the response speed of the LDO, in which the second amplification module A2 in fig. 2 is shown by element composition. As shown in fig. 2 to 3, in a circuit for improving the response speed of an LDO, an auxiliary loop for directly detecting a change in the output voltage VOUT through a third resistor R0 is disposed on a main loop of the LDO, and the auxiliary loop includes a second amplification module A2, a sixth NMOS transistor M0, and a first current source I0. The drain terminal of the sixth NMOS transistor M0 is connected to the input voltage terminal IN, the gate terminal of the sixth NMOS transistor M0 is connected to the output terminal of the second amplification module A2 and the gate terminal of the power NMOS transistor M1, respectively, the first path of the source terminal of the sixth NMOS transistor M0 is connected to the output voltage terminal OUT through the third resistor R0, the second path is connected to the ground terminal GND through the first current source I0, and the third path is connected to the negative input terminal (-) of the second amplification module A2. The LDO main loop comprises a first amplification module A1, a second amplification module A2, a power NMOS tube M1, a first resistor R1 and a second resistor R2, wherein the drain terminal of the power NMOS tube M1 is connected with an input voltage terminal IN, the source terminal of the power NMOS tube M1 is connected with an output voltage terminal OUT, the output voltage terminal OUT is connected with a feedback node FB through the first resistor R1, the feedback node FB is connected with a grounding terminal GND through the second resistor R2, the positive input terminal of the second amplification module A2 is connected with the output terminal of the first amplification module A1, the positive input terminal (+) of the first amplification module A1 is connected with a reference voltage terminal REF, and the negative input terminal (-) of the first amplification module A1 is connected with the feedback node FB.
Referring to fig. 3, the second amplifying module A2 includes a second NMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, and a second current source I1. The gate terminal of the second NMOS transistor M2 is connected to a ground terminal GND through the first current source I0, the drain terminal of the second NMOS transistor M2 is connected to the drain terminal of the fourth PMOS transistor M4 and then connected to the gate terminal of the power NMOS transistor M1 and the charge pump, the source terminal of the second NMOS transistor M2 is connected to the source terminal of the third NMOS transistor M3 and then connected to the ground terminal GND through the second current source I1, the gate terminal of the third NMOS transistor M3 is connected to the output terminal of the first amplification module A1, the drain terminal of the third NMOS transistor M3 is connected to the drain terminal of the fifth PMOS transistor M5 and then connected to the gate terminal of the fourth PMOS transistor M4 and the gate terminal of the fifth PMOS transistor M5, and the source terminal of the fourth PMOS transistor M4 is connected to the input voltage terminal IN after being connected to the drain terminal of the fifth PMOS transistor M5.
The auxiliary loop circuit plays a role in blocking the electric connection between the first amplification module A1 and the power NMOS transistor M1 in a steady state, namely, the output resistor of the first amplification module A1 cannot form a low-resistance pole with the gate capacitor of the power NMOS transistor M1, so that the circuit stability is improved, and the bandwidth is enlarged. The variation of the output voltage VOUT is transferred to the negative input (-) of the second amplification module A2 through the third resistor R0, so that the auxiliary loop responds earlier than the LDO main loop to suppress the variation of the output voltage VOUT by affecting the gate-source voltage of the power NMOS transistor M1 in time.
The specific working principle of the present invention is further explained below with reference to fig. 2.
M1 is a power NMOS tube, the drain terminal of which is connected with IN, the source terminal is connected with OUT, and the gate terminal is connected with the output of the A2 amplifying module;
m0 is an NMOS tube, the drain end of the NMOS tube is connected with IN, the source end of the NMOS tube is connected with the positive end of a current source I0, and the gate end of the NMOS tube is connected with the output end of an A2 amplification module;
one end of the R0 resistor is connected with the positive end of a current source I0 (simultaneously connected with the negative input end of the A2 amplifying module), and the other end of the R0 resistor is connected with OUT;
one end of the resistor R1 is connected with OUT, and the other end is connected with the negative input end of the amplifier module A1 (the node is named FB and is simultaneously connected with the resistor R2 in series, and the other end of the resistor R2 is grounded;
a1 is an amplifying module, and the positive input end of the amplifying module is connected with a REF signal which represents a reference voltage;
6.A2 is an amplifying module, and the positive input end of the amplifying module is connected with the output end of the A1 amplifying module;
the loop consisting of the A1, the M1 and the I0 only plays a role in blocking the electric connection between the A1 and the M1 in a steady state, namely the output resistance of the A1 cannot form a low-resistance pole with the gate capacitance of the M1, so that the stability is improved, and the bandwidth is enlarged;
8. when VOUT changes suddenly, the variable quantity of VOUT can be quickly transmitted to the negative input end of A2 through R0, and then the loops A2, M0 and I0 respond before the main loop (M1, R2, A1 and A2), so that the grid-source voltage of M1 can be influenced in time, and the change of VOUT is restrained;
as shown in fig. 3, M2 and M3 are NMOS transistors, and M4 and M5 are PMOS transistors, which together with the current source I1 constitute the A2 amplifier module of fig. 2.
The features of the invention can be seen from the above description: 1. as described in working principle 7, A2, M0, and I0 block the electrical connection of A1 and M1, thereby improving stability; and 2. The loop consisting of A2, M0 and I0 can directly detect VOUT change through R0, so that quick response in large signal is realized.
In the present invention, the NMOS transistors or PMOS transistors as illustrated in fig. 2 to 3 can be replaced by each other in principle or practice, and the equivalent circuits after replacement are well known to those skilled in the art. Therefore, the NMOS transistor or the PMOS transistor in the present specification and the claims should be understood as the MOS transistor with the technical features as an extension unless otherwise specified.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.
Claims (6)
1. A circuit for improving the response speed of an LDO (low dropout regulator) is characterized in that an auxiliary loop for directly detecting the change of an output voltage through a third resistor is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module, a sixth NMOS (N-channel metal oxide semiconductor) tube and a first current source;
the drain terminal of the sixth NMOS tube is connected with the input voltage terminal, the gate terminal of the sixth NMOS tube is respectively connected with the output terminal of the second amplification module and the gate terminal of the power NMOS tube, the first path of the source terminal of the sixth NMOS tube is connected with the output voltage terminal through the third resistor, the second path is connected with the grounding terminal through the first current source, and the third path is connected with the negative input terminal of the second amplification module.
2. The circuit of claim 1, wherein the main loop of the LDO comprises a first amplification module, the second amplification module, the power NMOS transistor, a first resistor, and a second resistor, a drain terminal of the power NMOS transistor is connected to an input voltage terminal, a source terminal of the power NMOS transistor is connected to the output voltage terminal, the output voltage terminal is connected to a feedback node through the first resistor, the feedback node is connected to a ground terminal through the second resistor, a positive input terminal of the second amplification module is connected to an output terminal of the first amplification module, a positive input terminal of the first amplification module is connected to a reference voltage terminal, and a negative input terminal of the first amplification module is connected to the feedback node.
3. The circuit for improving the response speed of the LDO as claimed in claim 2, wherein the second amplifying module comprises a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a second current source.
4. The circuit of claim 3, wherein a gate of the second NMOS transistor is connected to a ground terminal through the first current source, a drain of the second NMOS transistor is connected to a drain of the fourth PMOS transistor and then to a gate of the power NMOS transistor and a charge pump, respectively, a source of the second NMOS transistor is connected to a source of the third NMOS transistor and then to the ground terminal through the second current source, a gate of the third NMOS transistor is connected to an output of the first amplification module, a drain of the third NMOS transistor is connected to a drain of the fifth PMOS transistor and then to a gate of the fourth PMOS transistor and a gate of the fifth PMOS transistor, respectively, and a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor and then to the input voltage terminal.
5. The circuit of claim 2, wherein the auxiliary loop circuit is configured to block the electrical connection between the first amplifier module and the power NMOS transistor in a steady state, i.e. the output resistor of the first amplifier module cannot form a low resistance pole with the gate capacitor of the power NMOS transistor, so as to improve the circuit stability and increase the bandwidth.
6. The circuit of claim 2, wherein a change in the output voltage is transferred to the negative input of the second amplification module through the third resistor, such that the auxiliary loop responds earlier than the LDO main loop to suppress the change in the output voltage by affecting the gate-source voltage of the power NMOS transistor in more time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010444915.7A CN113703507B (en) | 2020-05-23 | 2020-05-23 | Circuit for improving response speed of LDO (low dropout regulator) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010444915.7A CN113703507B (en) | 2020-05-23 | 2020-05-23 | Circuit for improving response speed of LDO (low dropout regulator) |
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| CN113703507A CN113703507A (en) | 2021-11-26 |
| CN113703507B true CN113703507B (en) | 2023-01-10 |
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| US5675292A (en) * | 1996-06-05 | 1997-10-07 | Mccune, Jr.; Earl W. | Phase lock loop enabling smooth loop bandwidth switching over a wide range |
| US6703815B2 (en) * | 2002-05-20 | 2004-03-09 | Texas Instruments Incorporated | Low drop-out regulator having current feedback amplifier and composite feedback loop |
| CN1987710B (en) * | 2005-12-23 | 2010-05-05 | 深圳市芯海科技有限公司 | Voltage regulator |
| CN100492244C (en) * | 2007-03-21 | 2009-05-27 | 北京中星微电子有限公司 | Voltage regulator with low voltage difference |
| CN101398694A (en) * | 2007-09-30 | 2009-04-01 | Nxp股份有限公司 | Non-capacitance low voltage difference constant voltage regulator with rapid excess voltage response |
| US8054156B2 (en) * | 2008-08-26 | 2011-11-08 | Atmel Corporation | Low variation resistor |
| CN101728840A (en) * | 2008-10-20 | 2010-06-09 | 智原科技股份有限公司 | Charger for quick charge |
| CN102393781A (en) * | 2011-12-06 | 2012-03-28 | 四川和芯微电子股份有限公司 | Low-dropout linear voltage regulator circuit and system |
| JP2015122635A (en) * | 2013-12-24 | 2015-07-02 | 三菱プレシジョン株式会社 | Amplification circuit |
| CN104199504B (en) * | 2014-09-28 | 2017-03-29 | 苏州晶为微电子有限公司 | A kind of fast transient response low pressure difference linear voltage regulator |
| US9760103B2 (en) * | 2015-05-18 | 2017-09-12 | Marvell Israel (M.I.S.L) Ltd. | Integrated circuit having regulator controlled based on operational speed |
| US10534385B2 (en) * | 2016-12-19 | 2020-01-14 | Qorvo Us, Inc. | Voltage regulator with fast transient response |
| CN106774580B (en) * | 2017-01-19 | 2018-06-22 | 武汉众为信息技术有限公司 | A kind of LDO circuit of fast transient response high PSRR |
| CN106886243B (en) * | 2017-05-05 | 2018-03-06 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with fast response characteristic |
| CN110231847A (en) * | 2019-07-17 | 2019-09-13 | 江苏润石科技有限公司 | Rapid response type low pressure difference linear voltage regulator |
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