CN113691241A - High-precision digital jitter injection device based on amplitude conversion time sequence - Google Patents
High-precision digital jitter injection device based on amplitude conversion time sequence Download PDFInfo
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- CN113691241A CN113691241A CN202110918815.8A CN202110918815A CN113691241A CN 113691241 A CN113691241 A CN 113691241A CN 202110918815 A CN202110918815 A CN 202110918815A CN 113691241 A CN113691241 A CN 113691241A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Abstract
The invention belongs to the technical field of digital testing, and particularly relates to a high-precision digital jitter injection device based on an amplitude conversion time sequence. The invention uses the principle of amplitude conversion time sequence to connect the address generator with the clock generator, so that the address generated by the address generator is related with the time sequence, the original waveform sampling point data corresponding to the address is found out through the waveform lookup table, and the original jitter sampling point data is found out through the jitter data lookup table. Then, an amplitude modulation operation module and a data operation module are utilized, and direct amplitude addition or edge data sampling points screening and amplitude modification are carried out on data matched with jitter injection types according to different data jitter amplitudes and different jitter type injection requirements; namely, the method of changing the amplitude data of the edge sampling points of the original waveform signal data realizes the purpose of adding the jitter. Compared with the prior art, the method can simultaneously realize high adjustability of the jitter amplitude and the frequency parameter and improve the jitter injection precision.
Description
Technical Field
The invention belongs to the technical field of digital testing, and particularly relates to a high-precision digital jitter injection device based on an amplitude conversion time sequence.
Background
Currently, as the transmission rate between digital circuit systems reaches Gbps level, the accuracy and stability of data transmission at high rate become important criteria for evaluating whether the digital system works normally and stably. The jitter of the digital signal in the timing is a key factor affecting the correct delivery of data at high rates. The waveform data signals generate various types of jitter with controllable amplitude and frequency, so that the waveform data signals generate jitter components in a pertinence manner, and the jitter performance test of a high-speed digital system in the field of modern digital signals is met.
In the current jitter synthesis methods, two methods based on delay chain and analog modulation are most commonly used. The method based on the delay chain is limited by the precision and the linearity of the delay chain, and the jitter amplitude and the frequency parameter adjustability are poor, so that the jitter injection precision is influenced. The analog modulation method is based on jitter generation realized by modulating signals. One of the two signal generators is used as a modulation source to generate a modulation signal; the other signal generator is used as a clock source for generating a jittered clock and simultaneously used as a clock for generating a code pattern signal to realize a jittered data code pattern. The method needs the cooperation of a plurality of instruments, the system is complex to build, the instruments are difficult to synchronize, the analog signal serving as a modulation signal can directly introduce noise which is difficult to eliminate, the jitter synthesis effect is influenced, and the jitter injection precision is low.
Disclosure of Invention
The invention aims to: the high-precision digital jitter injection device based on the amplitude conversion time sequence is provided to solve the problems of poor jitter amplitude and frequency parameter adjustability and low jitter injection precision of a jitter synthesis method based on a delay chain and an analog modulation method.
A high precision digital jitter injection apparatus based on amplitude conversion timing, comprising: the device comprises a clock generator, an address generator, a waveform lookup table, a jitter data lookup table, an amplitude modulation calculation module, a data operation module, a digital-to-analog converter and a low pass filter LPF;
the clock generator is a variable clock generator and generates clock signals for controlling the address generator, the waveform lookup table, the jitter data lookup table and the digital-to-analog converter according to a set sampling rate;
the address generator is used for receiving a clock signal from the clock generator, and generating an address for addressing and searching waveform sampling point data by using the clock signal as a time sequence control signal;
the waveform lookup table receives an address generated by the address generator, various original waveform sampling point data are stored in the waveform lookup table, and the waveform sampling point data corresponding to each address are searched out in an addressing mode according to the address provided by the address generator;
the jitter data lookup table receives the address generated by the address generator, various types of jitter sampling point data are stored in the jitter data lookup table, and the original jitter sampling point data corresponding to each address is searched out in an addressing mode according to the address provided by the address generator and is provided to the amplitude modulation calculation module;
the amplitude modulation calculation module adjusts the original jitter sample point data from the jitter data lookup table according to the set time sequence jitter amplitude requirement, and provides the adjusted jitter sample point data to the data operation module;
the data operation module is used for receiving the waveform sampling point data from the waveform lookup table and the jitter sampling point data from the amplitude modulation calculation module, and obtaining jittered data signal waveform sampling point data by adopting a data calculation mode matched with jitter injection types according to different jitter injection types;
the digital-to-analog converter receives a clock signal generated by the clock generator and data signal waveform sampling point data from the data operation module, performs digital-to-analog conversion on the data signal waveform sampling point data in the previous row by taking the clock signal as a time sequence control signal to obtain an analog signal, and then sends the converted analog signal to the LPF (low pass filter) electric appliance;
the low pass filter LPF carries out low pass filtering on the analog signal output by the digital-to-analog converter to remove the stray signal, and the pulse waveform purity is improved.
Further, the data operation module obtains jittered data signal waveform sampling point data by directly adding data amplitudes matched with jitter injection types or screening edge data sampling points according to different jitter injection requirements.
The principle of the invention is as follows:
the deviation of the edge transition time of the signal from the edge transition time of the ideal signal is the jitter of the signal in time sequence. The digital signal edges are offset in timing by the magnitude of the jitter. The characteristics, types, sine, square wave, gaussian, etc. of the jitter amplitude data can be analyzed and defined by a common jitter analysis method, Time Interval Error (TIE). Based on this, the present invention uses the principle of amplitude conversion timing sequence (the principle of amplitude conversion timing sequence can refer to fig. 2), connects the address generator with the clock generator, associates the address generated by the address generator with the timing sequence, finds out the original waveform sampling point data corresponding to the address through the waveform lookup table, and finds out the original jitter sampling point data through the jitter data lookup table. And then, an amplitude modulation operation module and a data operation module are utilized, and aiming at the injection requirements of different data jitter amplitudes and jitter types, a mode of directly adding the amplitudes of data matched with the jitter injection types or screening edge data sampling points, namely changing the amplitude data of the edge sampling points of the original waveform signal data, is adopted, so that the purpose of adding jitter is realized.
The dithering of the invention is realized by a data operation module, and in the dithering process, a mode different from the prior mode of taking an analog signal as a modulation signal is adopted, namely, the data operation module takes an original waveform sampling point as basic data in the dithering process, and directly dithers the original waveform sampling point according to actual requirements, so that the dithering injection precision magnitude of the final waveform sampling point data can reach the data precision magnitude after the vertical resolution is divided by the waveform data signal slew rate, and the dithering injection precision is higher. In the aspect of adjusting the signal jitter amplitude, the amplitude of the original waveform is directly adjusted through an amplitude modulation operation module; in the aspect of adjusting the signal jitter frequency, the variable clock generator is simultaneously connected with the control address generator, the waveform lookup table, the jitter data lookup table and the digital-to-analog converter, and can be realized by changing the sampling rate. Compared with the existing method based on the delay chain, the method has the advantages of better adjustability of the jitter amplitude and the frequency parameter and simpler operation. In addition, through the combined action of the variable clock generator, the address generator, the waveform lookup table, the jitter data lookup table, the digital-to-analog converter, the amplitude modulation calculation module and the data operation module, the high adjustability of jitter amplitude and frequency parameters can be realized at the same time, the jitter injection precision is improved, additional instruments do not need to be added, the cost is reduced, and meanwhile, the integration level is higher.
Drawings
FIG. 1 is a schematic block diagram of a high-precision digital jitter injection apparatus based on amplitude conversion timing sequence according to the present invention;
FIG. 2 is a diagram of a digital jitter injection scheme based on amplitude transition timing;
fig. 3 is a diagram illustrating jitter injection timing of a data signal.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 1 is a schematic block diagram of a high-precision digital jitter injection apparatus based on amplitude conversion timing according to the present invention.
In this embodiment, as shown in fig. 1, the present invention provides a high-precision digital jitter injection apparatus based on amplitude conversion timing, including: the device comprises a variable clock generator module, a waveform lookup table module, a jitter data lookup table module, an amplitude modulation calculation module, a data operation module, a digital-to-analog converter and a low-pass filtering module;
each sub-module is described in detail below:
variable clock generator groundThe device comprises an address generator module, a waveform lookup table, a jitter data lookup table and a digital-to-analog converter, and generates clock signals for controlling the address generator, the waveform lookup table, the jitter data lookup table and the digital-to-analog converter according to a set sampling frequency. In this embodiment, let the variable clock frequency be fsIf each period of the periodic waveform is composed of n sampling points, the waveform output frequency is: f. ofo＝1/To＝1/nTs＝fsN; in the formula ToFor output signal waveform period, TsFor variable clock periods, the frequency of the output signal depends on the variable clock frequency fsAnd the number n of samples per cycle waveform.
The address generator module is respectively connected with the waveform data lookup table and the jitter data lookup table; the module generates addresses for addressing and searching waveform sampling point data by the waveform lookup table and the jitter data lookup table according to the clock signal. Specifically, at the rising edge of each clock signal, 1 is added to the output address of the address generator, the output address data of the address generator addresses the waveform data lookup table and the jitter data lookup table, and the waveform sample data and the jitter sample data are read out point by point.
The waveform lookup table receives an address from the address generator, various original waveform sampling point data are stored in the waveform lookup table, and the waveform lookup table is used for searching the waveform sampling point data corresponding to each address in an addressing mode according to the address provided by the address generator;
the waveform lookup table module is connected with the data operation module and used for receiving and storing the address from the address generator, and original waveform sampling point data is stored in the address; and searching the original waveform sampling point data corresponding to each address in an addressing mode based on the received address.
The jitter data lookup table module is connected with the amplitude modulation calculation module and used for receiving an address from the address generator, and various types of jitter sampling point data are stored in the jitter data lookup table module; and the jitter data lookup table is used for finding out the original jitter sampling point data corresponding to each address in an addressing mode and providing the original jitter sampling point data to the amplitude modulation calculation module.
The amplitude modulation calculation module adjusts the original jitter sample point data from the jitter data lookup table according to the set time sequence jitter amplitude requirement, and provides the adjusted jitter sample point data to the data operation module;
the data operation module is connected with the digital-to-analog converter and receives waveform sampling point data from the waveform lookup table and jitter sampling point data from the amplitude modulation calculation module. The data operation module is used for operating original waveform data and jitter data; according to different jitter injection types, data matched with the jitter injection types are subjected to direct amplitude addition or edge data sampling points are screened out and then subjected to amplitude modification to obtain jittered data signal waveform sampling point data;
the digital-to-analog conversion module is connected with the low-pass filter and used for receiving the jittered waveform sample point data and the clock signal, performing digital-to-analog conversion on the basis of the clock signal to obtain an analog signal, and then sending the converted analog signal to the low-pass filter; in this embodiment, the sampling rate of the digital-to-analog converter is fs。
The low pass filter LPF is connected with external equipment and is used for filtering analog signals output by the digital-to-analog converter and filtering stray signals. Due to the zero-order hold characteristic of the digital-to-analog converter, the output analog signal contains spurious signals including image frequency, and the analog signal containing the spurious signals needs to be filtered to improve the purity of the pulse signal. The low-pass filter filters out higher harmonics and image frequencies outside the pulse signal bandwidth required by a user to obtain a high-resolution pulse signal with controllable rising edge.
Fig. 2 is a diagram of a digital jitter injection scheme based on amplitude transition timing. As shown in fig. 2, at the rising edge of the data signal waveform, the time when the voltage value of the rising edge of the data signal reaches the decision voltage determines the decision of the high level or low level transition time of the data signal, the decision transition time can be affected by changing the voltage amplitude of the rising edge at the decision voltage, when the signal voltage amplitude at the decision voltage is increased by Δ a, the decision time sequence will be shifted forward by Δ t, and similarly, when the signal voltage amplitude at the decision voltage is decreased by Δ a, the decision time sequence will be delayed by Δ t; this isThe offset delta t of the time sequence is also determined by the slew rate SR of the signal edge, and the three satisfy the following relation: the signal edge slew rate can be generally determined by the amplitude difference between the rising time Tr and the edge, 20% -80% or 10% -90%, and in this embodiment, the waveform signal edge slew rate is determined by the sampling rate f of the variable clock generatorsAnd determining the waveform data sampling point parameters:
SR＝ΔA'/(1/fs)；
in the formula, delta A' is the interval amplitude difference between two points of the waveform data sampling point;
from this, the timing offset can be determined:
Δt＝ΔA/[ΔA'/(1/fs)]；
therefore, the high-precision digital jitter injection device based on the amplitude conversion time sequence can realize the arbitrariness of jitter injection types.
Fig. 3 is a diagram illustrating jitter injection timing of a data signal. As shown in fig. 3, the waveform data of the original data signal is subjected to dithering operation to obtain a dithered data signal waveform, the dithering amplitude of the rising edge of the dithered data waveform and the forward movement or the backward movement of the dithering timing sequence are set by the dithering data and data operation rules, as shown in fig. 3, the dithering type is sinusoidal dithering, and the time interval error of the rising edge of the dithered data signal, i.e., the TIE track, represents the sinusoidal characteristic.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (2)
1. A high precision digital jitter injection apparatus based on amplitude conversion timing, comprising: clock generator, address generator, waveform lookup table, jitter data lookup table, amplitude modulation calculation module, data operation module, digital-to-analog converter and low pass filter LPF, its characterized in that:
the clock generator is a variable clock generator and generates clock signals for controlling the address generator, the waveform lookup table, the jitter data lookup table and the digital-to-analog converter according to a set sampling rate;
the address generator is used for receiving a clock signal from the clock generator, and generating an address for addressing and searching waveform sampling point data by using the clock signal as a time sequence control signal;
the waveform lookup table receives an address generated by the address generator, various original waveform sampling point data are stored in the waveform lookup table, and the waveform sampling point data corresponding to each address are searched out in an addressing mode according to the address provided by the address generator;
the jitter data lookup table receives the address generated by the address generator, various types of jitter sampling point data are stored in the jitter data lookup table, and the original jitter sampling point data corresponding to each address is searched out in an addressing mode according to the address provided by the address generator and is provided to the amplitude modulation calculation module;
the amplitude modulation calculation module adjusts the original jitter sample point data from the jitter data lookup table according to the set time sequence jitter amplitude requirement, and provides the adjusted jitter sample point data to the data operation module;
the data operation module is used for receiving the waveform sampling point data from the waveform lookup table and the jitter sampling point data from the amplitude modulation calculation module, and obtaining jittered data signal waveform sampling point data by adopting a data calculation mode matched with jitter injection types according to different jitter injection types;
the digital-to-analog converter receives a clock signal generated by the clock generator and data signal waveform sampling point data from the data operation module, performs digital-to-analog conversion by taking the clock signal as a time sequence control signal to obtain an analog signal, and then sends the converted analog signal to the LPF (low pass filter);
the low pass filter LPF carries out low pass filtering on the analog signal output by the digital-to-analog converter to remove the stray signal, and the pulse waveform purity is improved.
2. A high precision digital jitter injection apparatus based on amplitude conversion timing as claimed in claim 1, wherein: and the data operation module obtains jittered data signal waveform sampling point data by directly adding data amplitudes matched with jitter injection types or screening edge data sampling points and then modifying the amplitudes according to different jitter injection requirements.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114153265A (en) * | 2021-11-26 | 2022-03-08 | 深圳市纽瑞芯科技有限公司 | Ultra-wideband baseband pulse generator based on table look-up digital-to-analog converter |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040223559A1 (en) * | 2003-05-09 | 2004-11-11 | Hill John P. | Integrated data jitter generator for the testing of high-speed serial interfaces |
| CN101032074A (en) * | 2004-09-30 | 2007-09-05 | 摩托罗拉公司 | System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis |
| JP2008118338A (en) * | 2006-11-02 | 2008-05-22 | Yokogawa Electric Corp | Device for generating jitters |
| CN102253254A (en) * | 2011-04-18 | 2011-11-23 | 中国航空工业集团公司北京长城计量测试技术研究所 | Device and method for generating multi-channel sine wave phase standard signals |
| CN103326726A (en) * | 2012-03-21 | 2013-09-25 | 爱德万测试株式会社 | Signal generation apparatus and signal generation method |
| CN104617938A (en) * | 2013-11-01 | 2015-05-13 | 韩国科学技术院 | Internal jitter tolerance tester with an internal jitter generator |
| CN105634486A (en) * | 2014-10-29 | 2016-06-01 | 江苏绿扬电子仪器集团有限公司 | Jitter injection system presented for aiming at DDS stray |
| CN107171657A (en) * | 2017-06-14 | 2017-09-15 | 电子科技大学 | A kind of jittered device of train pulse part rising edge |
| CN107271891A (en) * | 2017-06-14 | 2017-10-20 | 电子科技大学 | A kind of jittered device of train pulse rising edge |
| CN109142820A (en) * | 2018-09-26 | 2019-01-04 | 深圳市鼎阳科技有限公司 | A kind of pulse wave generating device |
-
2021
- 2021-08-11 CN CN202110918815.8A patent/CN113691241B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040223559A1 (en) * | 2003-05-09 | 2004-11-11 | Hill John P. | Integrated data jitter generator for the testing of high-speed serial interfaces |
| CN101032074A (en) * | 2004-09-30 | 2007-09-05 | 摩托罗拉公司 | System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis |
| JP2008118338A (en) * | 2006-11-02 | 2008-05-22 | Yokogawa Electric Corp | Device for generating jitters |
| CN102253254A (en) * | 2011-04-18 | 2011-11-23 | 中国航空工业集团公司北京长城计量测试技术研究所 | Device and method for generating multi-channel sine wave phase standard signals |
| CN103326726A (en) * | 2012-03-21 | 2013-09-25 | 爱德万测试株式会社 | Signal generation apparatus and signal generation method |
| CN104617938A (en) * | 2013-11-01 | 2015-05-13 | 韩国科学技术院 | Internal jitter tolerance tester with an internal jitter generator |
| CN105634486A (en) * | 2014-10-29 | 2016-06-01 | 江苏绿扬电子仪器集团有限公司 | Jitter injection system presented for aiming at DDS stray |
| CN107171657A (en) * | 2017-06-14 | 2017-09-15 | 电子科技大学 | A kind of jittered device of train pulse part rising edge |
| CN107271891A (en) * | 2017-06-14 | 2017-10-20 | 电子科技大学 | A kind of jittered device of train pulse rising edge |
| CN109142820A (en) * | 2018-09-26 | 2019-01-04 | 深圳市鼎阳科技有限公司 | A kind of pulse wave generating device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114153265A (en) * | 2021-11-26 | 2022-03-08 | 深圳市纽瑞芯科技有限公司 | Ultra-wideband baseband pulse generator based on table look-up digital-to-analog converter |
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