CN113690340B - Perovskite crystal silicon laminated solar cell manufacturing method and cell structure - Google Patents

Perovskite crystal silicon laminated solar cell manufacturing method and cell structure Download PDF

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CN113690340B
CN113690340B CN202110835841.4A CN202110835841A CN113690340B CN 113690340 B CN113690340 B CN 113690340B CN 202110835841 A CN202110835841 A CN 202110835841A CN 113690340 B CN113690340 B CN 113690340B
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CN113690340A (en
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请求不公布姓名
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Shenzhen Heijing Optoelectronic Technology Co ltd
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
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    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a manufacturing method of a perovskite crystal silicon laminated solar cell, which comprises the following steps: s100, texturing the bottom surface of the P-type silicon wafer, and texturing or polishing the top surface to form a silicon wafer substrate; s200, forming a bottom passivation layer on the bottom surface of the silicon wafer substrate by adopting a thermal growth method, an atomic deposition method or a plasma enhanced chemical vapor deposition method, and forming an open passivation layer of a bottom electrode by opening the bottom passivation layer by adopting a method including but not limited to laser etching. The battery structure manufactured by the method is also included. The invention directly adopts a double-sided passivated battery structure which can be independently used as a solar battery, and simultaneously has an effective heavily doped composite layer to form an integral battery structure, and the invention provides a manufacturing method of the structure according to the structure, thereby being fine and efficient; the battery structure formed by the scheme has the advantages of high open-circuit voltage, low preparation cost and high photoelectric efficiency.

Description

Perovskite crystal silicon laminated solar cell manufacturing method and cell structure
Technical Field
The invention relates to the technical field of solar cells, in particular to a perovskite crystal silicon laminated solar cell manufacturing method and a cell structure.
Background
Photovoltaic energy has been developed very rapidly in recent years as one of the most important renewable energy sources. Solar cells are the most important part of photovoltaic energy systems, and improving the photoelectric conversion efficiency is the most important way to reduce the cost of photovoltaic energy.
The current industrialized crystalline silicon photovoltaic cells gradually approach the bottleneck, the efficiency improvement is smaller, and the laminated photovoltaic cells provide the most favorable theoretical technical support for reducing the electricity cost of photovoltaic energy due to the higher ultimate efficiency.
The perovskite material has the characteristics of low cost, adjustable band gap and the like, and the perovskite-crystalline silicon laminated solar cell combined with the silicon bottom cell can improve the efficiency limit of the silicon solar cell to more than 40%, so that the perovskite-crystalline silicon laminated solar cell is considered to be the most promising next generation photovoltaic technology in the photovoltaic industry.
In the crystalline silicon perovskite laminated solar cell at the present stage, the front surface of the bottom cell is generally polished and unpassivated emitting electrodes due to the requirement of a preparation process, so that the laminated voltage is low, and the overall photoelectric conversion efficiency is affected. Therefore, the photovoltaic cell has the laminated structure with the front surface passivation and the effective compounding, the photovoltaic cell efficiency can be further improved, and the power generation cost of the photovoltaic system is reduced. Based on this, it is necessary to develop a corresponding solar cell structure.
Disclosure of Invention
In view of the above, one of the objects of the present invention is to provide a method for manufacturing a perovskite crystalline silicon stacked solar cell, which comprises the following steps:
a manufacturing method of a perovskite crystal silicon laminated solar cell comprises the following steps:
s100, texturing the bottom surface of a P-type silicon wafer, and texturing or polishing the top surface to form a silicon wafer substrate (110);
s200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and perforating the bottom passivation layer to form a bottom electrode perforating passivation layer (120);
s300, preparing a metal bottom electrode layer (130) on the bottom electrode open pore passivation layer (120);
s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110);
s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140);
s600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150);
s700, preparing a P-type heavily doped polycrystalline layer (170) on the second passivation layer (160);
s800, preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170);
s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210);
s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220);
s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230);
s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240);
s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250);
s1400, preparing an anti-reflection layer (270) on the metal gate line electrode layer (260).
Forming a bottom passivation layer on the bottom surface of the silicon wafer substrate (110) comprises:
a bottom passivation layer is manufactured on the bottom surface of the silicon wafer substrate (110) by adopting a thermal growth method, or an atomic deposition method or a plasma enhanced chemical vapor deposition method;
perforating the bottom passivation layer to form a bottom electrode perforated passivation layer comprising: and opening the bottom passivation layer by a laser etching opening method to form a bottom electrode opening passivation layer (120).
Preparing a metal bottom electrode layer (130) on the bottom electrode open-pore passivation layer (120) includes:
a metal bottom electrode layer (130) is prepared on the bottom electrode open-pore passivation layer (120) by adopting an electroplating method, an evaporation method or a printing method.
Forming a first passivation layer (140) on a top surface of the silicon wafer substrate (110) includes: forming a first passivation layer (140) on the top surface of the silicon wafer substrate (110) by adopting a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or
Preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) includes: preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method; and/or
Preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) includes: preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) using methods including, but not limited to, plasma enhanced chemical vapor deposition and thermal growth; and/or
Preparing a P-type heavily doped polycrystalline layer (170) on the second passivation layer (160) includes: a P-type heavily doped polycrystalline layer (170) is formed on the second passivation layer (160) by using a plasma enhanced chemical vapor deposition method and a low pressure chemical vapor deposition method.
Preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) includes: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) by adopting a spin coating method, an evaporation method, a sputtering method, a spraying method, a thermal spray decomposition method, a blade coating method, a printing method and a slit coating method; and/or
Preparing a perovskite light absorbing layer (220) on the hole transporting layer (210) includes: preparing a perovskite light absorbing layer (220) on the hole transport layer (210) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or blade coating, or printing and slit coating method; and/or
Preparing a perovskite light absorbing layer (220) on the hole transporting layer (210): an electron transport layer (230) is prepared on the perovskite light absorbing layer (220) by spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or knife coating, or printing and slot coating.
Preparing a top electrode buffer layer (240) on the electron transport layer (230) includes: preparing a top electrode buffer layer (240) on the electron transport layer (230) by sputtering, atomic deposition and evaporation; and/or
Preparing a transparent electrode (250) on the top electrode buffer layer (240) includes: preparing a transparent electrode (250) on the top electrode buffer layer (240) by adopting sputtering, atomic deposition and evaporation methods; and/or
Preparing a metal gate line electrode layer (260) on the transparent electrode (250) includes: preparing a metal gate line electrode layer (260) on the transparent electrode (250) by adopting evaporation, printing and electroplating methods; and/or
Preparing an anti-reflection layer (270) on the metal gate line electrode layer (260) includes: an anti-reflection layer (270) is prepared on the metal gate line electrode layer (260) by vapor deposition, sputtering and atomic deposition methods.
And forming an N-type doped emitter layer (180) on the top surface of the silicon wafer substrate (110) through a tubular boron diffusion or chained boron diffusion method between the steps S100 and S200 or between the steps S300 and S400, wherein the first passivation layer (140) is formed on the surface of the N-type doped emitter layer (180).
And preparing a P-type silicon wafer with the resistivity of 1-5 ohm-cm for standby by a suspension zone melting method before the step S100.
The second objective of the present invention is to provide a solar cell structure manufactured by the above-mentioned solar cell manufacturing method, where the solar cell structure is a layered structure and includes a bottom electrode unit (100) located at the bottom and a top electrode unit (200) located at the top, and the bottom electrode unit (100) and the top electrode unit (200) are stacked to form a whole;
the bottom electrode unit (100) comprises a silicon wafer substrate (110), wherein the silicon wafer substrate (110) is made of P-type silicon, a bottom electrode open-pore passivation layer (120) is formed on the bottom surface of the silicon wafer substrate (110), and a metal bottom electrode layer (130) is arranged on the bottom surface of the bottom electrode open-pore passivation layer (120); a first passivation layer (140) is formed on the top surface of the silicon wafer substrate (110), an N-type heavily doped polycrystalline layer (150) is formed on the top surface of the first passivation layer (140), a second passivation layer (160) is formed on the top surface of the N-type heavily doped polycrystalline layer (150), and a P-type heavily doped polycrystalline layer (170) is formed on the top surface of the second passivation layer (160);
the top electrode unit (200) comprises a hole transmission layer (210), wherein the bottom surface of the hole transmission layer (210) is connected to the top surface of the P-type heavily doped polycrystalline layer (170), a perovskite light absorption layer (220) is arranged on the top surface of the hole transmission layer (210), an electron transmission layer (230) is arranged on the top surface of the perovskite light absorption layer (220), a top electrode buffer layer (240) is arranged on the top surface of the electron transmission layer (230), a transparent electrode (250) is arranged on the top surface of the top electrode buffer layer (240), a metal gate line electrode layer (260) is arranged on the top surface of the transparent electrode (250), and an antireflection layer (270) is arranged on the top surface of the metal gate line electrode layer (260); necessary materials for the transparent electrode (250) include ITO, IZO, AZO and graphene.
An N-type doped emitter layer (180) is formed between the silicon substrate (110) and the first passivation layer (140), the bottom surface of the N-type doped emitter layer (180) is connected to the top surface of the silicon substrate (110), and the top surface of the N-type doped emitter layer (180) is connected to the bottom surface of the first passivation layer (140).
The beneficial effects are that: the invention has reasonable design, novel structure and good effect, and provides the preparation method for manufacturing the solar cell forming structure, the method can well form each layered structure on the silicon substrate, the composite polycrystalline silicon passivation layer with front and back tunneling passivation contact, the effect of the double-sided passivation structure of the silicon wafer layer can improve the open circuit voltage of the silicon cell, the composite doped polycrystalline silicon passivation layer on the upper surface can be used as the middle tunneling layer of the laminated cell, the prepared silicon bottom cell has high open circuit voltage, and the preparation method is particularly suitable for the preparation of multi-junction laminated solar cells and has higher photoelectric conversion efficiency.
Drawings
Fig. 1 is a schematic view of a solar structure according to an embodiment of the invention.
Detailed Description
The invention is further preferably illustrated in the following detailed description of embodiments in conjunction with the accompanying drawings and examples:
example 1
Referring to fig. 1, the method for manufacturing the perovskite crystal silicon stacked solar cell based on the structure comprises the following steps:
s100, texturing the bottom surface of a P-type silicon wafer, and texturing or polishing the top surface to form a silicon wafer substrate 110;
in the specific implementation process, the surface of the P-type silicon 103 sheet is subjected to texturing or polishing treatment by adopting, but not limited to, alkaline solution.
S200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and perforating the bottom passivation layer to form a bottom electrode perforating passivation layer (120);
in a specific implementation process, a bottom passivation layer is formed on the bottom surface of the silicon wafer substrate 110 by adopting a thermal growth method, an atomic deposition method or a plasma enhanced chemical vapor deposition method, and the bottom passivation layer is perforated by a method including but not limited to laser etching perforation to form a bottom electrode perforated passivation layer 120;
s300, preparing a metal bottom electrode layer (130) on the bottom electrode open pore passivation layer (120);
in a specific implementation, the metal bottom electrode layer 130 is prepared on the bottom electrode open passivation layer 120 by electroplating, evaporation, or printing;
s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110);
in particular embodiments, the first passivation layer 140 is formed on the top surface of the silicon wafer substrate 110 using a process including, but not limited to, plasma enhanced chemical vapor deposition and thermal growth;
s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140);
in particular embodiments, N-type heavily doped polycrystalline layer 150 is formed on first passivation layer 140 using a process including, but not limited to, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition;
s600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150);
in particular embodiments, the second passivation layer 160 is formed on the N-type heavily doped polycrystalline layer 150 using a process including, but not limited to, plasma enhanced chemical vapor deposition and thermal growth;
s700, preparing a P-type heavily doped polycrystalline layer (170) on the second passivation layer (160);
in particular embodiments, P-type heavily doped polycrystalline layer 170 is formed on second passivation layer 160 using a process including, but not limited to, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition;
s800, preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170);
in particular embodiments, hole transport layer 210 is formed on P-type heavily doped polycrystalline layer 170 by methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, knife coating, printing, and slot coating;
s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210);
in particular implementations, perovskite light absorbing layer 220 is fabricated on hole transporting layer 210 using methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, knife coating, printing, and slot coating;
s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220);
in particular implementations, electron transport layer 230 is fabricated on perovskite light absorbing layer 220 using methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, knife coating, printing, and slot coating;
s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230);
in an embodiment, top electrode buffer layer 240 is formed on electron transport layer 230 using methods including, but not limited to, sputtering, atomic deposition, and evaporation;
s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240);
in an embodiment, transparent electrode 250 is formed on top electrode buffer layer 240 using methods including, but not limited to, sputtering, atomic deposition, and evaporation;
s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250);
in particular implementations, metal gate line electrode layer 260 is fabricated on transparent electrode 250 using methods including, but not limited to, evaporation, printing, and electroplating;
s1400, preparing an anti-reflection layer (270) on the metal gate line electrode layer (260);
in particular embodiments, antireflective layer 270 is prepared on metal gate line electrode layer 260 using methods including, but not limited to, evaporation, sputtering, and atomic deposition.
It is further preferred that the N-type doped emitter layer 180 is formed on the top surface of the silicon wafer substrate 110 by a method including, but not limited to, tube boron diffusion or chain boron diffusion between steps S100 and S200, or between steps S300 and S400, and then the first passivation layer 140 is formed on the surface of the N-type doped emitter layer 180.
It is further preferred that the P-type silicon wafer having a resistivity of 1-5 ohm-cm is prepared for use by a suspension zone melting method prior to step S100.
Based on the above method steps, and preferred steps. In the specific implementation, a P-type silicon wafer with the resistivity of 1-5 ohm-cm can be prepared by adopting a suspension zone melting method; and texturing the bottom surface of the P-type silicon wafer, and expanding phosphorus on the top surface to form a PN homojunction, so as to form an N-type doped emitter layer 180 with lower doping concentration, wherein the doping concentration is 5 x 1012 cm < -3 >. And preparing a passivation layer of Al2O3/SiNx on the bottom surface of the P-type silicon wafer by ALD and PECVD, namely, the bottom passivation layer. The top surface of the P-type silicon wafer is grown with a 3nm SiO2 passivation layer by ALD, i.e., the first passivation layer 140. And growing a 60nm heavily doped N-type polycrystalline silicon layer on the top surface of the P-type silicon wafer by LPCVD, namely an N-type heavily doped polycrystalline layer 150, wherein the doping concentration of the N-type heavily doped polycrystalline layer 150 is 1.5 x 10201 cm < -3 >. The heavily doped N-type polysilicon layer surface is grown by ALD to form a 2nm SiO2 passivation layer, which is the second passivation layer 160. The P-type heavily doped polysilicon layer 170 is formed by LPCVD 20. 20nm, and has a doping concentration of 3 x 10201 cm-3. A metal bottom electrode was prepared by screen printing a 2 micron silver electrode, which was the metal bottom electrode layer 130. The hole transport layer 210 is obtained by spin coating PTAA on the front surface of the silicon wafer after treating the surface of the P heavily doped polysilicon layer with plasma. The perovskite light absorbing layer 220 of FAMACs was prepared in a one-step process and had a thickness of 600nm. The 25 nm c60 electron transport layer 230 was prepared using an evaporation method. Then, a 15nm SnO2 top electrode buffer layer 240 is prepared by ALD. The AZO transparent electrode 250 is prepared using a sputtering method. The metal gate electrode layer 260 and the LiF antireflection layer 270 were prepared by evaporation to have thicknesses of 300nm and 120nm, respectively.
Through the IV performance test, the stacked solar cell device obtained an open circuit voltage of 1.85V and a photoelectric conversion efficiency of 24.1%.
Example two
Fig. 1 shows a perovskite crystalline silicon stacked solar cell structure according to an embodiment of the invention, which is a layered structure and includes a bottom electrode unit 100 at the bottom and a top electrode unit 200 at the top, wherein the bottom electrode unit 100 and the top electrode unit 200 are stacked to form a whole; the bottom electrode unit 100 comprises a silicon wafer substrate 110, wherein the silicon wafer substrate 110 is made of P-type silicon, a bottom electrode open pore passivation layer 120 is formed on the bottom surface of the silicon wafer substrate 110, and a metal bottom electrode layer 130 is arranged on the bottom surface of the bottom electrode open pore passivation layer 120; a first passivation layer 140 is formed on the top surface of the silicon substrate 110, an N-type heavily doped polycrystalline layer 150 is formed on the top surface of the first passivation layer 140, a second passivation layer 160 is formed on the top surface of the N-type heavily doped polycrystalline layer 150, and a P-type heavily doped polycrystalline layer 170 is formed on the top surface of the second passivation layer 160; the top electrode unit 200 includes a hole transport layer 210, a bottom surface of the hole transport layer 210 is connected to a top surface of the P-type heavily doped polycrystalline layer 170, a perovskite light absorbing layer 220 is disposed on the top surface of the hole transport layer 210, an electron transport layer 230 is disposed on the top surface of the perovskite light absorbing layer 220, a top electrode buffer layer 240 is disposed on the top surface of the electron transport layer 230, a transparent electrode 250 is disposed on the top surface of the top electrode buffer layer 240, a metal gate line electrode layer 260 is disposed on the top surface of the transparent electrode 250, and an anti-reflection layer 270 is disposed on the top surface of the metal gate line electrode layer 260.
In the above basic scheme of the present invention, the bottom electrode unit 100 and the top electrode unit 200 may be used as independent solar cell structures.
P-type silicon is selected as the silicon wafer substrate 110, specifically, the resistivity of the silicon wafer substrate 110 is 0.1-50 ohm cm, the thickness is 100-800 mu m, the bottom surface is textured, and the top surface is pyramid textured or/and polished. In addition, the bottom and top surfaces of the silicon wafer substrate 110 may also be diamond wire cut back surface structures. The metal bottom electrode layer 130 is made of one or more materials selected from aluminum, silver, titanium, palladium, nickel, chromium and copper, and has a thickness of 1-2000 μm. The bottom electrode open pore passivation layer 120 is made of one or more materials of SiO2, al2O3, si3N4, alN, INSb, siC, tiO2, microcrystalline silicon or amorphous silicon, and has a thickness of 0-20 nm.
In particular, it is preferable that an N-type doped emitter layer 180 is formed between the silicon substrate 110 and the first passivation layer 140, and a bottom surface of the N-type doped emitter layer 180 is connected to a top surface of the silicon substrate 110, and a top surface of the N-type doped emitter layer 180 is connected to a bottom surface of the first passivation layer 140. Further, the depth of the N-doped emitter layer 180 is 0.5-10 μm and the diffusion sheet resistance is 1-150 ohm/sq.
Specifically, the first passivation layer 140 and the second passivation layer 160 are silicon oxide passivation layers or amorphous passivation layers having a thickness of 0-50nm.
Specifically, the doping concentration of the N-type heavily doped polycrystalline layer 150 is 8 x 1018cm-3 to 1 x 1021cm-3, and the thickness of the N-type heavily doped polycrystalline layer 150 may be 0-100nm.
Specifically, the doping concentration of the P-type heavily doped polycrystalline layer 170 is 8 x 1018cm-3 to 2 x 1021cm-3, and the thickness of the P-type heavily doped polycrystalline layer 170 may be 0-100nm.
The hole transport layer 210 is made of one or more materials selected from PTAA, poly-TPD, niOx, P3HT, V2O5, moOx, PEDOT PSS, WOx, spiro-OMeTAD, cuSCN, cu2O, cuI, spiro-TTB, F4-TCNQ, F6-TCNNQ, m-MTDATA and TAPC, and the thickness of the hole transport layer 210 may be 0-1000 nm.
Specifically, the general formula of the perovskite light absorbing layer 220 material is ABX3, wherein: a is a monovalent cation including, but not limited to, one or more cations of lithium, sodium, potassium, cesium, rubidium, amine, or amidino; b is a divalent cation including, but not limited to, one or more cations of lead particles, tin particles, tungsten particles, copper particles, zinc particles, gallium particles, selenium particles, rhodium particles, germanium particles, arsenic particles, palladium particles, silver particles, gold particles, indium particles, antimony particles, mercury particles, iridium particles, thallium particles, bismuth particles; x is a monovalent anion including, but not limited to, one or more anions of iodine, bromine, chlorine, or astatine particles; the perovskite light absorbing layer 220 has a thickness of 0.05-100 μm.
Specifically, the perovskite light absorbing layer 220 material has a chemical formula of cs0.05fa0.80ma0.15pbi2.55br0.45, wherein Cs is cesium, FA is formamidino, MA is methylamino, and I is iodine. The thickness of the light absorbing layer is 0.05-100 μm.
Specifically, the electron transport layer 230 is made of one or more of SnO2, tiO2, znO, zrO2, tiSnOx, snZnOx, fullerene and derivatives thereof; the electron transport layer 230 has a thickness of 0-500 a nm a.
Specifically, the top electrode buffer layer 240 is made of one or more of V2O5, moOx, ag, au, cu, snO2, znO, tiO2, al2O3, siO2, si3N4, PMMA, BCP, PEIE microcrystalline silicon, or amorphous silicon; the top electrode buffer layer 240 has a thickness of 0-50 a nm a.
Specifically, the necessary materials to make the transparent electrode 250 are ITO, IZO, AZO and graphene, and include, but are not limited to, one or more of Ag, au, cu, and Al metal nanowires; the transparent electrode 250 has a thickness of 0-500 a nm a.
Specifically, the metal gate electrode layer 260 is made of one or more of ITO, IZO, AZO, graphene, and metal nanowires including but not limited to Ag, au, cu, or Al, and the thickness of the metal gate electrode layer 260 is 0-500 nm.
Specifically, the manufacturing material of the anti-reflection layer 270 is one or more of LiF, mgF2, alN, znS, si N4, siO2, tiO2 or flexible film with suede structure, and the thickness of the anti-reflection layer 270 is 0-3 mm.
The names of the technical features and the letter expressions of the material names are all common in the field.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (10)

1. The manufacturing method of the perovskite crystal silicon laminated solar cell is characterized by comprising the following steps of:
s100, texturing the bottom surface of a P-type silicon wafer and texturing the top surface to form a silicon wafer substrate (110); the resistivity of the silicon wafer substrate (110) is 0.1-50 ohm-cm, the thickness of the silicon wafer substrate (110) is 100-800 mu m, the bottom surface of the silicon wafer substrate (110) is of a suede structure, and the top surface of the silicon wafer substrate (110) is of a pyramid suede structure;
s200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and perforating the bottom passivation layer to form a bottom electrode perforating passivation layer (120); the thickness of the bottom electrode open pore passivation layer (120) is 0-20nm, and the thickness of the bottom electrode open pore passivation layer (120) is greater than 0nm;
s300, preparing a metal bottom electrode layer (130) on the bottom electrode open pore passivation layer (120); the thickness of the metal bottom electrode layer (130) is 1-2000 mu m;
s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110); the thickness of the first passivation layer (140) is 0-50nm, and the thickness of the first passivation layer (140) is larger than 0nm;
s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140); the thickness of the N-type heavily doped polycrystalline layer (150) is 0-100nm, the thickness of the N-type heavily doped polycrystalline layer (150) is more than 0nm, and the doping concentration of the N-type heavily doped polycrystalline layer (150) is 8 multiplied by 10 18 cm -3 -1×10 21 cm -3 ；
S600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150); the thickness of the second passivation layer (160) is 0-50nm, and the thickness of the second passivation layer (160) is greater than 0nm;
s700, preparing a P-type heavily doped polycrystalline layer (170) on the second passivation layer (160); the thickness of the P-type heavily doped polycrystalline layer (170) is 0-100nm, the thickness of the P-type heavily doped polycrystalline layer (170) is more than 0nm, and the doping concentration of the P-type heavily doped polycrystalline layer (170) is 8 multiplied by 10 18 cm -3 -2×10 21 cm -3 ；
S800, preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170); the thickness of the hole transport layer (210) is 0-1000nm, and the thickness of the hole transport layer (210) is greater than 0nm;
s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210); the thickness of the perovskite light absorption layer (220) is 0.05-100 mu m;
s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220); the thickness of the electron transport layer (230) is 0-500nm, and the thickness of the electron transport layer (230) is greater than 0nm;
s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230); the thickness of the top electrode buffer layer (240) is 0-50nm, and the thickness of the top electrode buffer layer (240) is greater than 0nm;
s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240); the thickness of the transparent electrode (250) is 0-500nm, and the thickness of the transparent electrode (250) is larger than 0nm;
s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250); the thickness of the metal gate line electrode layer (260) is 0-500nm, and the thickness of the metal gate line electrode layer (260) is larger than 0nm;
s1400, preparing an anti-reflection layer (270) on the metal gate line electrode layer (260); the thickness of the anti-reflection layer (270) is 0-3mm, and the thickness of the anti-reflection layer (270) is greater than 0mm.
2. The method for manufacturing the perovskite crystal silicon laminated solar cell according to claim 1, wherein: forming a bottom passivation layer on the bottom surface of the silicon wafer substrate (110) comprises:
a bottom passivation layer is manufactured on the bottom surface of the silicon wafer substrate (110) by adopting a thermal growth method, or an atomic deposition method or a plasma enhanced chemical vapor deposition method;
the forming the bottom electrode open-pore passivation layer comprises the following steps: and opening the bottom passivation layer by a laser etching opening method to form a bottom electrode opening passivation layer (120).
3. The method for manufacturing the perovskite crystal silicon laminated solar cell according to claim 1, wherein: preparing a metal bottom electrode layer (130) on the bottom electrode open-pore passivation layer (120) includes:
a metal bottom electrode layer (130) is prepared on the bottom electrode open-pore passivation layer (120) by adopting an electroplating method, an evaporation method or a printing method.
4. The method for manufacturing the perovskite crystal silicon laminated solar cell according to claim 1, wherein:
forming a first passivation layer (140) on a top surface of the silicon wafer substrate (110) includes: forming a first passivation layer (140) on the top surface of the silicon wafer substrate (110) by adopting a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or
Preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) includes: preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method; and/or
Preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) includes: preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) using methods including, but not limited to, plasma enhanced chemical vapor deposition and thermal growth; and/or
Preparing a P-type heavily doped polycrystalline layer (170) on the second passivation layer (160) includes: a P-type heavily doped polycrystalline layer (170) is formed on the second passivation layer (160) by using a plasma enhanced chemical vapor deposition method and a low pressure chemical vapor deposition method.
5. The method for manufacturing the perovskite crystal silicon laminated solar cell according to claim 1, wherein: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) includes: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) by adopting a spin coating method, an evaporation method, a sputtering method, a spraying method, a thermal spray decomposition method, a blade coating method, a printing method and a slit coating method; and/or
Preparing a perovskite light absorbing layer (220) on the hole transporting layer (210) includes: preparing a perovskite light absorbing layer (220) on the hole transport layer (210) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or blade coating, or printing and slit coating method; and/or
Preparing a perovskite light absorbing layer (220) on the hole transporting layer (210): an electron transport layer (230) is prepared on the perovskite light absorbing layer (220) by spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or knife coating, or printing and slot coating.
6. The method for manufacturing the perovskite crystal silicon laminated solar cell according to claim 1, wherein: preparing a top electrode buffer layer (240) on the electron transport layer (230) includes: preparing a top electrode buffer layer (240) on the electron transport layer (230) by sputtering, atomic deposition and evaporation; and/or
Preparing a transparent electrode (250) on the top electrode buffer layer (240) includes: preparing a transparent electrode (250) on the top electrode buffer layer (240) by adopting sputtering, atomic deposition and evaporation methods; and/or
Preparing a metal gate line electrode layer (260) on the transparent electrode (250) includes: preparing a metal gate line electrode layer (260) on the transparent electrode (250) by adopting evaporation, printing and electroplating methods; and/or
Preparing an anti-reflection layer (270) on the metal gate line electrode layer (260) includes: an anti-reflection layer (270) is prepared on the metal gate line electrode layer (260) by vapor deposition, sputtering and atomic deposition methods.
7. The method for manufacturing a perovskite crystalline silicon stacked solar cell as claimed in any one of claims 1 to 6, wherein: and forming an N-type doped emitter layer (180) on the top surface of the silicon wafer substrate (110) through a tubular boron diffusion or chained boron diffusion method between the steps S100 and S200 or between the steps S300 and S400, wherein the first passivation layer (140) is formed on the surface of the N-type doped emitter layer (180).
8. The method for manufacturing a perovskite crystalline silicon stacked solar cell as claimed in any one of claims 1 to 6, wherein: and preparing a P-type silicon wafer with the resistivity of 1-5 ohm-cm for standby by a suspension zone melting method before the step S100.
9. A solar cell structure produced by the solar cell production method according to any one of claims 1 to 8, wherein the solar cell structure is a layered structure and comprises a bottom electrode unit (100) at the bottom and a top electrode unit (200) at the top, the bottom electrode unit (100) and the top electrode unit (200) being stacked to form a whole;
the bottom electrode unit (100) comprises a silicon wafer substrate (110), wherein the silicon wafer substrate (110) is made of P-type silicon, a bottom electrode open-pore passivation layer (120) is formed on the bottom surface of the silicon wafer substrate (110), and a metal bottom electrode layer (130) is arranged on the bottom surface of the bottom electrode open-pore passivation layer (120); a first passivation layer (140) is formed on the top surface of the silicon wafer substrate (110), an N-type heavily doped polycrystalline layer (150) is formed on the top surface of the first passivation layer (140), a second passivation layer (160) is formed on the top surface of the N-type heavily doped polycrystalline layer (150), and a P-type heavily doped polycrystalline layer (170) is formed on the top surface of the second passivation layer (160);
the top electrode unit (200) comprises a hole transmission layer (210), wherein the bottom surface of the hole transmission layer (210) is connected to the top surface of the P-type heavily doped polycrystalline layer (170), a perovskite light absorption layer (220) is arranged on the top surface of the hole transmission layer (210), an electron transmission layer (230) is arranged on the top surface of the perovskite light absorption layer (220), a top electrode buffer layer (240) is arranged on the top surface of the electron transmission layer (230), a transparent electrode (250) is arranged on the top surface of the top electrode buffer layer (240), a metal gate line electrode layer (260) is arranged on the top surface of the transparent electrode (250), and an antireflection layer (270) is arranged on the top surface of the metal gate line electrode layer (260); the material of the transparent electrode (250) comprises ITO, IZO, AZO and graphene.
10. The solar cell structure of claim 9, wherein an N-type doped emitter layer (180) is formed between the silicon substrate (110) and the first passivation layer (140), and a bottom surface of the N-type doped emitter layer (180) is connected to a top surface of the silicon substrate (110), and a top surface of the N-type doped emitter layer (180) is connected to a bottom surface of the first passivation layer (140).
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