CN111199962A - Solar cell and preparation method thereof - Google Patents

Solar cell and preparation method thereof Download PDF

Info

Publication number
CN111199962A
CN111199962A CN201811368172.9A CN201811368172A CN111199962A CN 111199962 A CN111199962 A CN 111199962A CN 201811368172 A CN201811368172 A CN 201811368172A CN 111199962 A CN111199962 A CN 111199962A
Authority
CN
China
Prior art keywords
cell
sub
layer
gallium arsenide
crystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811368172.9A
Other languages
Chinese (zh)
Inventor
许吉林
乔秀梅
刘琦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zishi Energy Co.,Ltd.
Original Assignee
Dongtai Hi Tech Equipment Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongtai Hi Tech Equipment Technology Co Ltd filed Critical Dongtai Hi Tech Equipment Technology Co Ltd
Priority to CN201811368172.9A priority Critical patent/CN111199962A/en
Publication of CN111199962A publication Critical patent/CN111199962A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a front electrode, a perovskite sub cell, a gallium arsenide sub cell, a crystalline silicon sub cell and a back electrode which are sequentially stacked from top to bottom, wherein the crystalline silicon sub cell is connected with the gallium arsenide sub cell through a bonding layer, and the perovskite sub cell is connected with the gallium arsenide sub cell through a composite layer. The perovskite/gallium arsenide/crystalline silicon laminated cell is prepared by heterologously integrating the perovskite cell, the gallium arsenide cell and the crystalline silicon cell, a plurality of semiconductor materials with different band gap widths form a multi-junction solar cell, and each sub-cell is used for absorbing a solar wave band matched with the band gap width of the sub-cell, so that the solar spectrum is maximally and effectively utilized, and the photoelectric conversion efficiency is maximally improved; meanwhile, the perovskite material has rich sources, low price and simple preparation process, and the cost is further reduced.

Description

Solar cell and preparation method thereof
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a solar cell and a preparation method thereof.
Background
Crystalline silicon solar cell technology is the most mature commercial photovoltaic power generation technology at present, and other types of solar cells such as thin film cells, compound cells and the like are difficult to replace crystalline silicon cells in a short time due to the advantages of the crystalline silicon solar cell technology in terms of comprehensive cost and conversion efficiency. Therefore, the method has important significance for continuously improving the performance of the crystalline silicon battery and continuously optimizing the process to reduce the cost. The theoretical limit efficiency of the crystalline silicon battery is only about 29%, and the aim of greatly improving the efficiency of the crystalline silicon battery is difficult.
Gallium arsenide (GaAs) cells are typical III-V compound solar cells and are the solar cell material system with the highest photoelectric conversion efficiency at present. The photoelectric conversion efficiency of the multijunction III-V group compound solar cell can reach more than 33 percent, but the multijunction III-V group compound solar cell has the defect of high cost and is only applied to space solar cells and concentrating solar cells at present.
Therefore, there is a need in the art to provide a solar cell with low cost while achieving high conversion efficiency.
Disclosure of Invention
The invention mainly aims to provide a solar cell and a preparation method thereof, and aims to solve the problem that the solar cell in the prior art cannot simultaneously have high conversion efficiency and low cost.
In order to achieve the above object, according to one aspect of the present invention, there is provided a solar cell including a front electrode, a perovskite sub-cell, a gallium arsenide sub-cell, a crystalline silicon sub-cell, and a back electrode, which are sequentially stacked from top to bottom, the crystalline silicon sub-cell and the gallium arsenide sub-cell being connected through a bonding layer, and the perovskite sub-cell and the gallium arsenide sub-cell being connected through a recombination layer.
Furthermore, the composite layer is a silver nanowire/PEDOT/PSS composite layer.
Further, the mass percentage of the silver nanowires in the composite layer is 2-10%.
Further, the bonding layer is a surface-roughened bonding layer.
According to another aspect of the present invention, there is provided a method for manufacturing the solar cell, including the steps of: s1, forming a crystalline silicon sub-cell, and forming a back electrode on one side of the crystalline silicon sub-cell; s2, forming a gallium arsenide sub-battery, and connecting one side of the crystalline silicon sub-battery, which is far away from the back electrode, with the gallium arsenide sub-battery by adopting a bonding process to obtain a laminated battery structure connected by a bonding layer; and S3, sequentially forming a composite layer and a perovskite sub-cell on the side, far away from the back electrode, of the laminated cell structure, so that the titanium ore sub-cell and the gallium arsenide sub-cell are connected through the composite layer, and forming a front electrode on the surface of the perovskite sub-cell to obtain the solar cell.
Furthermore, the bonding process is pressure bonding, and the pressure is 2.0-3.0 kN.
Further, the pressure bonding conditions are: vacuum degree of 10-6～10-8Pa, the bonding time is 0.5-3 h or the roughness of the contact surface of the gallium arsenide sub-battery and the crystalline silicon sub-battery is less than 1.0 nm.
Further, annealing treatment at 200-500 ℃ is carried out on the laminated battery structure after bonding.
Further, the step of forming the composite layer includes: and spin-coating a mixed solution containing silver nanowires and PEDOT (PSS) on the surface of the GaAs sub-battery, drying to obtain a silver nanowire/PEDOT (PSS) composite layer, and preferably heating the mixed solution at 100-150 ℃ for 0.5-2 h for drying.
Further, the mass fraction of the silver nanowires in the mixed solution is 0.1-2.0%.
By applying the technical scheme of the invention, the perovskite cell, the gallium arsenide cell and the crystalline silicon cell are heterogeneously integrated to prepare the perovskite/gallium arsenide/crystalline silicon laminated cell, a plurality of semiconductor materials with different band gap widths form the multi-junction solar cell, and each sub-cell is used for absorbing a solar light wave band matched with the band gap width of the sub-cell, so that the solar spectrum is maximally and effectively utilized, and the photoelectric conversion efficiency is maximally improved; meanwhile, the perovskite material has rich sources, low price and simple preparation process, and the cost is further reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view of a solar cell provided in the prior art;
fig. 2 is a schematic cross-sectional structure diagram of a substrate after a crystalline silicon sub-cell is formed and a back electrode is formed on one side of the crystalline silicon sub-cell in the method for manufacturing a solar cell provided in the embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of the substrate after forming a GaAs subcell;
FIG. 4 is a schematic cross-sectional view of the substrate after bonding the crystalline silicon subcell of FIG. 2 to the gallium arsenide subcell of FIG. 3; and
fig. 5 shows a schematic cross-sectional structure of the substrate after forming a perovskite sub-cell on the side of the stacked cell structure shown in fig. 4 remote from the back electrode and forming a front electrode on the surface of the perovskite sub-cell.
Wherein the figures include the following reference numerals:
1. a crystalline silicon substrate; 21. a first tunneling SiOx layer; 22. a second tunneling SiOx layer; 3. an n-type heavily doped polysilicon layer; 4. a p-type heavily doped polysilicon layer; 5. a back electrode; 6. a GaAs substrate; 7. a sacrificial layer; 8. an n-type GaAs layer; 9. a window layer; 10. a non-doped GaAs layer; 11. a back field layer; 12. a p-type AlGaAs layer; 13. a bonding layer; 14. compounding layers; 16. a perovskite layer; 17. an electron transport layer; 18. a transparent conductive film; 19. and a front electrode.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, there is a need in the art to provide a solar cell with low cost while achieving high conversion efficiency. The inventor of the present invention has made a study to solve the above problems, and has proposed a solar cell, as shown in fig. 1, including a front electrode 19, a perovskite sub-cell, a gallium arsenide sub-cell, a crystalline silicon sub-cell, and a back electrode 5, which are stacked in this order from top to bottom, wherein the crystalline silicon sub-cell and the gallium arsenide sub-cell are connected by a bonding layer 13, and the perovskite sub-cell and the gallium arsenide sub-cell are connected by a recombination layer 14.
In the solar cell, the perovskite cell, the gallium arsenide cell and the crystalline silicon cell are heterogeneously integrated to prepare the perovskite/gallium arsenide/crystalline silicon laminated cell, so that a plurality of semiconductor materials with different band gap widths can form a multi-junction solar cell, and each sub-cell is used for absorbing a solar wave band matched with the band gap width of the sub-cell, thereby realizing the maximum effective utilization of solar spectrum and furthest improving the photoelectric conversion efficiency; meanwhile, the perovskite material has rich sources, low price and simple preparation process, and the cost is further reduced.
In the solar cell of the present invention, the bonding layer 13 is formed by a bonding process to achieve a firm connection between the gaas sub-cell and the crystalline si sub-cell. Specifically, the above bonding layer 13 may be formed by bonding the n-type heavily doped polysilicon layer 3 in the crystalline silicon subcell with the p-type AlGaAs layer 12 in the gallium arsenide subcell. In order to enhance the bonding effect, the bonding layer 13 is preferably a surface-roughened bonding layer.
In the solar cell of the present invention, preferably, the composite layer 14 is a silver nanowire/PEDOT: PSS composite layer; more preferably, the thickness of the composite layer 14 is 50 to 100 nm.
In order to improve the conversion efficiency of the solar cell, in a preferred embodiment, the crystalline silicon sub-cell comprises a p-type heavily doped polysilicon layer 4, a first tunneling SiOx layer 21, a crystalline silicon substrate 1, a second tunneling SiOx layer 22 and an n-type heavily doped polysilicon layer 3 which are sequentially stacked in a direction away from the back electrode 5, wherein the crystalline silicon substrate 1 is n-type doped or p-type doped, and x is greater than 0 and less than or equal to 2.
In order to improve the conversion efficiency of the solar cell and ensure that the solar cell can have a smaller size, in the preferred embodiment, the thicknesses of the first tunneling SiOx layer 21 and the second tunneling SiOx layer 22 independently satisfy 1.0 to 2.0 nm; more preferably, the thicknesses of the p-type heavily doped polysilicon layer 4 and the n-type heavily doped polysilicon layer 3 independently satisfy 50 to 200 nm.
In order to improve the conversion efficiency of the solar cell, in a preferred embodiment, the above-described gallium arsenide subcell includes a p-type AlGaAs layer 12, a back field layer 11, an undoped GaAs layer 10, a window layer 9 and an n-type GaAs layer 8 sequentially stacked in a direction away from the back surface electrode. More preferably, the back field layer 11 is an InGaP layer; more preferably, the window layer 9 is an AlGaInP layer.
In order to improve the conversion efficiency of the solar cell and ensure a small size, in the above preferred embodiment, it is more preferred that the thickness of the n-type GaAs layer 8 is 10 to 50nm, the thickness of the window layer 9 is 10 to 50nm, the thickness of the undoped GaAs layer 10 is 100 to 500nm, the thickness of the back field layer 11 is 10 to 100nm, and the thickness of the p-type AlGaAs layer 12 is 10 to 50 nm.
In order to improve the conversion efficiency of the solar cell, in a preferred embodiment, the perovskite sub-cell comprises a perovskite layer 16, an electron transport layer 17 and a transparent conductive film 18 sequentially stacked on the composite layer 14 in a direction away from the back electrode.
In order to further improve the conversion efficiency of the solar cell, in the above preferred embodiment, it is more preferred that the transparent conductive film 18 is selected from any one of an ITO film and an FTO film; more preferably, the PCBM electron transport layer material of the electron transport layer 17 is selected from TiO2、ZnO、PCBM、SnO2And PCBM; more preferably, the band gap of the perovskite layer 16 is 1.7 to 2.0eV, and more preferably, the perovskite layer 16 is formed of CsPb0.9Sn0.1IBr2。
In order to improve the conversion efficiency of the solar cell and ensure that the solar cell can have a small size, in the above preferred embodiment, the thickness of the transparent conductive film 18 more preferably satisfies 10 to 100 nm; more preferably, the thickness of the electron transport layer 17 is 10 to 150 nm; more preferably, the thickness of the perovskite layer 16 is 50 to 1000 nm.
In the solar cell of the present invention, the material forming the back electrode 5 may be any one or more selected from silver paste, aluminum paste, copper paste, nickel paste and carbon paste electrode, and the thickness is preferably 100-; the material forming the front electrode 19 may be any one selected from gold, silver, platinum and copper, and the thickness is preferably 100-1000 nm. But not limited to the above, the material of the back electrode 5 and the front electrode 19 can be selected appropriately by those skilled in the art according to the prior art.
According to another aspect of the present invention, there is also provided a method for manufacturing the above solar cell, as shown in fig. 2 to 5, including the steps of: s1, forming a crystalline silicon sub-cell, and forming a back electrode 5 on one side of the crystalline silicon sub-cell; s2, forming a gallium arsenide sub-battery, and connecting one side of the crystalline silicon sub-battery, which is far away from the back electrode 5, with the gallium arsenide sub-battery by adopting a bonding process to obtain a laminated battery structure connected by the bonding layer 13; s3, a composite layer 14 and a perovskite sub-cell are sequentially formed on the side of the stacked cell structure away from the back electrode 5, so that the titanium sub-cell and the gallium arsenide sub-cell are connected by the composite layer 14, and the front electrode 19 is formed on the surface of the perovskite sub-cell, thereby obtaining a solar cell.
An exemplary embodiment of a method for manufacturing a solar cell provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: a crystalline silicon subcell is formed and a back electrode 5 is formed on one side of the crystalline silicon subcell as shown in fig. 2.
The above step S1 may include the following processes: sequentially adopting deionized water, alcohol, acetone and HF acid to crystallize the silicon substrate 1, naturally airing, and then respectively preparing a first tunneling SiOx layer 21 and a second tunneling SiOx layer 22 on two sides of the silicon wafer by adopting a nitric acid oxidation (with the concentration of 10% -20%), ozone oxidation or thermal oxygen oxidation (with the temperature of 200-; depositing a p-type heavily doped polysilicon layer 4 and an n-type heavily doped polysilicon layer 3 on two sides of a crystalline silicon substrate 1 respectively by adopting a Low Pressure Chemical Vapor Deposition (LPCVD) method, and then performing high-temperature annealing at the annealing temperature of 800-; and finally, screen printing a back electrode 5 on the surface of the crystalline silicon sub-battery.
After the step S1 is performed, a step S2 is performed: a gallium arsenide subcell is formed and the side of the crystalline silicon subcell remote from the back electrode 5 is connected to the gallium arsenide subcell to obtain a stacked cell structure as shown in fig. 3 and 4.
In a preferred embodiment, the crystalline silicon sub-battery comprises a p-type heavily doped polysilicon layer 4, a first tunneling SiOx layer 21, a crystalline silicon matrix 1, a second tunneling SiOx layer 22 and an n-type heavily doped polysilicon layer 3 which are sequentially stacked along the direction far away from a back electrode 5, wherein the crystalline silicon matrix 1 is n-type doped or p-type doped, and x is more than 0 and less than or equal to 2; at this time, the above step S2 includes the following processes: s21, sequentially forming a buffer layer, a sacrificial layer 7, an n-type GaAs layer 8, a window layer 9, a non-doped GaAs layer 10, a back field layer 11 and a p-type AlGaAs layer 12 on the GaAs substrate 6 to obtain a GaAs sub-battery; and S22, bonding the n-type heavily doped polysilicon layer 3 in the crystalline silicon sub-cell with the p-type AlGaAs layer 12 to obtain a laminated cell structure.
In the step S21, the functional layers may be sequentially formed on the GaAs substrate 6 by using an MOCVD epitaxial growth method, and those skilled in the art can reasonably set the process conditions for forming the functional layers according to the prior art; in order to remove the buffer layer more effectively in the subsequent steps, it is more preferable that the buffer layer is formed of GaAs; further, more preferably, the material forming the sacrifice layer 7 is AlAs.
In step S22, in order to further realize a firm connection between the crystalline silicon sub-cell and the gallium arsenide sub-cell, it is more preferable that the surface roughness of the n-type heavily doped polysilicon layer 3 and the p-type AlGaAs layer 12 is less than 1.0 nm; more preferably, the vacuum degree is 10-6～10-8Bonding is carried out under the condition of Pa; more preferably, the bonding pressure is 2.0-3.0 kN, and the bonding time is 0.5-3 h; and, more preferably, the stacked cell structure is subjected to annealing treatment at a temperature of 200 to 500 ℃ after bonding.
The above step S22 may include the following processes: transferring the prepared crystalline silicon sub-battery and gallium arsenide sub-battery into a bonding machine, vacuumizing to a vacuum degree of 10-6-10-8Pa; firstly, polishing the upper surface (n-type heavily doped polysilicon layer 3) of a crystalline silicon sub-cell and the lower surface (p-type AlGaAs layer 12) of a gallium arsenide sub-cell by adopting ion beams to ensure that the surface roughness is less than 1.0 nm; then at room temperature, 2.0-3Bonding the wafer under the pressure of 0kN for 0.5-3 h, and annealing at 200-500 deg.C.
Before the step of forming the perovskite sub-cell, it is more preferable that the above step S2 further comprises the step of removing the sacrificial layer 7 to separate the gallium arsenide sub-cell from the GaAs substrate 6. Specifically, the GaAs substrate can be separated from the stack structure by selectively etching away the sacrificial AlAs layer using HF acid solution (10% concentration) on the bonded stack. After the bonding of the crystalline silicon sub-battery and the gallium arsenide sub-battery is finished, the GaAs substrate 6 is completely stripped, and after proper treatment, the gallium arsenide battery thin film can be grown by repeated epitaxy of the crystalline silicon sub-battery and the gallium arsenide sub-battery, so that the purpose of recycling the substrate is achieved.
After the above step S2 is performed, step S3 is performed: a composite layer 14 and a perovskite sub-cell are sequentially formed on the side of the laminated cell structure far from the back electrode 5, so that the titanium sub-cell and the gallium arsenide sub-cell are connected through the composite layer 14, and a front electrode 19 is formed on the surface of the perovskite sub-cell, so as to obtain the solar cell, as shown in fig. 5.
In a preferred embodiment, the step S3 includes the following steps: s31, spin-coating a mixed solution containing silver nanowires and PEDOT: PSS on the surface of the laminated battery structure, and drying to obtain a silver nanowire/PEDOT: PSS composite layer (namely the composite layer 14); s32, forming a perovskite layer 16 on the surface of the composite layer 14; s33, forming an electron transport layer 17 on the surface of the perovskite layer 16; s34, a transparent conductive film 18 is formed on the surface of the electron transit layer 17.
In the preferred embodiment, a silver nanowire/PEDOT/PSS mixed solution can be prepared on the upper surface of the gallium arsenide/crystalline silicon laminated battery structure by spin coating, and the silver nanowire/PEDOT/PSS mixed solution is obtained after drying, and is preferably dried at 100-150 ℃ for 0.5-2 h, and the mass fraction of the silver nanowire in the mixed solution is preferably 0.1-2.0%; then, a perovskite layer 16 and an electron transport layer 17 are sequentially prepared on the silver nanowire/PEDOT PSS composite layer 14, and the preparation method comprises any one of a solution spin coating method, a thermal evaporation method, a co-evaporation method, a chemical vapor deposition method and an atomic layer deposition method; then, a transparent conductive film 18 may be formed on the electron transport layer 17 by magnetron sputtering; finally, the front electrode 19 can be prepared by thermal evaporation.
The solar cell and the method for manufacturing the solar cell provided by the invention will be further described with reference to the following examples.
Example 1
The present example relates to a solar cell, which is prepared as follows:
firstly, a p-type silicon wafer sample is used as a crystalline silicon substrate 1, deionized water, alcohol, acetone and HF acid are sequentially used for cleaning, after natural drying, a first tunneling SiOx layer 21 and a second tunneling SiOx layer 22 are respectively prepared on two sides of the crystalline silicon substrate 1 by a nitric acid oxidation (with the concentration of 15%), and the thicknesses of the first tunneling SiOx layer and the second tunneling SiOx layer are 1.5 nm;
step two, adopting a low pressure chemical vapor deposition method (LPCVD) to respectively deposit p on two sides of the crystalline silicon substrate 1+poly-Si layer (p-type heavily doped polysilicon layer 4), n+A poly-Si layer (an n-type heavily doped polysilicon layer 3) with the thickness of 150nm is annealed at the high temperature of 1000 ℃;
step three, screen printing a back Al electrode to form a back electrode 5 with the thickness of 2000nm, thereby preparing a crystalline silicon sub-battery, as shown in FIG. 2;
step four, cleaning the GaAs substrate 6 by using deionized water and alcohol, and sequentially preparing a GaAs buffer layer, an AlAs sacrificial layer 7, an n-type GaAs layer 8, an AlGaInP window layer 9, a non-doped GaAs layer 10, an InGaP back field layer 11 and a p-type AlGaAs layer 12 on the substrate by adopting an MOCVD epitaxial growth method; specifically, the method comprises the following steps:
the thickness of the n-type GaAs layer 8 is 30nm, the thickness of the AlGaInP window layer 9 is 20nm, the thickness of the undoped GaAs layer 10 is 500nm, the thickness of the InGaP back field layer 11 is 20nm, and the thickness of the p-type AlGaAs layer 12 is 50nm, thereby preparing a GaAs sub-cell, as shown in FIG. 3;
fifthly, transferring the prepared crystalline silicon sub-battery and the prepared gallium arsenide sub-battery into a bonding machine, vacuumizing, and setting the vacuum degree to be 10-8Pa; firstly, polishing the upper surface (n-type heavily doped polysilicon layer 3) of a crystalline silicon sub-cell and the lower surface (p-type AlGaAs layer 12) of a gallium arsenide sub-cell by adopting ion beams to ensure that the surface roughness is less than 1.0 nm; then in the chamberCarrying out wafer bonding under the conditions of temperature and 2kN pressure for 3 hours, and carrying out annealing treatment after the bonding is finished, wherein the annealing temperature is 500 ℃, so that a gallium arsenide/crystalline silicon laminated cell structure is prepared, as shown in FIG. 4;
step six, selectively corroding the AlAs sacrificial layer 7 on the bonded gallium arsenide/crystalline silicon laminated cell structure by adopting an HF acid solution (with the concentration of 10 percent), so as to separate the GaAs substrate 6 from the laminated cell structure;
step seven, spin-coating a layer of silver nanowire/PEDOT (PSS) mixed solution on the upper surface solution of the gallium arsenide/crystalline silicon laminated battery structure, and drying at 100 ℃ for 2 hours to obtain a silver nanowire/PEDOT (PSS) composite layer 14, wherein the thickness of the prepared composite layer is 100 nm; the mass fraction of the silver nanowires in the mixed solution is 0.2 percent;
step eight, preparing the CsPbI2Br perovskite layer 16 on the composite layer by adopting a thermal evaporation method, wherein the band gap is 1.9eV, and the thickness is 850 nm; preparing a ZnO electron transmission layer 17 by adopting a chemical vapor deposition method, wherein the thickness is 100 nm;
step nine, performing magnetron sputtering on a layer of ITO (transparent conductive film 18) on the electronic transmission layer 17, wherein the thickness of the ITO is 80nm, and then preparing an Au front electrode 19 by adopting a thermal evaporation method, wherein the thickness of the Au front electrode is 200 nm; thereby preparing a perovskite/gallium arsenide/crystalline silicon tandem cell as shown in fig. 5.
Example 2
The present example relates to a solar cell, which is prepared as follows:
step one, adopting an n-type silicon wafer sample as a crystalline silicon substrate 1, sequentially using deionized water, alcohol, acetone and HF acid for cleaning, naturally drying, and preparing tunneling SiO on two sides of the crystalline silicon substrate 1 by adopting a thermal oxidation method (at the temperature of 400 ℃)xThe thickness of each of the layers (the first tunneling SiOx layer 21 and the second tunneling SiOx layer 22) is 1.7 nm;
step two, respectively depositing p on two sides of the crystalline silicon substrate 1 by adopting a low pressure chemical vapor deposition method (LPCVD)+poly-Si layer (p-type heavily doped polysilicon layer 4), n+A poly-Si layer (an n-type heavily doped polysilicon layer 3) with the thickness of 100nm is annealed at the high temperature of 950 ℃;
step three, screen printing a back Ag/Cu alloy electrode to form a back electrode 5 with the thickness of 1000nm, thereby preparing the crystalline silicon sub-battery, as shown in FIG. 2;
step four, cleaning the GaAs substrate 6 by using deionized water and alcohol, and sequentially preparing a GaAs buffer layer, an AlAs sacrificial layer 7, an n-type GaAs layer 8, an AlGaInP window layer 9, a non-doped GaAs layer 10, an InGaP back field layer 11 and a p-type AlGaAs layer 12 on the substrate by adopting an MOCVD epitaxial growth method; specifically, the method comprises the following steps:
the thickness of the n-type GaAs layer 8 is 20nm, the thickness of the AlGaInP window layer 9 is 40nm, the thickness of the undoped GaAs layer 10 is 300nm, the thickness of the InGaP back field layer 11 is 60nm, and the thickness of the p-type AlGaAs layer 12 is 10nm, so that a GaAs sub-cell is prepared, as shown in FIG. 3;
fifthly, transferring the prepared crystalline silicon sub-battery and the prepared gallium arsenide sub-battery into a bonding machine, vacuumizing, and setting the vacuum degree to be 10-6Pa; firstly, polishing the upper surface (n-type heavily doped polysilicon layer 3) of a crystalline silicon sub-cell and the lower surface (p-type AlGaAs layer 12) of a gallium arsenide sub-cell by adopting ion beams to ensure that the surface roughness is less than 1.0 nm; then carrying out wafer bonding at room temperature under the condition of 3kN pressure for 0.5h, and carrying out annealing treatment at 200 ℃ after the wafer bonding is finished, thereby preparing the gallium arsenide/crystalline silicon laminated cell as shown in figure 4;
step six, selectively corroding the AlAs sacrificial layer 7 on the bonded gallium arsenide/crystalline silicon laminated cell by adopting an HF acid solution (with the concentration of 10 percent), thereby separating the GaAs substrate 6 from the laminated cell structure;
step seven, spin-coating a layer of silver nanowire/PEDOT (PSS) mixed solution on the upper surface solution of the gallium arsenide/crystalline silicon laminated battery structure, and drying for 0.5h at 150 ℃ to obtain a silver nanowire/PEDOT (PSS) composite layer 14, wherein the thickness of the prepared composite layer is 50 nm; the mass fraction of the silver nanowires in the mixed solution is 2 percent;
step eight, preparing CsPb on the composite layer by adopting a co-evaporation method0.9Sn0.1IBr2 A perovskite layer 16 with a band gap of 1.79eV and a thickness of 600 nm; preparing a PCBM electron transport layer 17 by adopting a solution spin-coating method, wherein the thickness is 80 nm;
step nine, performing magnetron sputtering on a layer of FTO (transparent conductive film 18) on the electronic transmission layer 17, wherein the thickness of the FTO is 60nm, and then preparing an Au front electrode 19 by adopting a thermal evaporation method, wherein the thickness of the Au front electrode is 300 nm; thereby preparing a perovskite/gallium arsenide/crystalline silicon tandem cell as shown in fig. 5.
Example 3
The difference between the preparation method of the tandem solar cell provided in this embodiment and embodiment 1 is that:
step seven, spin-coating a layer of silver nanowire/PEDOT (PSS) mixed solution on the upper surface solution of the gallium arsenide/crystalline silicon laminated battery structure, and drying at 120 ℃ for 1h to obtain a silver nanowire/PEDOT (PSS) composite layer 14, wherein the thickness of the prepared composite layer is 80 nm; the mass fraction of the silver nanowires in the mixed solution was 0.5%.
Example 4
The difference between the preparation method of the tandem solar cell provided in this embodiment and embodiment 1 is that:
PSS composite layer 14 is not used, but in the seventh step, a layer of transparent conducting film ITO is sputtered on the upper surface of the GaAs/crystalline silicon laminated cell structure, and then a layer of PEDOT is spin-coated on the ITO, wherein PSS is used as a hole transport layer;
example 5
The difference between the preparation method of the solar cell provided in this embodiment and embodiment 1 is that:
in step five, the degree of vacuum is set to 10-5Pa; firstly, polishing the upper surface (n-type heavily doped polysilicon layer 3) of a crystalline silicon sub-cell and the lower surface (p-type AlGaAs layer 12) of a gallium arsenide sub-cell by adopting ion beams to ensure that the surface roughness is more than or equal to 1.0 nm; and then carrying out wafer bonding at room temperature under the pressure of 1.8kN for 0.4h, and carrying out annealing treatment at 180 ℃.
The solar cells of examples 1 to 5 were tested for conversion efficiency using the IV test method, and the results are shown in the following table.
/ Example 1 Example 2 Example 3 Example 4 Example 5
Conversion efficiency/%) 30.6％ 29.5％ 29.8％ 28.1％ 27.2％
The test results show that the photoelectric conversion efficiency of the triple-junction laminated cell is greatly improved compared with that of a single-junction cell, and the wafer bonding process of the crystalline silicon cell and the gallium arsenide cell and the composite layer design of the interface of the crystalline silicon cell and the gallium arsenide cell are beneficial to improving the conversion efficiency of the laminated cell.
The specific I-V test method comprises the following test conditions: at 25 ℃, AM1.5G, 100mW cm～2(ii) a The main test equipment: the efficiency of the cell was measured using a solar simulator, standard silicon detector, Keithley 2400 source meter, IV tester, etc.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
1. according to the invention, a perovskite cell, a gallium arsenide cell and a crystalline silicon cell are heterogeneously integrated together to prepare a perovskite/gallium arsenide/crystalline silicon laminated cell, a plurality of semiconductor materials with different band gap widths form a multi-junction solar cell, and each sub-cell is used for absorbing a solar light wave band matched with the band gap width of the sub-cell, so that the solar spectrum is maximally and effectively utilized, and the photoelectric conversion efficiency is maximally improved;
2. the perovskite material has rich sources, low price and simple preparation process, and the cost is further reduced;
3. after the bonding of the crystalline silicon battery and the gallium arsenide battery is finished, the gallium arsenide substrate is completely peeled off, and after proper treatment, the gallium arsenide battery film can be grown by repeated epitaxy of the gallium arsenide substrate, so that the aim of recycling the substrate is fulfilled.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A solar cell comprises a front electrode (19), a perovskite sub-cell, a gallium arsenide sub-cell, a crystalline silicon sub-cell and a back electrode (5) which are sequentially stacked from top to bottom, wherein the crystalline silicon sub-cell is connected with the gallium arsenide sub-cell through a bonding layer (13), and the perovskite sub-cell is connected with the gallium arsenide sub-cell through a composite layer (14).
2. Solar cell according to claim 1, characterized in that the composite layer (14) is a silver nanowire/PEDOT: PSS composite layer.
3. The solar cell according to claim 2, wherein the composite layer comprises 2-10% by mass of silver nanowires.
4. Solar cell according to claim 1, characterized in that the bonding layer (13) is a surface roughened bonding layer.
5. A method for manufacturing a solar cell according to any one of claims 1 to 4, comprising the steps of:
s1, forming a crystalline silicon sub-cell, and forming a back electrode (5) on one side of the crystalline silicon sub-cell;
s2, forming a gallium arsenide sub-battery, and connecting one side of the crystalline silicon sub-battery, which is far away from the back electrode (5), with the gallium arsenide sub-battery by adopting a bonding process to obtain a laminated battery structure connected by a bonding layer (13);
and S3, sequentially forming a composite layer (14) and a perovskite sub-cell on one side of the laminated cell structure far away from the back electrode (5), so that the titanium ore sub-cell and the gallium arsenide sub-cell are connected through the composite layer (14), and forming a front electrode (19) on the surface of the perovskite sub-cell to obtain the solar cell.
6. The method according to claim 5, wherein the bonding process is pressure bonding, and the pressure is 2.0-3.0 kN.
7. The production method according to claim 6, wherein the pressure bonding conditions are: vacuum degree of 10-6～10-8Pa, the bonding time is 0.5-3 h or the roughness of the contact surface of the gallium arsenide sub-battery and the crystalline silicon sub-battery is less than 1.0 nm.
8. The method according to claim 7, further comprising annealing the laminated cell structure at a temperature of 200 to 500 ℃ after the bonding.
9. The method of manufacturing according to claim 5, wherein the step of forming the composite layer (14) comprises:
and spin-coating a mixed solution containing silver nanowires and PEDOT and PSS on the surface of the gallium arsenide sub-battery, drying to obtain a silver nanowire/PEDOT and PSS composite layer, and preferably heating the mixed solution at 100-150 ℃ for 0.5-2 h to perform drying.
10. The preparation method according to claim 9, wherein the mass fraction of the silver nanowires in the mixed solution is 0.1-2.0%.
CN201811368172.9A 2018-11-16 2018-11-16 Solar cell and preparation method thereof Pending CN111199962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811368172.9A CN111199962A (en) 2018-11-16 2018-11-16 Solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811368172.9A CN111199962A (en) 2018-11-16 2018-11-16 Solar cell and preparation method thereof

Publications (1)

Publication Number Publication Date
CN111199962A true CN111199962A (en) 2020-05-26

Family

ID=70745677

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811368172.9A Pending CN111199962A (en) 2018-11-16 2018-11-16 Solar cell and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111199962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690340A (en) * 2021-07-23 2021-11-23 深圳黑晶光电技术有限公司 Perovskite crystal silicon laminated solar cell manufacturing method and cell structure

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407506A (en) * 1992-06-04 1995-04-18 Alliedsignal Inc. Reaction bonding through activation by ion bombardment
CN1751387A (en) * 2003-02-12 2006-03-22 硅绝缘技术公司 Semiconductor structure on an extremely rough substrate
US20100216294A1 (en) * 2007-10-12 2010-08-26 Marc Rabarot Method of fabricating a microelectronic structure involving molecular bonding
CN102593229A (en) * 2011-01-11 2012-07-18 朱忻 Multi-junction solar cell and manufacturing method thereof
CN102779865A (en) * 2012-08-09 2012-11-14 厦门大学 Silicon-based triple-junction solar battery using germanium as tunneling junction
US20130240027A1 (en) * 2010-06-07 2013-09-19 Solarno, Inc. Multijunction hybrid solar cell with parallel connection and nanomaterial charge collecting interlayers
CN105185860A (en) * 2015-09-25 2015-12-23 郑州轻工业学院 Bonding connected silicon substrate and gallium arsenide substrate solar cell
US20160027935A1 (en) * 2012-03-30 2016-01-28 Kabushiki Kaisha Toshiba Method for producing stacked electrode and method for producing photoelectric conversion device
CN106653950A (en) * 2016-12-30 2017-05-10 中国电子科技集团公司第十八研究所 Preparation method of gallium arsenide-silicon multi-junction efficient solar cell
US20170207033A1 (en) * 2016-05-09 2017-07-20 Solar-Tectic, Llc Maximizing the power conversion efficiency of a tin perovskite/silicon thin-film tandem solar cell
CN107046027A (en) * 2016-12-30 2017-08-15 中国电子科技集团公司第十八研究所 Perovskite and gallium arsenide hetero-integrated solar cell manufacturing method and cell
CN107924933A (en) * 2015-06-12 2018-04-17 牛津光电有限公司 More knot photovoltaic devices

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407506A (en) * 1992-06-04 1995-04-18 Alliedsignal Inc. Reaction bonding through activation by ion bombardment
CN1751387A (en) * 2003-02-12 2006-03-22 硅绝缘技术公司 Semiconductor structure on an extremely rough substrate
US20100216294A1 (en) * 2007-10-12 2010-08-26 Marc Rabarot Method of fabricating a microelectronic structure involving molecular bonding
US20130240027A1 (en) * 2010-06-07 2013-09-19 Solarno, Inc. Multijunction hybrid solar cell with parallel connection and nanomaterial charge collecting interlayers
CN102593229A (en) * 2011-01-11 2012-07-18 朱忻 Multi-junction solar cell and manufacturing method thereof
US20160027935A1 (en) * 2012-03-30 2016-01-28 Kabushiki Kaisha Toshiba Method for producing stacked electrode and method for producing photoelectric conversion device
CN102779865A (en) * 2012-08-09 2012-11-14 厦门大学 Silicon-based triple-junction solar battery using germanium as tunneling junction
CN107924933A (en) * 2015-06-12 2018-04-17 牛津光电有限公司 More knot photovoltaic devices
CN105185860A (en) * 2015-09-25 2015-12-23 郑州轻工业学院 Bonding connected silicon substrate and gallium arsenide substrate solar cell
US20170207033A1 (en) * 2016-05-09 2017-07-20 Solar-Tectic, Llc Maximizing the power conversion efficiency of a tin perovskite/silicon thin-film tandem solar cell
CN106653950A (en) * 2016-12-30 2017-05-10 中国电子科技集团公司第十八研究所 Preparation method of gallium arsenide-silicon multi-junction efficient solar cell
CN107046027A (en) * 2016-12-30 2017-08-15 中国电子科技集团公司第十八研究所 Perovskite and gallium arsenide hetero-integrated solar cell manufacturing method and cell

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
向贤碧;廖显伯;: "Ⅲ-V族太阳电池的研究和应用", 阳光能源, no. 06 *
李春静;杨瑞霞;田汉民;: "钙钛矿/晶硅叠层太阳能电池的研究进展", 物理, no. 06 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690340A (en) * 2021-07-23 2021-11-23 深圳黑晶光电技术有限公司 Perovskite crystal silicon laminated solar cell manufacturing method and cell structure
CN113690340B (en) * 2021-07-23 2024-01-30 深圳黑晶光电技术有限公司 Perovskite crystal silicon laminated solar cell manufacturing method and cell structure

Similar Documents

Publication Publication Date Title
CN111244278A (en) Non-doped crystalline silicon heterojunction perovskite laminated solar cell structure and preparation method
CN110600614B (en) Tunneling junction structure of perovskite/perovskite two-end laminated solar cell
US20140373907A1 (en) Four-Junction Quaternary Compound Solar Cell and Method Thereof
CN111081878A (en) Perovskite/silicon-based heterojunction laminated solar cell and preparation method thereof
US20140352751A1 (en) Solar cell or tandem solar cell and method of forming same
CN110970562A (en) Perovskite/crystalline silicon laminated solar cell and preparation method thereof
CN109638094A (en) Efficient heterojunction battery intrinsic amorphous silicon passivation layer structure and preparation method thereof
CN103038897A (en) Thin film solar cell with microcrystalline absorpber layer and passivation layer and method for manufacturing such a cell
CN114256387A (en) Preparation method of perovskite-heterojunction three-end MWT structure laminated solar cell
CN107170840A (en) Back contacts heterojunction solar battery and its emitter stage, solar cell preparation method
CN110085683A (en) Silicon/crystalline silicon heterogenous joint solar cell of non-impurity-doped and preparation method thereof
CN116017993A (en) Solar cell and preparation method thereof
CN108878594B (en) Silicon heterojunction photovoltaic cell and manufacturing method thereof
CN114335348B (en) PN heterojunction antimony selenide/perovskite solar cell and preparation method thereof
CN214176064U (en) Double-sided incident laminated solar cell
CN115148838B (en) Solar cell, production method and photovoltaic module
CN111199962A (en) Solar cell and preparation method thereof
CN210156406U (en) Heterojunction solar cell structure with double-layer amorphous silicon intrinsic layer
CN217182188U (en) Perovskite/silicon-germanium-based triple-junction laminated solar cell
CN110556445A (en) laminated parallel solar cell
Zhang et al. The Intermediate Connection of Subcells in Si‐based Tandem Solar Cells
CN208580756U (en) A kind of lamination series-connected solar cells
CN209150136U (en) A kind of lamination parallel connection solar battery and its GaAs/GaInP lamination parallel connection solar battery
CN109192798B (en) P-type monocrystalline silicon HIT photovoltaic cell and manufacturing method thereof
CN114744052A (en) Solar cell and photovoltaic module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210118

Address after: Unit 611, unit 3, 6 / F, building 1, yard 30, Yuzhi East Road, Changping District, Beijing 102208

Applicant after: Zishi Energy Co.,Ltd.

Address before: Room a129-1, No. 10, Zhongxing Road, science and Technology Park, Changping District, Beijing

Applicant before: DONGTAI HI-TECH EQUIPMENT TECHNOLOGY Co.,Ltd.

SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200526