CN113690138A - Semiconductor structure and method for forming semiconductor structure - Google Patents
Semiconductor structure and method for forming semiconductor structure Download PDFInfo
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- CN113690138A CN113690138A CN202010420663.4A CN202010420663A CN113690138A CN 113690138 A CN113690138 A CN 113690138A CN 202010420663 A CN202010420663 A CN 202010420663A CN 113690138 A CN113690138 A CN 113690138A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 167
- 239000010410 layer Substances 0.000 claims description 237
- 238000005530 etching Methods 0.000 claims description 37
- 239000011241 protective layer Substances 0.000 claims description 21
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
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- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- 239000012212 insulator Substances 0.000 description 4
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
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- 230000005540 biological transmission Effects 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method for forming the same, the structure comprising: a substrate including opposing first and second sides, the substrate including an active area and a connecting area; the first groove is positioned in the substrate connecting area, and comprises a first area, a second area and a third area in the direction from the first surface to the second surface of the substrate, the first area is provided with a first projection on the surface of the substrate, the second area is provided with a second projection on the surface of the substrate, the third area is provided with a third projection on the surface of the substrate, the area of the second projection is larger than that of the first projection, the area of the second projection is larger than that of the third projection, the first projection is positioned in the range of the second projection, and the third projection is positioned in the range of the second projection; a first connection layer located in the first recess and electrically connectable. The performance of the semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor technology nodes continue to shrink, the size of logic semiconductor standard cells also shrinks. There is a need to increase the density of logic semiconductor circuits to make standard cell sizes very small.
At present, scaling is used to increase the density of logic semiconductor circuits. However, the density of logic semiconductor circuits increased by scaling is limited. Therefore, it is proposed to reduce the height of the transistor cells to increase the density of the logic semiconductor circuit, i.e., to reduce the number of standard cell fins and to reduce the embedded Power line (BPR). The embedded power line is usually used in conjunction with a back-side Power Delivery Network (PDN) to increase the voltage drop.
However, the matching performance of the existing embedded power line and the back power transmission network still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising opposing first and second faces, the substrate comprising an active area and a connecting area; a first groove located in a substrate connection region, the first groove extending from a first surface to a second surface of a substrate, the first groove including a first region, a second region and a third region, the first region having a first projection on a surface of the substrate, the second region having a second projection on the surface of the substrate, the third region having a third projection on the surface of the substrate, an area of the second projection being larger than an area of the first projection, an area of the second projection being larger than an area of the third projection, the first projection being within a range of the second projection, and the third projection being within a range of the second projection; and the first connecting layer is positioned in the first groove and can be electrically connected.
Optionally, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5.
Optionally, the substrate further includes a plurality of fin structures on the first surface active region, and the fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; the connection region is located between adjacent fin structures.
Optionally, the method further includes: the protective layer is positioned on the first surface of the substrate and covers the top surface and the side wall surface of the fin structure; the second groove is positioned in the protective layer and communicated with the first groove, and part of the first connecting layer is positioned in the second groove; and the isolation layer is positioned in the second groove on the first connecting layer.
Optionally, the method further includes: a second tie layer within the substrate tie region, the second tie layer extending from the substrate second face toward the substrate first face, the second tie layer contacting the first tie layer.
Optionally, the bottom of the first connection layer has a first size, and the top of the second connection layer in contact with the first connection layer has a second size, and the first size is larger than the second size.
Optionally, the range of the first size being greater than the second size is 10% to 50%.
Optionally, the method further includes: and the conductive structures are positioned on the second surface of the substrate and are electrically connected with the second connecting layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising opposing first and second faces, the substrate comprising an active area and a connecting area; forming a first groove in a substrate connecting area, wherein the first groove extends from a first surface to a second surface of a substrate, and in the direction from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the surface of the substrate, the second area has a second projection on the surface of the substrate, the third area has a third projection on the surface of the substrate, the area of the second projection is larger than that of the first projection, the area of the second projection is larger than that of the third projection, the first projection is in the range of the second projection, and the third projection is in the range of the second projection; a first connection layer is formed in the first recess to be electrically connected.
Optionally, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5.
Optionally, the substrate further includes a plurality of fin structures on the first surface active region, and the fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; the connection region is located between adjacent fin structures.
Optionally, the method for forming the first groove includes: forming a protective layer on the first surface of the substrate, wherein the protective layer covers the top surface and the side wall surface of the fin structure; forming a first mask layer on the protective layer, wherein the first mask layer exposes the surface of the protective layer on the connecting area; etching the protective layer by taking the first mask layer as a mask until the surface of the substrate is exposed, and forming a second groove in the protective layer; and etching the substrate exposed by the second groove to form the first groove.
Optionally, the method for etching the substrate exposed by the second groove includes: etching the substrate by adopting a first etching process to form an initial first groove, wherein the side wall of the initial first groove is vertical to the bottom surface of the initial first groove; and etching the substrate exposed by the initial first groove by adopting a second etching process to form a first groove, wherein the side wall of the first groove is sunken towards the inside of the effective area.
Optionally, the first etching process includes an anisotropic dry etching process.
Optionally, the second etching process includes one or more of a wet etching process and an isotropic dry etching process.
Optionally, a portion of the first connection layer is also located in the second groove.
Optionally, after forming the first connection layer, the method further includes: and forming an isolation layer in the second groove.
Optionally, after forming the first connection layer, the method further includes: a second connection layer is formed within the substrate connection region, the second connection layer extending from the substrate second face toward the substrate first face, and the second connection layer being in contact with the first connection layer.
Optionally, the bottom of the first connection layer has a first size, and the top of the second connection layer in contact with the first connection layer has a second size, and the first size is larger than the second size.
Optionally, the range of the first size being greater than the second size is 10% to 50%.
Optionally, the forming method of the second connection layer includes: forming a second mask layer on the second surface of the substrate, wherein the second mask layer exposes the surface of the connecting region; etching the substrate by taking the second mask layer as a mask until the surface of the first connecting layer is exposed, and forming a third groove in the substrate; and forming a second connecting layer in the third groove.
Optionally, after forming the second connection layer, the method further includes: and forming a plurality of conductive structures on the second surface of the substrate, wherein the conductive structures are electrically connected with the second connecting layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure according to the technical scheme of the present invention, the substrate first plane connection region has a first groove therein, and the first groove includes a first region, a second region and a third region along a direction from the first plane to the second plane of the substrate, the first region has a first projection on the surface of the substrate, the second region has a second projection on the surface of the substrate, the third region has a third projection on the surface of the substrate, an area of the second projection is larger than an area of the first projection, an area of the second projection is larger than an area of the third projection, the first projection is in a range of the second projection, the third projection is in a range of the second projection, and the first connection layer is located in the first groove, so that a bottom area of the first connection layer is increased. On one hand, when a second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, and the condition that the second connecting layer is in contact with the first connecting layer poorly is reduced, so that the first connecting layer can be electrically connected with a subsequently formed conductive structure through the second connecting layer; on the other hand, the contact resistance of the first connection layer and the second connection layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
According to the forming method of the semiconductor structure, the first groove is formed in the connecting area of the first surface of the substrate, the first groove comprises the first area, the second area and the third area along the direction from the first surface to the second surface of the substrate, the first area has the first projection on the surface of the substrate, the second area has the second projection on the surface of the substrate, the third area has the third projection on the surface of the substrate, the area of the second projection is larger than that of the first projection, the area of the second projection is larger than that of the third projection, the first projection is in the range of the second projection, the third projection is in the range of the second projection, and the first connecting layer is formed in the first groove, so that the bottom area of the first connecting layer is increased. On one hand, when a second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, and the condition that the second connecting layer is in contact with the first connecting layer poorly is reduced, so that the first connecting layer can be electrically connected with a subsequently formed conductive structure through the second connecting layer; on the other hand, the contact resistance of the first connection layer and the second connection layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
Further, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5, so that the area of the bottom of the first groove is increased, and the second connection layer is easily contacted with the bottom of the first connection layer.
Further, the bottom of the first connection layer has a first size, and the top of the second connection layer in contact with the first connection layer has a second size, the first size being larger than the second size, so that the second connection layer is easily in contact with the bottom of the first connection layer when the second connection layer is formed.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
fig. 2 to 7 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the matching performance of the existing embedded power line and the back power transmission network is still to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate 100, said substrate 100 comprising opposing first and second sides, said substrate comprising an active area (not labeled) and a connection area (not labeled); a fin structure 101 located on an active area of a first side of the substrate 100; a dielectric layer 102 on the first side of the substrate 100, the dielectric layer 102 covering the top surface and the sidewall surface of the fin structure 101; a first connection layer 103 located in a first side connection region of the substrate 100, said first connection layer 103 further being located in said dielectric layer 102; a second tie layer 104 located within the second side tie region of substrate 100, said second tie layer 104 contacting the bottom of said first tie layer 103; a conductive layer 105 on the second side of the substrate 100, said conductive layer 105 being electrically connected to said second connection layer 104.
In the semiconductor structure, as the size of the semiconductor structure is smaller and smaller, the size of the first connection layer 103 is also smaller and smaller, so that when the second connection layer 104 in contact with the first connection layer 103 is formed in the second surface connection region of the substrate 100, the second connection layer 104 is affected by the precision of the etching process and the precision of the etching process, and the formed second connection layer 104 has a risk of poor contact with the bottom of the first connection layer 103, so that the first connection layer 103 cannot be electrically connected with the conductive layer 105 through the second connection layer 104, and the performance of the semiconductor structure is affected.
To solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, by forming a first recess in the connection region of the first side of the substrate, the first recess is formed, in the direction from the first side to the second side of the substrate, the first recess comprises a first region, a second region and a third region, the first region having a first projection onto the substrate surface, the second region having a second projection at the substrate surface, the third region having a third projection at the substrate surface, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, and the first projection is in the range of the second projection, the third projection is in the range of the second projection, and then a first connecting layer is formed in the first groove, so that the bottom area of the first connecting layer is increased. On one hand, when a second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, and the condition that the second connecting layer is in contact with the first connecting layer poorly is reduced, so that the first connecting layer can be electrically connected with a subsequently formed conductive structure through the second connecting layer; on the other hand, the contact resistance of the first connection layer and the second connection layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 includes a first side and a second side opposite to each other, and the substrate 200 includes an active area I and a connection area II.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or germanium on insulator.
The substrate 200 also has a plurality of fin structures 201 on the first surface active region I, and the plurality of fin structures 201 are arranged in parallel along a first direction X parallel to the surface of the substrate 200.
The connection region II is located between adjacent fin structures 201.
In this embodiment, the fin structure 201 is made of monocrystalline silicon; in other embodiments, the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or germanium on insulator.
With continued reference to fig. 2, a protection layer 202 is formed on the first surface of the substrate, wherein the protection layer 202 covers the top surface and the sidewall surface of the fin structure 201.
The material of the protection layer 202 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In the present embodiment, the material of the protection layer 202 includes silicon oxide.
Next, a first recess 205 is formed in the attachment area II of the substrate 200, said first recess 205 extending from the first side towards the second side of the substrate 200. Please refer to fig. 3 to 4 for a specific process of forming the first recess 205.
Referring to fig. 3, a first mask layer 203 is formed on the protection layer 202, wherein the first mask layer 203 exposes the surface of the protection layer 202 on the connection region II; and etching the protective layer 202 by taking the first mask layer 203 as a mask until the surface of the substrate 200 is exposed, and forming a second groove 204 in the protective layer 202.
The process of etching the protection layer 202 includes one or a combination of a dry etching process and a wet etching process.
In this embodiment, the process of etching the protection layer 202 includes a dry etching process.
Referring to fig. 4, the substrate 200 exposed by the second recess 204 is etched, and the first recess 205 is formed in the connection region II.
The method for etching the substrate 200 exposed by the second groove 204 comprises the following steps: etching the substrate 200 by using a first etching process to form an initial first groove (not shown), wherein a side wall of the initial first groove is perpendicular to a bottom surface of the initial first groove; and etching the substrate 200 exposed by the initial first groove by adopting a second etching process to form a first groove 205, wherein the side wall of the first groove 205 is recessed into the effective area I.
The first etching process can obtain an initial first groove with the side wall vertical to the bottom surface. In this embodiment, the first etching process includes an anisotropic dry etching process.
The second etching process can obtain the first groove 205 with the side wall recessed into the effective region I. The second etching process comprises one or more combination of a wet etching process and an isotropic dry etching process.
In this embodiment, the second etching process includes an isotropic dry etching process, and the parameters of the isotropic dry etching process include: the etching gas is NF3、H2、N2And O2The mixed gas of (3); the air pressure is 5 mTorr-100 mTorr; the power is 100W-1000W; the gas flow is 0sccm to 500 sccm.
In a first direction X parallel to the surface of the substrate 200 and in a direction perpendicular to the extending direction of the fin structure 201, the cross-sectional shape of the first groove 205 is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5, so that the area of the bottom of the first groove 205 is increased, and a subsequently formed second connection layer is easily contacted with the bottom of the first connection layer.
In this embodiment, the size of the first groove 205 in the first direction X is 10nm to 100 nm; the first groove 205 has a dimension in a direction from the first surface to the second surface of the substrate of 10nm to 100 nm. The first groove 205 in the size range increases the area of the bottom of the first connection layer when the first connection layer is formed in the first groove 205, so that the second connection layer formed subsequently is easy to contact with the first connection layer, and the first connection layer has a good conductive effect.
In this embodiment, the first groove 205 is spherical in shape.
In a direction from the first face to the second face of the substrate 200, the first groove 205 includes a first region (not labeled), a second region (not labeled) and a third region (not labeled), the first region has a first projection on the surface of the substrate 200, the second region 200 has a second projection on the surface of the substrate, the third region 200 has a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, the first projection is within the range of the second projection, and the third projection is within the range of the second projection, so that when a first connection layer is formed in the first groove 205 later, the area of the bottom of the first connection layer is increased, and the second connection layer formed later is easy to contact with the first connection layer.
Referring to fig. 5, a first connection layer 206 is formed in the first recess 205.
The method for forming the first connection layer 206 includes: forming a connecting material layer (not shown) in the second groove 204, in the first groove 205 and on the protective layer 202; planarizing the connection material layer until the surface of the protection layer 202 is exposed, and forming an initial connection layer (not shown); the initial connection layer is etched back to form the first connection layer 206.
The material of the first connection layer 206 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride. The forming process of the connecting material layer comprises a physical vapor deposition process or an electroplating process.
In the present embodiment, the material of the first connection layer 206 includes copper; the forming process of the connecting material layer comprises a physical vapor deposition process.
In this embodiment, a portion of the first connection layer 206 is also located in the second groove 204.
In a direction from the first side to the second side of the substrate 200, the first groove 205 includes a first region, a second region and a third region, the first region has a first projection on the surface of the substrate 200, the second region 200 has a second projection on the surface of the substrate, the third region 200 has a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, and the first projection is in the range of the second projection, the third projection is in the range of the second projection, so that the area of the bottom of the first connection layer 206 located in the first groove 205 is increased. The area of the bottom of the first connection layer 206 is increased, so that when a second connection layer is formed in the substrate connection region II, the bottom of the second connection layer is easy to contact with the bottom of the first connection layer 206, and the poor contact between the second connection layer and the first connection layer 206 is reduced, so that the first connection layer 206 can be electrically connected with a subsequently formed conductive structure through the second connection layer; on the other hand, the contact resistance of the first connection layer 206 and the second connection layer can be reduced.
With continued reference to fig. 5, after the first connection layer 206 is formed, an isolation layer 207 is formed in the second recess 204.
The material of the isolation layer 207 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the isolation layer 207 includes silicon oxide.
Referring to fig. 6, after forming the first connection layer 206, a second connection layer 208 is formed in the substrate connection region II, the second connection layer 208 extends from the second side of the substrate 200 to the first side of the substrate 200, and the second connection layer 208 is in contact with the first connection layer 206.
The bottom of the first connection layer 206 has a first size and the top of the second connection layer 208 in contact with the first connection layer 206 has a second size, the first size being larger than the second size, so that the second connection layer 208 is easily in contact with the bottom of the first connection layer 206 when the second connection layer 208 is formed.
In this embodiment, the range of the first size being greater than the second size is 10% to 50%.
The forming method of the second connection layer 208 includes: forming a second mask layer (not shown) on the second surface of the substrate, wherein the second mask layer exposes the surface of the connecting region II; etching the substrate 200 with the second mask layer as a mask until the surface of the first connection layer 206 is exposed, and forming a third groove (not shown) in the connection region II; a second connection layer 208 is formed within the third recess.
The material of the second connection layer 208 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Since the range of the first dimension larger than the second dimension is 10% to 50%, when the third groove is formed, the area of the bottom of the third groove exposed to the bottom of the first connection layer 206 is large, so that even if the position of the third groove is deviated, the second connection layer 208 formed in the third groove can be in contact with the first connection layer 206, and meanwhile, the contact area of the second connection layer 208 and the first connection layer 206 is large, so that the contact resistance of the first connection layer 206 and the second connection layer 208 can be reduced, and the process window for forming the third groove can be increased.
Referring to fig. 7, a plurality of conductive structures 209 are formed on the second surface of the substrate 200, and the conductive structures 209 are electrically connected to the second connection layer 208.
The conductive structure 209 is used for electrical connection of the semiconductor structure to external structures.
The material of the conductive structure 209 comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
The second connection layer 208 preferably contacts the first connection layer 206, so that the first connection layer 206 can be electrically connected to the conductive structure 209 via the second connection layer 208, thereby electrically connecting the semiconductor structure to an external structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 7, which includes: a substrate 200, said substrate 200 comprising opposing first and second faces, said substrate 200 comprising an active area I and a connection area II; a first groove 205 located in a connecting region II of the substrate 200, the first groove 205 extending from the first face to the second face of the substrate 200, the first groove comprising a first region, a second region and a third region, the first region having a first projection on the surface of the substrate 200, the second region having a second projection on the surface of the substrate 200, the third region having a third projection on the surface of the substrate 200, the area of the second projection being larger than the area of the first projection, the area of the second projection being larger than the area of the third projection, and the first projection being within the range of the second projection, the third projection being within the range of the second projection; a first connection layer 206 located in the first recess 205 and electrically connectable.
In the present embodiment, in the first direction X parallel to the surface of the substrate 200, the shape of the first groove 205 is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5.
In this embodiment, the substrate 200 further has a plurality of fin structures 201 on the first surface active region I, and the fin structures 201 are arranged in parallel along a first direction X parallel to the substrate surface; the connection region II is located between adjacent fin structures 201.
In this embodiment, the method further includes: a protective layer 202 on the first side of the substrate 200, wherein the protective layer 202 covers the top surface and the sidewall surface of the fin structure 201; a second groove 204 located in the protection layer 202, wherein the second groove 204 is communicated with the first groove 205, and a part of the first connection layer 206 is located in the second groove 204; an isolation layer 207 located in the second recess 204 on the first connection layer 206.
In this embodiment, the method further includes: a second tie layer 208 located within the tie region II of the substrate 200, said second tie layer 208 extending from the second side of the substrate 200 towards the first side of the substrate 200, and said second tie layer 208 being in contact with said first tie layer 206.
In this embodiment, the bottom of the first connection layer 206 has a first size, and the top of the second connection layer 208 in contact with the first connection layer 206 has a second size, and the first size is larger than the second size.
In this embodiment, the range of the first size being greater than the second size is 10% to 50%.
In this embodiment, the material of the first connection layer 206 includes a metal, and the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride; the material of the second connection layer 208 includes a metal including: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
In this embodiment, the method further includes: a number of conductive structures 209 located on the second side of the substrate 200, said conductive structures 209 being electrically connected to said second connection layer 208.
In the semiconductor structure, the substrate 200 has a first groove 205 in a first surface connection region II, and in a direction from a first surface to a second surface of the substrate, the first groove includes a first region, a second region and a third region, the first region has a first projection on a surface of the substrate, the second region has a second projection on the surface of the substrate, the third region has a third projection on the surface of the substrate, an area of the second projection is larger than an area of the first projection, an area of the second projection is larger than an area of the third projection, the first projection is in a range of the second projection, the third projection is in a range of the second projection, and the first connection layer 206 is located in the first groove 205, so that a bottom area of the first connection layer 206 is increased. On one hand, when the second connecting layer 208 is formed in the connecting region II of the substrate 200, the bottom of the second connecting layer 208 is easy to contact with the bottom of the first connecting layer 206, so that the condition that the second connecting layer 208 is in poor contact with the first connecting layer 206 is reduced, and the first connecting layer 206 can be electrically connected with the conductive structure 209 through the second connecting layer 208; on the other hand, the contact resistance of the first connection layer 206 and the second connection layer 208 can be reduced. In conclusion, the performance of the semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (22)
1. A semiconductor structure, comprising:
a substrate comprising opposing first and second faces, the substrate comprising an active area and a connecting area;
a first groove located in a substrate connection region, the first groove extending from a first surface to a second surface of a substrate, the first groove including a first region, a second region and a third region, the first region having a first projection on a surface of the substrate, the second region having a second projection on the surface of the substrate, the third region having a third projection on the surface of the substrate, an area of the second projection being larger than an area of the first projection, an area of the second projection being larger than an area of the third projection, the first projection being within a range of the second projection, and the third projection being within a range of the second projection;
and the first connecting layer is positioned in the first groove and can be electrically connected.
2. The semiconductor structure of claim 1, wherein a cross-sectional shape of the first groove in a first direction parallel to a surface of the substrate is a sphere or a polygon having a number of sides greater than or equal to 5.
3. The semiconductor structure of claim 1, further comprising a plurality of fin structures on the active area of the first surface of the substrate, the plurality of fin structures being arranged in parallel along a first direction parallel to the surface of the substrate; the connection region is located between adjacent fin structures.
4. The semiconductor structure of claim 3, further comprising: the protective layer is positioned on the first surface of the substrate and covers the top surface and the side wall surface of the fin structure; the second groove is positioned in the protective layer and communicated with the first groove, and part of the first connecting layer is positioned in the second groove; and the isolation layer is positioned in the second groove on the first connecting layer.
5. The semiconductor structure of claim 1, further comprising: a second tie layer within the substrate tie region, the second tie layer extending from the substrate second face toward the substrate first face, the second tie layer contacting the first tie layer.
6. The semiconductor structure of claim 5, wherein a bottom portion of the first connection layer has a first dimension and a top portion of the second connection layer in contact with the first connection layer has a second dimension, the first dimension being greater than the second dimension.
7. The semiconductor structure of claim 6, wherein the first dimension is greater than the second dimension in a range from 10% to 50%.
8. The semiconductor structure of claim 1, further comprising: and the conductive structures are positioned on the second surface of the substrate and are electrically connected with the second connecting layer.
9. A method of forming a semiconductor structure, comprising:
providing a substrate comprising opposing first and second faces, the substrate comprising an active area and a connecting area;
forming a first groove in a substrate connecting area, wherein the first groove extends from a first surface to a second surface of a substrate, and in the direction from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the surface of the substrate, the second area has a second projection on the surface of the substrate, the third area has a third projection on the surface of the substrate, the area of the second projection is larger than that of the first projection, the area of the second projection is larger than that of the third projection, the first projection is in the range of the second projection, and the third projection is in the range of the second projection;
a first connection layer is formed in the first recess to be electrically connected.
10. The method of forming a semiconductor structure according to claim 9, wherein a cross-sectional shape of the first groove in a first direction parallel to a surface of the substrate is a sphere or a polygon having a number of sides greater than or equal to 5.
11. The method of claim 9, wherein the active area of the first surface of the substrate further comprises a plurality of fin structures, wherein the plurality of fin structures are arranged in parallel along a first direction parallel to a surface of the substrate; the connection region is located between adjacent fin structures.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the first recess comprises: forming a protective layer on the first surface of the substrate, wherein the protective layer covers the top surface and the side wall surface of the fin structure; forming a first mask layer on the protective layer, wherein the first mask layer exposes the surface of the protective layer on the connecting area; etching the protective layer by taking the first mask layer as a mask until the surface of the substrate is exposed, and forming a second groove in the protective layer; and etching the substrate exposed by the second groove to form the first groove.
13. The method of forming a semiconductor structure of claim 12, wherein etching the substrate exposed by the second recess comprises: etching the substrate by adopting a first etching process to form an initial first groove, wherein the side wall of the initial first groove is vertical to the bottom surface of the initial first groove; and etching the substrate exposed by the initial first groove by adopting a second etching process to form a first groove, wherein the side wall of the first groove is sunken towards the inside of the effective area.
14. The method of forming a semiconductor structure of claim 13, wherein the first etching process comprises an anisotropic dry etching process.
15. The method of forming a semiconductor structure of claim 13, wherein the second etching process comprises a combination of one or more of a wet etching process and an isotropic dry etching process.
16. The method of forming a semiconductor structure of claim 12, wherein a portion of the first connection layer is also located within the second recess.
17. The method of forming a semiconductor structure of claim 12, further comprising, after forming the first tie layer: and forming an isolation layer in the second groove.
18. The method of forming a semiconductor structure of claim 9, further comprising, after forming the first tie layer: a second connection layer is formed within the substrate connection region, the second connection layer extending from the substrate second face toward the substrate first face, and the second connection layer being in contact with the first connection layer.
19. The method of forming a semiconductor structure of claim 18, wherein a bottom portion of the first connection layer has a first dimension and a top portion of the second connection layer in contact with the first connection layer has a second dimension, the first dimension being greater than the second dimension.
20. The method of forming a semiconductor structure of claim 19, wherein the first dimension is greater than the second dimension in a range of 10% to 50%.
21. The method of forming a semiconductor structure of claim 9, wherein the method of forming the second connection layer comprises: forming a second mask layer on the second surface of the substrate, wherein the second mask layer exposes the surface of the connecting region; etching the substrate by taking the second mask layer as a mask until the surface of the first connecting layer is exposed, and forming a third groove in the substrate; and forming a second connecting layer in the third groove.
22. The method of forming a semiconductor structure of claim 9, further comprising, after forming the second connection layer: and forming a plurality of conductive structures on the second surface of the substrate, wherein the conductive structures are electrically connected with the second connecting layer.
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| JPH07193126A (en) * | 1993-12-27 | 1995-07-28 | Nec Corp | Semiconductor device and its manufacture |
| US20090305502A1 (en) * | 2008-06-10 | 2009-12-10 | Ho-Jin Lee | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby |
| CN102187452A (en) * | 2008-10-16 | 2011-09-14 | 美光科技公司 | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods |
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