CN113688092B - Low-power-consumption safety protection control device based on singlechip - Google Patents
Low-power-consumption safety protection control device based on singlechip Download PDFInfo
- Publication number
- CN113688092B CN113688092B CN202110825157.8A CN202110825157A CN113688092B CN 113688092 B CN113688092 B CN 113688092B CN 202110825157 A CN202110825157 A CN 202110825157A CN 113688092 B CN113688092 B CN 113688092B
- Authority
- CN
- China
- Prior art keywords
- resistor
- singlechip
- capacitor
- power
- trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000007654 immersion Methods 0.000 claims abstract description 23
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052744 lithium Inorganic materials 0.000 claims abstract description 18
- 238000004891 communication Methods 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 77
- 239000000523 sample Substances 0.000 claims description 26
- 238000012545 processing Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 4
- 230000009471 action Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000009434 installation Methods 0.000 abstract 1
- 230000000875 corresponding effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012806 monitoring device Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The application provides a low-power-consumption safety protection control device and algorithm based on a singlechip, which mainly comprise the singlechip, a main controller and a safety protection trigger control circuit; the security trigger control circuit is connected with the singlechip, and the singlechip is connected with the main controller for normal data communication in an electrified mode; the security trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time-to-trigger circuit, a working mode switching circuit and a power supply switching circuit. The safety protection control device provided by the application has the advantages that the service life of the lithium battery is long under the low power consumption mode, the installation control device can flexibly deform and expand multiple paths according to specific use occasions, the cost is low, the circuit is simple, and the triggering is efficient.
Description
Technical Field
The application relates to the field of single-chip microcomputer, in particular to a low-power-consumption safety protection control device and algorithm based on the single-chip microcomputer.
Background
In the application occasions needing safety protection control, the key data and key information in the emergency situation are often required to be directly erased or physically destroyed so as to avoid important information leakage. The security control triggering means comprise various common modes such as water immersion, card pulling, switching and timing, the response and processing of the equipment only need to consider the response speed in a charged normal working mode of the equipment, but the security control after the system is powered down becomes important, the equipment is required to be powered down by a lithium battery, the security function module is independently powered up to monitor each security input state and respond in time under the condition that the equipment is required to be powered down by the power supply, the processor can be awakened in time to carry out specific security control steps after the triggering of the signals under the condition that the standby state is required, and meanwhile, the power consumption of the whole security monitoring device under the condition that the standby state is required is extremely low so as to meet the service life requirement of the lithium battery.
The current low-power consumption control basically uses a single chip microcomputer (Microcontrollers) as a core control unit, and the single chip microcomputer (Microcontrollers) is a small and perfect microcomputer system formed by integrating functions (possibly including a real driving circuit, a pulse width modulation circuit, an analog multiplexer, an A/D converter and the like) such as a central processing unit CPU with data processing capability, various I/O ports, an interrupt system, a timer/counter and the like on a silicon chip by adopting a very large scale integrated circuit technology, and is widely applied to the field of industrial control. Meanwhile, the singlechip has the advantages of simple circuit, low price and the like.
In chinese patent document with publication number CN103425235a, a low-power consumption standby circuit of a single chip microcomputer and a control method thereof are disclosed, wherein the low-power consumption standby circuit comprises an MCU, a power supply VCC, an NPN triode Q1 or a PNP triode Q1, a resistor R2 and a switch SW1, an I/O port of the MCU can be configured to output a high level and a low level, and the two states can control the two triodes to be turned on or off, thereby controlling the power on or power off of the MCU.
In the Chinese patent literature with the publication number of CN208673086U, a low-cost low-power consumption singlechip timing wake-up circuit is disclosed, and belongs to the field of singlechip management circuits, and the singlechip timing wake-up circuit comprises a singlechip, a resistor R1, a resistor R2 and a capacitor C1, wherein the singlechip is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the capacitor C1 and the resistor R2, and the other ends of the capacitor C1 and the resistor R2 are connected with a ground wire.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide a low-power-consumption safety protection control device and algorithm based on a singlechip.
The application provides a low-power-consumption safety protection control device based on a singlechip, which comprises: the system comprises a singlechip, a main controller and a security trigger control circuit; the security trigger control circuit is connected with the singlechip, and the singlechip is connected with the main controller for normal data communication in an electrified mode;
the security trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time-to-trigger circuit, a working mode switching circuit and a power supply switching circuit.
Preferably, the power supply switching circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a lithium battery;
one end of a first resistor R1 is a NORMAL power supply VCC_3V3 end, the other end of the first resistor R1 is connected with the positive electrode of a first diode D1, the negative electrode of the first diode D1 is connected with one end of a third resistor R3, the positive electrode of a lithium battery is a VBAT end, the positive electrode of the lithium battery is connected with one end of a second resistor R2, one end of the first capacitor C1 is connected with one end of the second resistor R2, the negative electrode of the lithium battery is connected with the other end of the first capacitor C1 and grounded, the other end of the second resistor R2 is connected with the positive electrode of a second diode D2, the negative electrode of the second diode D2 is connected with one end of a third resistor R3, one end of the third resistor R3 is connected with one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 forms a VMCU_3V3 end, the VMCU_3V3 end is respectively connected with a VBAT end of a singlechip, a VDD/DC+end and a third capacitor C3, and a power consumption pin of the singlechip is a power supply pin of the singlechip is in a NORMAL power supply mode under the voltage mode, and the other end of the singlechip is a power supply mode of the singlechip is a low power supply pin of the power supply mode.
Preferably, the working mode judging circuit includes a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, a collector of the first triode Q1 is respectively connected with one end of the sixth resistor R6 and one end of the fourth resistor R4, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected with a GPIO port of P1.5 of the singlechip, the other end of the sixth resistor R6 forms a vmcu_3v3 end, a base of the first triode Q1 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a vcc_3v3 end, and an emitter of the first triode Q1 is grounded.
Preferably, in a charged state when the power supply is normally powered, VCC_3V3 is 3.3V voltage, and the PowerCheck pin is low level; in the battery-only power down state, vcc_3v3 is 0V and the powercheck pin is high.
Preferably, the water immersion trigger circuit includes a first probe, a seventh resistor R7 and a fourth capacitor C4, one path of the first probe is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected to one end of the fourth capacitor C4 and a P1.1 port of the singlechip, and the other end of the fourth capacitor C4 is grounded.
Preferably, the card pulling trigger circuit comprises a second probe, an eighth resistor R8, a ninth resistor R9 and a fifth capacitor C5, one path of the second probe is connected with one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is respectively connected with a P1.2 port of the singlechip, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a vmcu_3v3 end, and the other end of the fifth capacitor C5 is grounded.
Preferably, the switch triggering circuit comprises a touch switch and a sixth capacitor C6, one end of the touch switch is grounded, the other end of the touch switch is respectively connected with the P1.3 end of the singlechip and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
Preferably, the timing trigger circuit includes a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, where a signal of the clock chip is DS3232, a VCC pin of the clock chip is connected to one end of the tenth resistor R10, another end of the tenth resistor R10 is grounded, an int# pin of the clock chip is connected to one end of the P1.4 port and one end of the seventh capacitor C7 of the singlechip respectively, another end of the seventh capacitor C7 is grounded, an SCL pin of the clock chip is connected to one end of the twelfth resistor R12 and one end of the P0.7 port of the singlechip respectively, an SDA pin of the clock chip is connected to one end of the eleventh resistor R11 and one end of the singlechip respectively, another end of the eleventh resistor is connected to another end of the twelfth resistor R12 to form a vmcu_3v3 end, a VBAT end of the clock chip is connected to one end of the eighth capacitor C8, a VBAT end of the clock chip forms a vmcu_3v3 end, and a GND end of the clock chip is connected to the eighth capacitor C8.
Preferably, the main controller comprises an ARM chip and a DSP chip, and the main controller is connected with the singlechip through a serial port or an I2C interface.
The application provides a low-power-consumption security control algorithm based on a singlechip, which comprises the following steps of:
step S1: power-on initialization: initializing a GPIO port of the singlechip, setting a card pulling trigger judging port as analog input, and judging the occurrence of the event through a comparator; setting the water immersion, switching and timing triggering judging ports as digital inputs, judging the occurrence of the events through periodically scanning the port states of the timers, and initializing a comparator CP0 and a Timer 0;
step S2: the main loop is entered, and the main loop is branched into two sub-loops according to the P1.5 port PowerCheck level state, wherein one sub-loop is a sleep mode sub-loop under the power supply of a battery, and the other sub-loop is a normal mode sub-loop under the power supply of a normal.
Step S3: if P1.5 is high level, enter sleep mode subcycle, set up the single-chip microcomputer to enter sleep mode and set up and wake up the source as comparator 0 and port match, if not triggering, the single-chip microcomputer is in mode of low power consumption, if have water logging, card pulling, switch, timing and any triggering event that the working mode changes take place, the single-chip microcomputer is awoken, read and awak the source status register at this moment, judge awak source kind first, judge what awak source is specific, go to carry out the corresponding response action again.
Step S4: if the detection judgment P1.5 is low level, a normal mode subcycle is entered, the singlechip normally and sequentially executes all task processing flows required by the system, and the trigger judgment of water immersion, card pulling, switching, timing and working modes is responded in an interrupt mode, wherein the card pulling is realized through the interrupt of the comparator 0, and the trigger judgment of water immersion, switching, timing and working modes is realized through the interrupt of the timer and the timing scanning of the port state.
Step S5: when the P1.5 level state is changed, the system is switched into a corresponding working mode when the next cycle is judged, and the main cycle is continuously judged again by two branch subcycles after the trigger event is responded, so that the system is operated as required.
Compared with the prior art, the application has the following beneficial effects:
1. the application develops the low-power-consumption security control device which is finished by using the C8051F912 singlechip, the security trigger control in the low-power-consumption sleep working mode is realized by configuring a corresponding wake-up source, the system current in the actually measured sleep mode is not more than 10 mu A, when a CR2450 lithium battery is selected, the battery electric quantity is 580mAh, and the service life of the lithium battery of the device in the low-power-consumption sleep mode is easily satisfied and is more than 5 years;
2. the application relies on a C8051F912 singlechip to develop two applicable low-power-consumption trigger configuration modes, one is normally high level, the trigger state is transient low level, and the configuration is suitable for digital input; the other is normally low, the trigger state is continuously high, and the device is suitable for being configured as analog input. Flexible deformation and multipath expansion can be performed according to specific use occasions;
3. the application provides a low-cost security control scheme, which has the advantages of simple circuit and high triggering efficiency, responds to various triggering events in a wake-up triggering mode in a power-down sleep mode, and simultaneously, the singlechip is connected with the storage circuit in an extensible manner, and can erase key data or directly physically destroy the key data when the triggering event occurs; meanwhile, the singlechip can be also interconnected with other main controllers (such as ARM, DSP or other SOC chips) through a serial port or an I2C common interface, and the response time in a charged normal mode can be also transmitted to the main controllers, so that other important tasks in the system can be conveniently expanded and completed.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a low-power-consumption security control device based on a singlechip;
FIG. 2 is a diagram of a power supply switching circuit in the present application;
FIG. 3 is a circuit diagram of the operation mode determination circuit of the present application;
FIG. 4 is a schematic diagram of a water immersion trigger circuit according to the present application;
FIG. 5 is a diagram of a card pulling trigger circuit according to the present application;
FIG. 6 is a diagram of a switch trigger circuit according to the present application;
FIG. 7 is a timing trigger circuit diagram of the present application;
FIG. 8 is a diagram of a single-chip microcomputer low-power-consumption security control algorithm.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
The application comprises two parts, wherein one part is a hardware design block diagram of the low-power consumption singlechip security control device and a hardware circuit which is specifically realized by each trigger circuit, so that the switching of a power supply under normal power supply and battery power supply, the judgment of a working mode and the construction of the trigger circuit under each trigger mode are realized; the other part is a singlechip low-power-consumption security control algorithm, so that trigger control in a normal mode and wake-up trigger control in a sleep low-power-consumption mode are realized.
As shown in fig. 1, in the hardware system block diagram of the application, a singlechip is selected from C8051F912 of SILICON LABORATORIES, and is directly connected with a security trigger control circuit, wherein the security trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time to trigger circuit, a working mode switching circuit and a power supply switching circuit; meanwhile, normal data communication under the electrified mode is carried out through the serial port (or other common communication interfaces such as I2C) and the main controller, so that the expansion of the system function is realized, and the main controller comprises an ARM chip, a DSP chip and other SOC controller chips.
As shown in fig. 2, the power supply switching circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a lithium battery, where the types of the first diode D1 and the second diode D2 are BAT54C.
One end of the first resistor R1 is a normal power supply VCC_3V3 end, the other end of the first resistor R1 is connected with the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected with one end of the third resistor R3, the positive electrode of the lithium battery is a VBAT end, the positive electrode of the lithium battery is connected with one end of the second resistor R2, one end of the first capacitor C1 is connected with one end of the second resistor R2, the negative electrode of the lithium battery is connected with the other end of the first capacitor C1 and grounded, the other end of the second resistor R2 is connected with the positive electrode of the second diode D2, one end of the third resistor R3 is connected with one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 forms a VMCU_3V3 end, and the VMCU_3V3 end is respectively connected with the VDD/DC+ end of the singlechip, the VBAT end and one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded. The VDD/DC+ end of the singlechip is a power supply pin in NORMAL operation NORMAL mode of the singlechip, and the VBAT end is a power supply pin in low-power consumption operation SLEEP mode of the singlechip.
VDD/dc+ and VBAT corresponding pins of the singlechip C8051F912 are both connected to vmcu_3v3, and vmcu_3v3 is the back end output of the normal power supply vcc_3v3 and the battery VBAT through the BAT54C. VBAT is the voltage across the lithium battery, normally 3.3V and will be smaller and smaller, vcc_3v3 is the normal charging voltage, normally up to 3.35V, and is essentially unchanged within the corresponding ripple range. When VCC_3V3 is present, the VMCU_3V3 output is based on VCC_3V3, and when VCC_3V3 is absent, the VMCU_3V3 output is based on VBAT. The power supply switching circuit realizes switching between normal power supply and battery power supply, and ensures that VMCU_3V3 power supply voltage always exists (unless the battery is exhausted at the same time when the power supply is powered down).
As shown in fig. 3, the operation mode determination circuit: the working mode judging circuit comprises a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, wherein a collector electrode of the first triode Q1 is respectively connected with one end of the sixth resistor R6 and one end of the fourth resistor R4, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected with a GPIO port of P1.5 of the singlechip, the other end of the sixth resistor R6 forms a VMCU_3V3 end, a base electrode of the first triode Q1 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a VCC_3V3 end, and an emitter electrode of the first triode Q1 is grounded.
A judging circuit is built in the working mode judging circuit, wherein the model number of the first triode Q1 is 2N3904, VCC_3V3 is 3.3V voltage in a charged state when the power supply is powered normally, and the PowerCheck pin is low level; in the power-down state with only battery power, VCC_3V3 is 0V, and the PowerCheck pin is high level; the PowerCheck judging signal is connected to the GPIO port of P1.5 of the singlechip C8051F 912. The working mode judging circuit is connected with the P1.5 GPIO port of the singlechip through a Powercheck signal to realize the change of Powercheck level state after the working mode is converted, so that the singlechip acquires the working mode which should be currently in by reading the state of the P1.5 port.
As shown in fig. 4, the water immersion trigger circuit includes a first probe, a seventh resistor R7 and a fourth capacitor C4, one path of the first probe is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected to one end of the fourth capacitor C4 and a P1.1 port of the singlechip, and the other end of the fourth capacitor C4 is grounded.
The water immersion trigger circuit is triggered by short circuit generated by inserting two probe signals into water, wherein 1 path of probe signals are GND, and the other path of probe signals are connected to a GPIO port of P1.1 of a singlechip C8051F912, and meanwhile, the ground is connected with a 0.1uF capacitor for anti-shake. And the water immersion trigger circuit is used for realizing water immersion trigger after the water immersion probe is in short circuit in water, the WaterDestroy+ signal level is changed, and the singlechip acquires the trigger event by reading the state of the P1.1 port, so that corresponding action is performed.
As shown in fig. 5, the card pulling trigger circuit includes a second probe, an eighth resistor R8, a ninth resistor R9 and a fifth capacitor C5, one path of the second probe is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is respectively connected to a P1.2 port of the singlechip, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a vmcu_3v3 end, and the other end of the fifth capacitor C5 is grounded.
The card pulling trigger circuit is characterized in that two probe signals are normally short-circuited on the bottom plate, and the module is disconnected for triggering after being pulled out. The 1-path probe signal is a 51K resistor which is pulled down to GND, the other path of probe signal is a GPIO port which is pulled up to a 1M resistor and is connected to P1.2 of the singlechip C8051F912, and meanwhile, the anti-shake function is realized by connecting 0.1uF capacitor to the ground. And the card pulling trigger circuit is used for realizing separation of two probes of the normal short circuit of the board card when the module is pulled out of the chassis, triggering the card pulling, changing the card pulling trigger + analog voltage value of the P1.2 port, and acquiring the trigger event by the singlechip through the state change output by the configured comparator, thereby making corresponding action.
As shown in fig. 6, the switch trigger circuit includes a touch switch and a sixth capacitor C6, one end of the touch switch is grounded, and the other end of the touch switch is connected to the P1.3 end of the singlechip and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
The switch trigger circuit is triggered by pressing a light touch switch (short circuit of a trigger signal and GND), and returns to a normal state after being released, wherein the trigger signal is connected to a GPIO port of P1.3 of the singlechip C8051F912, and meanwhile, the ground connection 0.1uF capacitor is subjected to anti-shake. And the switch trigger circuit is used for realizing instantaneous short circuit at two ends of the key after the light touch switch is pressed, and separating the two ends of the key again after the light touch switch is loosened, so that the level of the switch trigger signal switch Destroy is changed in the process, and the singlechip acquires the trigger event by reading the state of the P1.3 port, thereby making corresponding action.
As shown in fig. 7, the timing trigger circuit includes a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, where the signal of the clock chip is DS3232, the VCC pin of the clock chip is connected to one end of the tenth resistor R10, the other end of the tenth resistor R10 is grounded, the int# pin of the clock chip is connected to the P1.4 port of the singlechip and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is grounded, the SCL pin of the clock chip is connected to one end of the twelfth resistor R12 and the P0.7 port of the singlechip, the SDA pin of the clock chip is connected to one end of the eleventh resistor R11 and the P0.6 port of the singlechip, the other end of the eleventh resistor is connected to the other end of the twelfth resistor R12 and forms a vmcu_3v3 end, the VBAT end of the clock chip is connected to one end of the eighth capacitor C8, the VBAT end of the clock chip forms a vm3V 3 end, and the GND end of the clock chip is connected to the other end of the eighth capacitor C8 in parallel. The 32KHZ pin of the clock chip is a 32.768KHZ clock output port, and the clock chip is not used, suspended and not externally connected; the RST# pin of the clock chip is a low-level effective reset pin of drain on-drain input/output, and the application only uses the pull-up resistor function of 50KΩ in the chip connected to the VCC pin, and is powered on, self-reset and suspended and not externally connected.
The timing trigger circuit adopts a DS3232 clock chip as an RTC clock function, and can set time and timing alarm time, and the time is timed to generate a trigger signal. The trigger signal is connected to the GPIO port of P1.4 of the singlechip C8051F912, and the ground connection 0.1uF capacitor is subjected to anti-shake. The timing trigger circuit adopts an RTC chip DS3232 to realize timing and alarm functions, is interconnected with the singlechip P1.4 through a chip interrupt output pin TimeDestroy, is triggered by timing time and events, and the singlechip acquires the trigger event by reading the state of the P1.4 port, thereby performing corresponding actions.
As shown in fig. 8, the low-power-consumption security control algorithm for the single-chip microcomputer is realized by programming the single-chip microcomputer in the language C:
step 1: power-on initialization: the port initialization is carried out on the GPIO port, so that the weak pull-up function of the singlechip port is enabled to avoid a great amount of current consumption caused by externally connecting the pull-up resistor. Setting a card pulling trigger judging port as analog input, and judging the occurrence of the event through a comparator; the water immersion, switching and timing trigger judging ports are set as digital inputs, and the occurrence of the events is judged through the periodic scanning of the port states of the Timer, so that the comparator CP0 and the Timer0 are also required to be initialized, and in addition, other functional modules of the singlechip required by the normal operation of the system are required to be initialized.
Step 2: entering a main cycle: in the while (1) main loop, according to the P1.5 port PowerCheck level state, the loop is branched into two sub-loops, one is a sleep mode sub-loop under battery power and the other is a normal mode sub-loop under normal power.
Step 3: if P1.5 is high at the beginning, a sleep sub-cycle is entered, the singlechip is set to enter a sleep mode and a wake-up source is set as a comparator 0 (CP 0 rising edge) and a PORT MATCH (PORT_MATCH). If the single chip microcomputer is not triggered all the time, the single chip microcomputer is in a low-power consumption mode all the time, the actually measured current consumption is only about 8 mu A, if any trigger event of water immersion, card pulling, switching, timing and working mode change occurs, the single chip microcomputer is awakened, at the moment, an awakening source state register is read, the type of the awakening source is judged firstly, and then the specific type of the awakening source is judged, so that corresponding response actions are executed.
Step 4: if the detection judgment P1.5 is low level, normal sub-cycle is entered, and the singlechip executes each task processing flow required by the system in normal sequence. In order to improve the response speed and the security processing efficiency, at the moment, the triggering judgment of water immersion, card pulling, switching, timing and working modes is responded in an interrupt mode, wherein the card pulling is realized through the interrupt of a comparator 0 (the rising edge of CP 0), and the other is realized through the interrupt of a timer to scan the port state at regular time.
Step 5: when the state of the P1.5 level is changed, the system is switched into a corresponding working mode when the next cycle is judged, namely, the main cycle is continuously judged again by two branch subcycles after the trigger event is responded, so that the system is operated as required.
Those skilled in the art will appreciate that the application provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the application can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.
Claims (6)
1. A low-power consumption safety protection control device based on singlechip, characterized by comprising: the system comprises a singlechip, a main controller and a security trigger control circuit; the security trigger control circuit is connected with the singlechip, and the singlechip is connected with the main controller for normal data communication in an electrified mode;
the security trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing trigger circuit, a working mode judging circuit and a power supply switching circuit;
the power supply switching circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a lithium battery;
one end of the first resistor R1 is a NORMAL power supply VCC_3V3 end, the other end of the first resistor R1 is connected with the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected with one end of the third resistor R3, the positive electrode of the lithium battery is a VBAT end, the positive electrode of the lithium battery is connected with one end of the second resistor R2, one end of the first capacitor C1 is connected with one end of the second resistor R2, the negative electrode of the lithium battery is connected with the other end of the first capacitor C1 and is grounded, the other end of the second resistor R2 is connected with the positive electrode of the second diode D2, the negative electrode of the second diode D2 is connected with one end of the third resistor R3, one end of the third resistor R3 is connected with one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 forms a VMCU_3V3 end, the VMCU_3V3 end is respectively connected with a VBAT end of a singlechip, a VDD/DC+end and a third capacitor C3 end of the singlechip, and a power consumption pin of the singlechip is in a NORMAL power supply mode under the singlechip, and the power supply mode is a low power supply pin of the singlechip;
the working mode judging circuit comprises a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, wherein a collector electrode of the first triode Q1 is respectively connected with one end of the sixth resistor R6 and one end of the fourth resistor R4, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected with a GPIO port of P1.5 of the singlechip, the other end of the sixth resistor R6 forms a VMCU_3V3 end, a base electrode of the first triode Q1 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a VCC_3V3 end, and an emitter electrode of the first triode Q1 is grounded;
in a charged state when the power supply is normally powered, VCC_3V3 is 3.3V voltage, and the Powercheck pin is low level; in the power-down state with only battery power, VCC_3V3 is 0V, and the PowerCheck pin is high level;
the low-power-consumption safety protection control device adopts a low-power-consumption safety protection control algorithm and comprises the following components:
step S1: power-on initialization: initializing a GPIO port of the singlechip, setting a card pulling trigger judging port as analog input, and judging the occurrence of an event through a comparator; setting the water immersion, switching and timing triggering judging ports as digital inputs, judging the occurrence of the events through periodically scanning the port states of the timers, and initializing a comparator CP0 and a Timer 0;
step S2: entering a main loop, and branching into two sub-loops according to the P1.5 port PowerCheck level state, wherein one is a sleep mode sub-loop under the power supply of a battery, and the other is a normal mode sub-loop under the normal power supply;
step S3: if P1.5 is high level, entering sleep mode subcycle, setting the singlechip to enter sleep mode and setting a wake-up source as a comparator 0 and port matching, if not triggering, the singlechip is in a low-power consumption mode, if any triggering event of water immersion, card pulling, switching, timing and working mode change occurs, the singlechip is waken, at the moment, reading a wake-up source state register, judging the type of the wake-up source, judging the specific type of the wake-up source, and executing corresponding response action;
step S4: if the detection judgment P1.5 is low level, a normal mode subcycle is entered, and the singlechip normally and sequentially executes all task processing flows required by the system, wherein the triggering judgment of water immersion, card pulling, switching, timing and working modes is responded in an interrupt mode, the card pulling is realized through the interrupt of a comparator 0, and the triggering judgment of water immersion, switching, timing and working modes is realized through the interrupt of a timer and the timing scanning of a port state;
step S5: when the P1.5 level state is changed, the system is switched into a corresponding working mode when the next cycle is judged, and the main cycle is continuously judged again by two branch subcycles after the trigger event is responded, so that the system is operated as required.
2. The single-chip microcomputer-based low-power-consumption safety protection control device according to claim 1, wherein: the water immersion trigger circuit comprises a first probe, a seventh resistor R7 and a fourth capacitor C4, one path of the first probe is connected with one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected with one end of the fourth capacitor C4 and a P1.1 port of the singlechip, and the other end of the fourth capacitor C4 is grounded.
3. The single-chip microcomputer-based low-power-consumption safety protection control device according to claim 1, wherein: the card pulling trigger circuit comprises a second probe, an eighth resistor R8, a ninth resistor R9 and a fifth capacitor C5, one path of the second probe is connected with one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is respectively connected with a P1.2 port of the singlechip, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a VMCU_3V3 end, and the other end of the fifth capacitor C5 is grounded.
4. The single-chip microcomputer-based low-power-consumption safety protection control device according to claim 1, wherein: the switch trigger circuit comprises a tact switch and a sixth capacitor C6, wherein one end of the tact switch is grounded, the other end of the tact switch is respectively connected with the P1.3 end of the singlechip and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
5. The single-chip microcomputer-based low-power-consumption safety protection control device according to claim 1, wherein: the timing trigger circuit comprises a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, wherein a signal of the clock chip is DS3232, a VCC pin of the clock chip is connected with one end of the tenth resistor R10, the other end of the tenth resistor R10 is grounded, an INT# pin of the clock chip is respectively connected with one end of a P1.4 port of a singlechip and one end of a seventh capacitor C7, the other end of the seventh capacitor C7 is grounded, an SCL pin of the clock chip is respectively connected with one end of the twelfth resistor R12 and one end of a P0.7 port of the singlechip, an SDA pin of the clock chip is respectively connected with one end of the eleventh resistor R11 and one end of the singlechip, the other end of the eleventh resistor is connected with the other end of the twelfth resistor R12 to form a CU_3V3 end, a VBAT end of the clock chip is connected with one end of the eighth capacitor C8, a VBAT end of the clock chip forms a VBAT 3V3 end of the clock chip, and the other end of the VMAT end of the clock chip is connected with the other end of the eighth capacitor C8 in parallel with the ground.
6. The single-chip microcomputer-based low-power-consumption safety protection control device according to claim 1, wherein: the main controller comprises an ARM chip and a DSP chip, and is connected with the singlechip through a serial port or an I2C interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825157.8A CN113688092B (en) | 2021-07-21 | 2021-07-21 | Low-power-consumption safety protection control device based on singlechip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825157.8A CN113688092B (en) | 2021-07-21 | 2021-07-21 | Low-power-consumption safety protection control device based on singlechip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113688092A CN113688092A (en) | 2021-11-23 |
| CN113688092B true CN113688092B (en) | 2023-12-08 |
Family
ID=78577628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110825157.8A Active CN113688092B (en) | 2021-07-21 | 2021-07-21 | Low-power-consumption safety protection control device based on singlechip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113688092B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204029141U (en) * | 2014-08-21 | 2014-12-17 | 台州通禾流体控制设备有限公司 | A kind of wireless water logging Inductance valve |
| CN204408000U (en) * | 2014-09-10 | 2015-06-17 | 东莞奥华电子有限公司 | Modularization security device power-supply system |
| JP2017045125A (en) * | 2015-08-24 | 2017-03-02 | 株式会社デンソー | Electronic control device |
| CN109448347A (en) * | 2018-10-16 | 2019-03-08 | 江苏万邦微电子有限公司 | A kind of security device based on low-power consumption |
| CN110588542A (en) * | 2019-09-09 | 2019-12-20 | 洛阳嘉盛电源科技有限公司 | Low-power-consumption self-awakening control circuit and control method for vehicle-mounted power supply |
| CN112994670A (en) * | 2021-05-08 | 2021-06-18 | 杭州米芯微电子有限公司 | Low-shutdown-power-consumption circuit of SOC (System on chip) and SOC |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399536A (en) * | 2007-09-30 | 2009-04-01 | 天津市研翔电子科技有限公司 | On/off control circuit for light touch switch in micro-controller system and control method |
| US8364326B2 (en) * | 2011-02-22 | 2013-01-29 | Asoka Usa Corporation | Set of sensor units for communication enabled for streaming media delivery with monitoring and control of power usage of connected appliances |
| BR112019004408A8 (en) * | 2016-09-05 | 2023-02-14 | Iot Nxt Bv | SOFTWARE DEFINED DEVICE INTERFACE SYSTEM AND METHOD |
| CN107818676A (en) * | 2017-12-13 | 2018-03-20 | 天津诚意创达科技有限公司 | A kind of low power consumption data acquiring and transmission system and implementation method based on clock chip |
| CN213754036U (en) * | 2020-11-05 | 2021-07-20 | 广东力科新能源有限公司 | Battery low-power consumption awakening circuit and battery low-power consumption control system |
-
2021
- 2021-07-21 CN CN202110825157.8A patent/CN113688092B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204029141U (en) * | 2014-08-21 | 2014-12-17 | 台州通禾流体控制设备有限公司 | A kind of wireless water logging Inductance valve |
| CN204408000U (en) * | 2014-09-10 | 2015-06-17 | 东莞奥华电子有限公司 | Modularization security device power-supply system |
| JP2017045125A (en) * | 2015-08-24 | 2017-03-02 | 株式会社デンソー | Electronic control device |
| CN109448347A (en) * | 2018-10-16 | 2019-03-08 | 江苏万邦微电子有限公司 | A kind of security device based on low-power consumption |
| CN110588542A (en) * | 2019-09-09 | 2019-12-20 | 洛阳嘉盛电源科技有限公司 | Low-power-consumption self-awakening control circuit and control method for vehicle-mounted power supply |
| CN112994670A (en) * | 2021-05-08 | 2021-06-18 | 杭州米芯微电子有限公司 | Low-shutdown-power-consumption circuit of SOC (System on chip) and SOC |
Non-Patent Citations (1)
| Title |
|---|
| "基于FPGA的动态部分可重构智能I/O接口设计与实现";徐健 等;《计算机工程》;第42卷(第6期);第14-20页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113688092A (en) | 2021-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101907918B (en) | Computer system for saving power consumption in standby/power-off state and related method thereof | |
| CN1971481A (en) | Drive circuit of power supply device of computer peripheral equipment | |
| TW200419331A (en) | Power shutdown method of wireless peripheral device | |
| CN103064488A (en) | Power source control circuit | |
| CN101907914A (en) | Computer power starting signal control signal | |
| CN101399536A (en) | On/off control circuit for light touch switch in micro-controller system and control method | |
| CN109613970B (en) | Low-power-consumption processing method based on FPGA and DSP framework | |
| CN110058541A (en) | Micro controller system with debugger in circuit | |
| CN109799898A (en) | A kind of power control of chip, chip and its power control method | |
| CA2029498A1 (en) | Method and apparatus for conserving power in a data processing system | |
| CN201780549U (en) | Multi-status switch control device and system | |
| CN205540692U (en) | Case of exempting from to start shooting updates intel management engine firmware circuit | |
| CN105403248B (en) | A kind of low-power consumption environmental monitoring system | |
| CN113688092B (en) | Low-power-consumption safety protection control device based on singlechip | |
| CN101498971B (en) | Remote control network physical isolation apparatus and its control method | |
| CN209297244U (en) | A kind of industrial personal computer timed power on/off circuit | |
| CN114578939A (en) | Single-line awakening and key detection circuit | |
| CN101208647A (en) | Computer volatile memory power backup system | |
| CN203151453U (en) | Power-down monitoring reset circuit for field programmable gate array device | |
| CN101329595A (en) | Emulator of low power consumption mode | |
| CN102915258A (en) | Control method of watchdog circuit | |
| CN113687711A (en) | Terminal wake-up circuit and wake-up method | |
| CN220962186U (en) | Power management control circuit | |
| CN100555788C (en) | The implement device of multi-voltage monitoring and protective circuit and method | |
| CN101995927A (en) | Resetting-operating method of 51 single chip microcomputer (SCM) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |