CN113688092A - Low-power-consumption safety protection control device and algorithm based on single chip microcomputer - Google Patents

Low-power-consumption safety protection control device and algorithm based on single chip microcomputer Download PDF

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CN113688092A
CN113688092A CN202110825157.8A CN202110825157A CN113688092A CN 113688092 A CN113688092 A CN 113688092A CN 202110825157 A CN202110825157 A CN 202110825157A CN 113688092 A CN113688092 A CN 113688092A
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resistor
single chip
chip microcomputer
capacitor
power
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CN113688092B (en
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李贺
方明
章阳
陈聪葱
王佳
姬叶华
邹志强
张佩
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CETC 32 Research Institute
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    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

本发明提供了一种基于单片机的低功耗安全防护控制装置及算法，主要包括单片机，主控制器以及安防触发控制电路；所述安防触发控制电路与单片机连接，所述单片机与主控制器连接进行带电模式下的正常数据通信；所述安防触发控制电路包括水浸触发电路、拔卡触发电路、开关触发电路、定时时间到触发电路、工作模式切换电路以及供电电源切换电路。本发明提供的安防控制装置在低功耗模式下锂电池使用寿命长，本安装控制装置可以根据具体的使用场合进行灵活变形和多路的扩展，且成本低，电路简单，触发高效。

Figure 202110825157

The invention provides a low power consumption safety protection control device and algorithm based on single chip microcomputer, which mainly includes a single chip microcomputer, a main controller and a security triggering control circuit; the security triggering control circuit is connected with the single chip microcomputer, and the single chip microcomputer is connected with the main controller Carry out normal data communication in the live mode; the security trigger control circuit includes a flood trigger circuit, a card pull trigger circuit, a switch trigger circuit, a timing time trigger circuit, a working mode switching circuit and a power supply switching circuit. The security control device provided by the invention has a long service life of the lithium battery in the low power consumption mode, and the installation control device can be flexibly deformed and expanded in multiple ways according to specific use occasions, and has low cost, simple circuit and efficient triggering.

Figure 202110825157

Description

Low-power-consumption safety protection control device and algorithm based on single chip microcomputer
Technical Field
The invention relates to the field of single-chip microcomputers, in particular to a low-power-consumption safety protection control device and an algorithm based on a single-chip microcomputer.
Background
In an application occasion requiring safety protection control, the critical data and the critical information under an emergency need to be directly erased or physically destroyed, so as to avoid leakage of the important information. The security control triggering means comprises various common modes such as water immersion, card pulling, switching, timing and the like, response speed only needs to be considered for triggering response and processing in a normal working mode with electrified equipment, but security control after the system is powered down is important, the equipment is required to be independently powered on a security function module for monitoring each security input state and responding in time under the condition that only a lithium battery supplies power after the power supply is powered down, the processor can be timely awakened to carry out specific security control steps after each signal is triggered in a standby state, and meanwhile, the power consumption of the whole security monitoring device in the standby state is required to be extremely low so as to meet the requirement of the service life of the lithium battery.
At present, a single chip microcomputer (Microcontrollers) is a kind of integrated circuit chip, and the functions of a central processing unit CPU with data processing capability, various I/O ports, interrupt systems, timers/counters (possibly including circuits such as a real driving circuit, a pulse width modulation circuit, an analog multiplexer, an a/D converter, etc.) are integrated on a silicon chip by using a very large scale integrated circuit technology to form a small and perfect microcomputer system, which is widely applied in the field of industrial control. Meanwhile, the singlechip has the advantages of simple circuit, low price and the like.
In chinese patent publication No. CN103425235A, a low-power-consumption standby circuit of a single chip microcomputer and a control method thereof are disclosed, including an MCU, a power VCC, an NPN transistor Q1 or a PNP transistor Q1, a resistor R1, a resistor R2, and a switch SW1, where an I/O port of the MCU may be configured to output a high level state and a low level state, and the two states may control the two transistors to be turned on or off, thereby controlling the MCU to be powered on or powered off.
The Chinese patent document with the publication number of CN208673086U discloses a low-cost and low-power-consumption timing wake-up circuit for a single chip microcomputer, which belongs to the field of management circuits of the single chip microcomputer and comprises the single chip microcomputer, a resistor R1, a resistor R2 and a capacitor C1, wherein the single chip microcomputer is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a capacitor C1 and a resistor R2, and the other ends of a capacitor C1 and a resistor R2 are both connected with a ground wire.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a low-power-consumption safety protection control device and an algorithm based on a single chip microcomputer.
The invention provides a low-power-consumption safety protection control device based on a single chip microcomputer, which comprises: the system comprises a singlechip, a main controller and a security protection triggering control circuit; the security trigger control circuit is connected with the single chip microcomputer, and the single chip microcomputer is connected with the main controller to carry out normal data communication in a live mode;
the security protection trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time-to-trigger circuit, a working mode switching circuit and a power supply switching circuit.
Preferably, the power supply switching circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a lithium battery;
one end of a first resistor R1 is a normally-supplied power VCC _3V3 end, the other end of the first resistor R1 is connected with the anode of a first diode D1, the cathode of the first diode D1 is connected with one end of a third resistor R3, the anode of the lithium battery is a VBAT end, the anode of the lithium battery is connected with one end of a second resistor R2, one end of a first capacitor C1 is connected with one end of a second resistor R2, the cathode of the lithium battery is connected with the other end of a first capacitor C1 and grounded, the other end of the second resistor R2 is connected with the anode of a second diode D2, the cathode of the second diode D2 is connected with one end of a third resistor R3, one end of the third resistor R3 is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 constitutes a VMCU _3V3 end, and the single chip microcomputer 3 ends are respectively connected with the DC/CU + DC end and the VDD + DC end, The other end of the third capacitor C3 is grounded, the VDD/DC + end of the single chip microcomputer is a power supply pin in a NORMAL working NORMAL mode of the single chip microcomputer, and the VBAT end of the single chip microcomputer is a power supply pin in a low-power-consumption working SLEEP mode of the single chip microcomputer.
Preferably, the operating mode determining circuit includes a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, a collector of the first triode Q1 is connected to one end of the sixth resistor R6 and one end of the fourth resistor R4, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected to a GPIO port of P1.5 of the single chip microcomputer, the other end of the sixth resistor R6 forms a VMCU _3V3 end, a base of the first triode Q1 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a VCC _3V3 end, and an emitter of the first triode Q1 is grounded.
Preferably, when the power supply is in a charged state during normal power supply, VCC _3V3 is 3.3V voltage, and the PowerCheck pin is at a low level; in the battery-only power-down state, VCC _3V3 is 0V, and the PowerCheck pin is high.
Preferably, the water logging trigger circuit includes a first probe, a seventh resistor R7 and a fourth capacitor C4, one path of the first probe is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected to one end of the fourth capacitor C4 and the P1.1 port of the single chip, and the other end of the fourth capacitor C4 is grounded.
Preferably, the card pulling trigger circuit includes a second probe, an eighth resistor R8, a ninth resistor R9, and a fifth capacitor C5, one path of the second probe is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is connected to the P1.2 port of the single chip microcomputer, one end of the eighth resistor R8, and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a VMCU _3V3 end, and the other end of the fifth capacitor C5 is grounded.
Preferably, the switch trigger circuit includes a touch switch and a sixth capacitor C6, one end of the touch switch is grounded, the other end of the touch switch is respectively connected to the P1.3 end of the single chip microcomputer and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
Preferably, the timing trigger circuit includes a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, the signal of the clock chip is DS3232, a VCC pin of the clock chip is connected to one end of a tenth resistor R10, the other end of the tenth resistor R10 is grounded, an INT # pin of the clock chip is respectively connected to a P1.4 port of the single chip and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is grounded, an SCL pin of the clock chip is respectively connected to one end of a twelfth resistor R12 and a P0.7 port of the single chip, an SDA pin of the clock chip is respectively connected to one end of the eleventh resistor R11 and the P0.6 port of the single chip, the other end of the eleventh resistor is connected to the other end of the twelfth resistor R12 to form a VMCU _3V3 end, a VBAT end of the clock chip is connected to one end of the eighth capacitor C8, the VBAT end of the clock chip forms a VMCU _3V3 end, and the GND end of the clock chip is connected with the other end of the eighth capacitor C8 and grounded.
Preferably, the main controller comprises an ARM chip and a DSP chip, and the main controller is connected with the single chip microcomputer through a serial port or an I2C interface.
The invention provides a low-power-consumption security control algorithm based on a single chip microcomputer, which comprises the following steps of:
step S1: power-on initialization: initializing a GPIO port of the singlechip, setting a card pulling trigger judgment port as analog input, and judging the occurrence of the event through a comparator; setting a water logging, switching and timing triggering judgment port as digital input, judging the occurrence of the events through the periodic scanning port state of a Timer, and initializing a comparator CP0 and a Timer 0;
step S2: and entering a main loop, and branching into two sub-loops according to the PowerCheck level state of the P1.5 port, wherein one sub-loop is a sleep mode sub-loop under the power supply of a battery, and the other sub-loop is a normal mode sub-loop under the normal power supply.
Step S3: if P1.5 is high level, then enter sleep mode subcircuit, set the single chip computer to enter sleep mode and set the awakening source as comparator 0 and port matching, if not triggered, then the single chip computer is in low power consumption mode, if any trigger event of water logging, card pulling, switching, timing and working mode change occurs, then the single chip computer is awakened, at this moment, read the awakening source status register, firstly judge the type of awakening source, then judge the concrete reason of awakening source, and then execute the corresponding response action.
Step S4: if the detection judges that the P1.5 is low level, normal mode sub-circulation is entered, the single chip microcomputer normally and sequentially executes the processing flow of each task required by the system, the triggering judgment of the water logging, the card pulling, the switching, the timing and the working mode is responded by an interruption mode, wherein the card pulling is realized by the interruption of a comparator 0, and the triggering judgment of the water logging, the switching, the timing and the working mode is realized by the interruption of a timer and the scanning of the port state at the timing.
Step S5: when the P1.5 level state changes, the corresponding working mode can be switched to enter in the next cycle judgment, and the two branch sub-cycles can be continuously judged again in the main cycle after the triggering event response is finished, so that the system can operate as required.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention develops a low-power-consumption security control device which is completed by using a C8051F912 singlechip, the security trigger control in a low-power-consumption sleep working mode is realized by configuring a corresponding awakening source, the system current is not more than 10 muA in the sleep mode actually measured, when a CR2450 lithium battery is selected, the battery capacity is 580mAh, and the service life of the lithium battery of the device in the low-power-consumption sleep mode is easily prolonged to more than 5 years;
2. the invention relies on C8051F912 singlechip, develop two applicable low-power consumption trigger configuration modes, one is the high level in the normality, the low level in transient state of the trigger state, suitable for being configured as the digital input; the other is normally low level, and the trigger state is continuously high level, and is suitable for being configured as an analog input. Flexible deformation and multipath expansion can be carried out according to specific use occasions;
3. the invention provides a low-cost security control scheme, which has simple circuit and high triggering efficiency, responds to various triggering events in a wake-up triggering mode in a power-down sleep mode, and simultaneously, a singlechip can be connected with a storage circuit in an extensible manner, so that key data can be erased or the key data can be directly physically destroyed when the triggering events occur; meanwhile, the single chip microcomputer can be further interconnected with other main controllers (such as ARM, DSP or other SOC chips) through a serial port or common interfaces such as I2C, the time from response to triggering in the electrified normal mode can be further transmitted to the main controllers, and other important tasks in the system can be conveniently completed in an expanded mode.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a low-power-consumption security control device based on a single chip microcomputer;
FIG. 2 is a circuit diagram of the power supply switching circuit of the present invention;
FIG. 3 is a circuit diagram of the present invention for determining the operation mode;
FIG. 4 is a diagram of a water soak trigger circuit of the present invention;
FIG. 5 is a circuit diagram of the card-pulling trigger circuit of the present invention;
FIG. 6 is a circuit diagram of the switch trigger of the present invention;
FIG. 7 is a timing trigger circuit diagram according to the present invention;
FIG. 8 is a diagram of a low-power security control algorithm of the single-chip microcomputer according to the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The invention comprises two parts, wherein one part is a hardware design block diagram of a low-power-consumption singlechip security control device and a hardware circuit specifically realized by each trigger circuit, so that the switching of a power supply under normal power supply and battery power supply, the judgment of a working mode and the establishment of the trigger circuit under each trigger mode are realized; the other part is a single-chip microcomputer low-power-consumption security control algorithm, and the trigger control under a normal mode and the awakening trigger control under a sleep low-power-consumption mode are realized.
As shown in fig. 1, in the hardware system block diagram of the present invention, the single chip microcomputer is selected from the C8051F912 of SILICON laboritories, and is directly connected to the security trigger control circuit, and the security trigger control circuit includes a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time-to-trigger circuit, a working mode switching circuit, and a power supply switching circuit; meanwhile, normal data communication in a live mode is carried out with a main controller through a serial port (or other common communication interfaces such as I2C) to realize expansion of system functions, and the main controller comprises an ARM chip, a DSP chip and other SOC controller chips.
As shown in fig. 2, the power supply switching circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a lithium battery, and the types of the first diode D1 and the second diode D2 are BAT 54C.
One end of a first resistor R1 is a normally-supplied VCC _3V3 end, the other end of the first resistor R1 is connected with the anode of a first diode D1, the cathode of the first diode D1 is connected with one end of a third resistor R3, the anode of the lithium battery is a VBAT end, the anode of the lithium battery is connected with one end of a second resistor R2, one end of a first capacitor C1 is connected with one end of a second resistor R2, the cathode of the lithium battery is connected with the other end of a first capacitor C1 and is grounded, the other end of the second resistor R2 is connected with the anode of a second diode D2, the cathode of a second diode D2 is connected with one end of a third resistor R3, one end of the third resistor R3 is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 forms a VMCU 3V3 end, and the VMCU 3V3 ends are respectively connected with the VDD/DC + end of the single chip microcomputer, VBAT terminal, and one terminal of a third capacitor C3, the other terminal of the third capacitor C3 being connected to ground. The VDD/DC + end of the single chip microcomputer is a power supply pin under a NORMAL working NORMAL mode of the single chip microcomputer, and the VBAT end of the single chip microcomputer is a power supply pin under a low-power-consumption working SLEEP mode of the single chip microcomputer.
The corresponding pins of VDD/DC + and VBAT of the singlechip C8051F912 are both connected to VMCU _3V3, and VMCU _3V3 is the back-end output of normally supplying VCC _3V3 and battery VBAT through BAT 54C. VBAT is the voltage at two ends of the lithium battery, is normally 3.3V and can be smaller and smaller, VCC _3V3 is the normal charged voltage, can normally reach 3.35V, and basically does not change in the corresponding ripple range. When VCC _3V3 is present, the output of VMCU _3V3 is at VCC _3V3, when VCC _3V3 is not present, the output of VMCU _3V3 is at VBAT. The power supply switching circuit realizes the switching between normal power supply and battery power supply, and ensures that the power supply voltage of the VMCU _3V3 exists all the time (unless the power supply is powered down and the battery power is exhausted at the same time).
As shown in fig. 3, the operation mode determination circuit: the working mode judging circuit comprises a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, wherein a collector of the first triode Q1 is respectively connected with one end of the sixth resistor R6 and one end of the fourth resistor R4, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected with a GPIO port of P1.5 of the single chip microcomputer, the other end of the sixth resistor R6 forms a VMCU _3V3 end, a base of the first triode Q1 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a VCC _3V3 end, and an emitter of the first triode Q1 is grounded.
The type of a first triode Q1 in the working mode judging circuit is 2N3904 to build a judging circuit, when a power supply is in a charged state when supplying power normally, VCC _3V3 is 3.3V voltage, and a PowerCheck pin is at a low level; in the power-down state with only battery power supply, VCC-3V 3 is 0V, and the PowerCheck pin is high level; the PowerCheck judgment signal is accessed to a GPIO port of P1.5 of the singlechip C8051F 912. The working mode judging circuit is connected with a P1.5 GPIO port of the singlechip through a PowerCheck signal, so that the PowerCheck level state is changed after the working mode is converted, and the singlechip acquires the current working mode through reading the P1.5 port state.
As shown in fig. 4, the water logging trigger circuit includes a first probe, a seventh resistor R7, and a fourth capacitor C4, one path of the first probe is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected to one end of the fourth capacitor C4 and the P1.1 port of the single chip, and the other end of the fourth capacitor C4 is grounded.
The water logging trigger circuit is triggered by two probe signals inserted into water to generate short circuit, wherein 1 path of probe signal is GND, the other path of signal is connected to a GPIO port of P1.1 of the singlechip C8051F912, and meanwhile, a 0.1uF capacitor is connected to the ground to prevent shaking. The water immersion trigger circuit realizes water immersion trigger after the water immersion probe is short-circuited in water, the WaterDestroy + signal level is changed, and the single chip microcomputer obtains the trigger event by reading the state of the P1.1 port, so that corresponding action is performed.
As shown in fig. 5, the card unplugging trigger circuit includes a second probe, an eighth resistor R8, a ninth resistor R9 and a fifth capacitor C5, one path of the second probe is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is connected to the P1.2 port of the single chip, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a VMCU _3V3 end, and the other end of the fifth capacitor C5 is grounded.
The card pulling trigger circuit is used for triggering the two probe signals in a normal short circuit on the bottom plate and in a disconnection mode after the module is pulled out. Wherein, 1 way probe signal is 51K resistance pull down to GND, and another way signal is the GPIO port of pulling up 1M resistance to the power and accessing the P1.2 of singlechip C8051F912, connects 0.1uF electric capacity to ground simultaneously and prevents trembling. The card pulling trigger circuit is used for separating two probes of a normal short circuit of a board card when the module is pulled out of a case, the card pulling trigger circuit triggers the card pulling, the CardDestroy + analog voltage value of a P1.2 port changes, and the single chip microcomputer obtains the trigger event through the state change output by the configured comparator, so that corresponding action is performed.
As shown in fig. 6, the switch trigger circuit includes a touch switch and a sixth capacitor C6, one end of the touch switch is grounded, the other end of the touch switch is connected to the P1.3 end of the single chip microcomputer and one end of the sixth capacitor C6, respectively, and the other end of the sixth capacitor C6 is grounded.
The switch trigger circuit is triggered by pressing a touch switch (the trigger signal is in short circuit with GND), and returns to a normal state after being released, wherein the trigger signal is connected to a GPIO port of P1.3 of the singlechip C8051F912 and is connected with a 0.1uF capacitor to the ground for anti-shake. The switch trigger circuit realizes instantaneous short circuit at two ends of the key after the tact switch is pressed down, the two ends of the key are separated again after the key is released, the level of a switch trigger signal is changed in the process, and the single chip microcomputer obtains the trigger event by reading the state of the P1.3 port, so that corresponding action is performed.
As shown in fig. 7, the timing trigger circuit includes a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, the signal of the clock chip is DS3232, the VCC pin of the clock chip is connected to one end of a tenth resistor R10, the other end of the tenth resistor R10 is grounded, the INT # pin of the clock chip is connected to the P1.4 port of the single chip and one end of the seventh capacitor C7 respectively, the other end of the seventh capacitor C7 is grounded, the SCL pin of the clock chip is connected to one end of a twelfth resistor R12 and the P0.7 port of the single chip respectively, the SDA pin of the clock chip is connected to one end of an eleventh resistor R11 and the P0.6 port of the single chip respectively, the other end of the eleventh resistor R12 is connected to the other end of the twelfth resistor R12 and forms a VMCU 3V3 terminal, the VBAT terminal of the clock chip 737 terminal of the eighth capacitor C8 is connected to one end of the VMCU 463V 84, the GND terminal of the clock chip is connected to the other terminal of the eighth capacitor C8 and is grounded. The 32KHZ pin of the clock chip is a 32.768KHZ clock output port, and the invention is not used, suspended and not externally connected; the RST # pin of the clock chip is a low-level effective reset pin with drain open-drain input/output, the invention only uses the pull-up resistance function of connecting the internal 50K omega of the chip to the VCC pin, and the RST # pin is electrified, self-reset and suspended without external connection.
The timing trigger circuit adopts a DS3232 clock chip to have the RTC clock function, and can set time and timing alarm time at the same time, and trigger signals are generated after the timing time. The trigger signal is accessed to a GPIO port of P1.4 of the singlechip C8051F912, and meanwhile, the trigger signal is connected with a 0.1uF capacitor to the ground for anti-shaking. The timing trigger circuit adopts an RTC chip DS3232 to realize timing and alarm functions, is interconnected with a singlechip P1.4 through a chip interrupt output pin TimeDestroy, triggers when the timing time reaches an event, and the singlechip acquires the trigger event by reading the state of a P1.4 port so as to make corresponding action.
As shown in fig. 8, the low-power-consumption security control algorithm for the single chip microcomputer is implemented by programming the C language of the single chip microcomputer:
step 1: power-on initialization: and initializing a port of the GPIO port, and enabling a weak pull-up function of a port of the single chip microcomputer in order to avoid introducing a large amount of current consumption by an external pull-up resistor. Setting a card pulling triggering judgment port as analog input, and judging the occurrence of the event through a comparator; the water logging, switching and timing triggering judging ports are set to be digital input, and the occurrence of the events is judged by periodically scanning the states of the ports through a Timer, so that the comparator CP0 and the Timer0 need to be initialized, and in addition, other functional modules of the single chip microcomputer needed by the normal work of the system need to be initialized.
Step 2: entering a main cycle: in while (1) main loop, according to P1.5 port PowerCheck level state, the branch is divided into two sub-loops, one is sleep mode sub-loop under battery power supply, and the other is normal mode sub-loop under normal power supply.
And step 3: if P1.5 is high level at first, then enter sleep sub-cycle, set the single chip to enter sleep mode and set the wake-up source to comparator 0(CP0 rising edge) and PORT MATCH (PORT _ MATCH). If the trigger is not triggered all the time, the single chip microcomputer is in a low power consumption mode all the time, the actually measured current consumption is only about 8 muA, if any trigger event of water immersion, card pulling, switching, timing and working mode change occurs, the single chip microcomputer is awakened, at the moment, an awakening source state register is read, the type of the awakening source is judged firstly, then the specific reason of the awakening source is judged, and therefore the corresponding response action is executed.
And 4, step 4: if the detection judges that the P1.5 is low level, normal sub-circulation is entered, and the single chip microcomputer normally and sequentially executes the processing flow of each task required by the system. In order to improve the response speed and improve the security processing efficiency, at the moment, the triggering judgment of water immersion, card pulling, switching, timing and working modes is responded by an interruption mode, wherein the card pulling is realized by interruption of a comparator 0(CP0 rising edge), and the other modes are realized by interruption of a timer to scan the port state at regular time.
And 5: when the P1.5 level state changes, the corresponding working mode is switched to enter in the next cycle determination, that is, the main cycle continuously performs re-determination of the two branch sub-cycles after the triggering event response is completed, so that the system operates as required.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. The utility model provides a low-power consumption safety protection controlling means based on singlechip which characterized in that includes: the system comprises a singlechip, a main controller and a security protection triggering control circuit; the security trigger control circuit is connected with the single chip microcomputer, and the single chip microcomputer is connected with the main controller to carry out normal data communication in a live mode;
the security protection trigger control circuit comprises a water immersion trigger circuit, a card pulling trigger circuit, a switch trigger circuit, a timing time-to-trigger circuit, a working mode switching circuit and a power supply switching circuit.
2. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the power supply switching circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a lithium battery;
one end of a first resistor R1 is a normally-supplied power VCC _3V3 end, the other end of the first resistor R1 is connected with the anode of a first diode D1, the cathode of the first diode D1 is connected with one end of a third resistor R3, the anode of the lithium battery is a VBAT end, the anode of the lithium battery is connected with one end of a second resistor R2, one end of a first capacitor C1 is connected with one end of a second resistor R2, the cathode of the lithium battery is connected with the other end of a first capacitor C1 and grounded, the other end of the second resistor R2 is connected with the anode of a second diode D2, the cathode of the second diode D2 is connected with one end of a third resistor R3, one end of the third resistor R3 is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the other end of the third resistor R3 constitutes a VMCU _3V3 end, and the single chip microcomputer 3 ends are respectively connected with the DC/CU + DC end and the VDD + DC end, The other end of the third capacitor C3 is grounded, the VDD/DC + end of the single chip microcomputer is a power supply pin in a NORMAL working NORMAL mode of the single chip microcomputer, and the VBAT end of the single chip microcomputer is a power supply pin in a low-power-consumption working SLEEP mode of the single chip microcomputer.
3. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the working mode judging circuit comprises a first triode Q1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, wherein a collector of the first triode Q1 is connected with one end of a sixth resistor R6 and one end of a fourth resistor R4 respectively, the other end of the fourth resistor R4 forms a PowerCheck pin, the PowerCheck pin is connected with a GPIO port of P1.5 of the single chip microcomputer, the other end of the sixth resistor R6 forms a VMCU _3V3 end, a base of the first triode Q1 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 forms a VCC _3V3 end, and an emitter of the first triode Q1 is grounded.
4. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 3, characterized in that: when the power supply is in a charged state during normal power supply, VCC-3V 3 is 3.3V voltage, and the PowerCheck pin is at low level; in the battery-only power-down state, VCC _3V3 is 0V, and the PowerCheck pin is high.
5. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the water logging trigger circuit comprises a first probe, a seventh resistor R7 and a fourth capacitor C4, one path of the first probe is connected with one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, the other path of the first probe is respectively connected with one end of the fourth capacitor C4 and a P1.1 port of the single chip microcomputer, and the other end of the fourth capacitor C4 is grounded.
6. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the card pulling trigger circuit comprises a second probe, an eighth resistor R8, a ninth resistor R9 and a fifth capacitor C5, one path of the second probe is connected with one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, the other end of the second probe is respectively connected with a P1.2 port of the single chip microcomputer, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the eighth resistor R8 forms a VMCU _3V3 end, and the other end of the fifth capacitor C5 is grounded.
7. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the switch trigger circuit comprises a touch switch and a sixth capacitor C6, one end of the touch switch is grounded, the other end of the touch switch is respectively connected with the P1.3 end of the single chip microcomputer and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded.
8. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the timing trigger circuit comprises a clock chip, a seventh capacitor C7, an eighth capacitor C8, a 10 th resistor R10, an eleventh resistor R11 and a twelfth resistor R12, wherein a signal of the clock chip is DS3232, a VCC pin of the clock chip is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is grounded, an INT # pin of the clock chip is respectively connected with a P1.4 port of the singlechip and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is grounded, an SCL pin of the clock chip is respectively connected with one end of a twelfth resistor R12 and a P0.7 port of the singlechip, an SDA pin of the clock chip is respectively connected with one end of the eleventh resistor R11 and a P0.6 port of the singlechip, the other end of the eleventh resistor and the other end of the twelfth resistor R12 are connected to form a VMCU 3V3 end, a VBAT end of the clock chip is connected with one end of an eighth capacitor C8, the VBAT end of the clock chip forms a VMCU _3V3 end, and the GND end of the clock chip is connected with the other end of the eighth capacitor C8 and grounded.
9. The low-power-consumption safety protection control device based on the single chip microcomputer according to claim 1, characterized in that: the main controller comprises an ARM chip and a DSP chip, and is connected with the single chip microcomputer through a serial port or an I2C interface.
10. A low-power-consumption security protection control algorithm based on a single chip microcomputer, which adopts the low-power-consumption security protection control device based on the single chip microcomputer in any one of claims 1 to 9, and is characterized by comprising the following steps:
step S1: power-on initialization: initializing a GPIO port of the singlechip, setting a card pulling trigger judgment port as analog input, and judging the occurrence of the event through a comparator; setting a water logging, switching and timing triggering judgment port as digital input, judging the occurrence of the events through the periodic scanning port state of a Timer, and initializing a comparator CP0 and a Timer 0;
step S2: and entering a main loop, and branching into two sub-loops according to the PowerCheck level state of the P1.5 port, wherein one sub-loop is a sleep mode sub-loop under the power supply of a battery, and the other sub-loop is a normal mode sub-loop under the normal power supply.
Step S3: if P1.5 is high level, then enter sleep mode subcircuit, set the single chip computer to enter sleep mode and set the awakening source as comparator 0 and port matching, if not triggered, then the single chip computer is in low power consumption mode, if any trigger event of water logging, card pulling, switching, timing and working mode change occurs, then the single chip computer is awakened, at this moment, read the awakening source status register, firstly judge the type of awakening source, then judge the concrete reason of awakening source, and then execute the corresponding response action.
Step S4: if the detection judges that the P1.5 is low level, normal mode sub-circulation is entered, the single chip microcomputer normally and sequentially executes the processing flow of each task required by the system, the triggering judgment of the water logging, the card pulling, the switching, the timing and the working mode is responded by an interruption mode, wherein the card pulling is realized by the interruption of a comparator 0, and the triggering judgment of the water logging, the switching, the timing and the working mode is realized by the interruption of a timer and the scanning of the port state at the timing.
Step S5: when the P1.5 level state changes, the corresponding working mode can be switched to enter in the next cycle judgment, and the two branch sub-cycles can be continuously judged again in the main cycle after the triggering event response is finished, so that the system can operate as required.
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