CN101208647A

CN101208647A - Computer volatile memory power backup system

Info

Publication number: CN101208647A
Application number: CNA2006800194778A
Authority: CN
Inventors: D·费尔德曼; D·科查茨; S·坎恩; I·阿蒂尔斯; A·帕克; M·A·塞尔赫
Original assignee: Microsemi Corp Analog Mixed Signal Group Ltd
Current assignee: Microsemi PoE Ltd
Priority date: 2005-03-31
Filing date: 2006-03-19
Publication date: 2008-06-25

Abstract

A system for placing and maintaining a computer in a standby mode during power failure, the system comprising: a mains power failure sensor; a source of standby power, the source of standby power being less than the power available for full operation; a volatile memory arranged to be powered from the source of standby power in the event of a failure of mains power; and a processor operative responsive to the mains power failure sensor to store status information on the volatile memory and reduce power demand of the processor and associated devices to no more than that available from the source of standby power. In an exemplary embodiment the source of standby power is one of a battery, a capacitor, a flywheel energy storage system and a power over Ethernet connection.

Description

Computer volatile memory power backup system

Background of invention

The present invention relates to the back-up source field, relate in particular to during main supply breaks down by powering (preferably utilizing the power supply on the Ethernet) thereby the device of backup computer for volatile memory.

For the office and family of cableization, be a kind of important driving force based on the LAN (Local Area Network) of ethernet technology and the continuous development of wide area network with structuring cable system with many pair twists zygonema always.Ubiquitous LAN (Local Area Network) and operation equipment have thereon caused a kind of like this situation, promptly usually need to connect a kind of network operation equipment, and are this power devices by network layout by this network preferably.Powering by network layout has many advantages, comprising but be not limited to: installation cost has reduced, and power center has changed, safety and managed also centralization.

There are several patents to be used to address the above problem, comprising: people's such as Lehr United States Patent (USP) 6,473,608, its content is incorporated herein by reference; People's such as Lehr United States Patent (USP) 6,643,566, its content is incorporated herein by reference.In addition, for solving the above-mentioned problem that remote equipment on the Ethernet is powered Network Based, the standard of having announced is IEEE 802.3af, and its content is incorporated herein by reference.

POE (PoE) provide limited electric weight to the consumer that is connected, and above-mentioned standard is limited to maximum 12.95 watts with the Mean Input Power of consumer.Computing machine particularly desk-top computer is powered by the main line connection of electricity, and usually above 15 watts.If main supply breaks down, it is to keep power supply in the 17-20ms that computer power supply was supplied with at least one cycle of main supply.The time cycle of keeping power supply when the disappearance main supply is called as the hold-up time.When the hold-up time stops, provide computer power supply no longer reliably, and all information has been lost all in the processor state of this computing machine and the volatile memory.Similar is that any information of being stored in the video memory (such as the font that is just showing on the screen) has also been lost.Prior art is to support each computing machine with uninterrupted power supply (ups) Unity to the solution of this difficulty, and UPS is designed to power supply reliably in a period of time after losing main supply.Usually, UPS provides warning to the user, thereby makes the user can be with all information stores in nonvolatile memory and close this computing machine in an orderly way.In another kind of prior art solution, UPS connects by the network that is connected to computing machine, and closes the program that all are just moving in an orderly manner.Usually, UPS can continued power number minute, if the words of in time taking action just can realize orderly closing.

For each computing machine provides UPS is very expensive, and needs each computer location place that additional space is arranged.In addition, safeguard that the independent UPS in each computing machine place can increase expense.Perhaps, provide the UPS of centralization, thereby connect up and power by being connected to each special-purpose AC with the computing machine that is supported.This special-purpose wiring installs very expensive, and it is also very expensive to revise this special-purpose wiring when changing computer location.

Modern computer is designed to have some power saving feature, just as given example in high level computer power interface (ACPI) standard.Particularly, defined standby mode or sleep state, the information that comprises all registers that wherein is used for the definition processor state all is stored in volatile memory.Next, close the power supply of processor, hard disk drive and monitor, simultaneously electric energy is exclusively offered standby memory power bus.For example, in Intel ACPI 3.0 standards, defined this mode of operation.In order to realize " Energy Star " of USEPA evaluation, computing machine must significantly reduce its power in standby mode.For U.S. government's guilding principle of specifically being illustrated in the administrative decree that meets U.S. president signature on July 31 calendar year 2001, the electrical equipment that comprises computing machine that U.S. government purchases is preferably under the ideal case energy consumption less than 1 watt.

Fig. 1 shows the exemplary embodiment of the Computer Architecture of supporting ACPI 3.0.Computing machine 10 comprises: power supply unit 20 is made of controlled source 22 and standby power 24; CPU 30; Hard disk drive 40; Volatile memory 50; OR circuit 60; Standby power bus 65; And the AC main line connects 70.Power supply 20 receives and connects 70 electric energy from the AC main line, and the controlled source 22 of power supply unit 20 is in response to from CPU 30 and be denoted as the output signal of PS_ON#, and this will further explain hereinafter.Controlled source 22 output multiple voltage are comprising 5 volts, 3.3 volts and 12 volts.Independent and the 5 volts of outputs that be denoted as 5V STBY of standby power 24 outputs, this output is not subjected to the influence of the state of PS_ON#.These 5 volts outputs are fed to CPU 30 and hard disk drive 40, and are connected to an input of OR circuit 60.These 5 volts of standby outputs are connected to the second input OR circuit 60, and the output of OR circuit 60 is connected to volatile memory 50 by standby power bus 65 again.Miscellaneous equipment also can receive the electric energy from standby power 24.

In operating process, when can connecting from the AC main line, the AC main supply obtains 70 and during in response to effective low signal PS_ON#, and a plurality of power supplys outputs by controlled source 22 offer CPU 30 and hard disk drive 40 with electric energy.By 5 volts of outputs of controlled source 22,, by standby power bus 65, also electric energy is offered volatile memory 50 again through OR circuit 60.If logic high signal appears on the PS_ON#, remove from 5 volts of outputs, 3.3 volts of outputs and 12 volts of electric energy of exporting in response to the controlled source 22 of logic high signal.Yet, still,, electric energy is offered volatile memory 50 and is connected to above-mentioned 5 volts of any miscellaneous equipments for the treatment of machine circuit through OR circuit 60 by standby power 24.In addition, it is uncharged that those equipment of special other voltage that provides from controlled source 22 are provided, unless the dual supply arrangement is provided.This arrangement well known to a person skilled in the art and be to have bought, for example, and the FairchildFAN5063 biswitch controller of selling by the Fairchild Semiconductor that uses Maine state South Portland.

Support in the computing machine of this architecture that power supply 20 is in response to by the CPU 30 PS_ON# signal that produced of the power-management interface (not shown) of the chipset relevant with CPU 30 particularly being designed for.Thus, in order to proceed to standby mode, before the value with PS_ON# is made as height, CPU 30 will comprise that at first all information stores of status register are in volatile memory 50.In one embodiment, this realizes by enabling System Management Mode (SMM).Unfortunately, if lose the AC main supply, then CPU 30 shortage time enough and warning proceed to standby mode in an orderly way, because the dead time of 17-20ms is not enough.In addition, do not provide any mechanism when losing the AC main supply, to start standby mode.In addition, if lost the AC main supply, then keep power bus 65 without any the source of electric energy.

Above be to be described using under the situation of OR circuit 60, but this and do not mean that by any way and limit.Particularly, in one embodiment, substitute OR circuit 60 with the FET switch of a plurality of series connection, first in the described FET switch is used for and will feeds electric energy into the input of storer 50 and follow-up switch.The United States Patent (USP) 6 that is entitled as " System and Methodfor Providing a Hibernation Mode in an Information Handling System " that people such as Kohno submitted on February 18th, 2003,523,125 have described a kind of like this embodiment.In another embodiment, OR circuit 60 comprises the biswitch controller, such as above-mentioned Fairchild FAN5063.

Fig. 1 b shows the high level schematic diagram according to the chipset system chart of the computing machine 10 of prior art support Advanced Configuration and Power Interface.Computing machine 10 comprises: CPU 30; North bridge 80; Volatile memory 50; Video interface 85; South bridge 90; IDE device 94; USB port 96; Serial port 98; And audio frequency and UART 99.The operating system that runs on the computing machine 10 has realized ACPI, and is controlling the power supply operating position (the power supply operating position that comprises CPU 30) of each connection device.The processor system bus of north bridge 80 and CPU 30 is directly mutual and be connected thereon.Video interface 85 is connected to north bridge 80, and in one embodiment, this video interface 85 can comprise one or more in following: cathode-ray tube display; Digital video output; The low voltage digital signal interface; And Accelerated Graphics Port interface.Volatile memory 50 is connected to north bridge 80, and in typical embodiment, this volatile memory 50 comprises Synchronous Dynamic Random Access Memory.

South bridge 90 is connected to north bridge 80, and is connected to IDE equipment 94, USB port 96, serial port 96 and audio frequency and UART 99.Thus, north bridge 80 and CPU 30 direct communications, and south bridge 90 is communicated by letter with CPU 30 by north bridge 80.ACPI can be used for controlling the power supply operating position of each connection device, and can be used for any equipment (comprising CPU 30) in the computing machine 10 are placed and reduce power consumption mode.

Unfortunately, when main supply broke down, ACPI just can't reduce power consumption, had not had because be used for the working power of computing machine 10.In addition, when main supply breaks down, no longer be volatile memory 50 power supplies, under the situation that does not have power supply, all information that are stored thereon have all been lost thus.

Above be to be described, yet this does not also mean that by any way and limit in conjunction with the computing machine that is rendered as northbridge/southbridge architecture.Other architecture (comprising the Intel hub architecture) presents some similar problems, the losing of the electric power thus supplied when breaking down about the AC main supply and information and processor state.

People need that a kind of prior art do not provide can prevent information dropout in the computing machine and not need the automation equipment of UPS or other macrocell back-up system simultaneously when outage.

Summary of the invention

Correspondingly, fundamental purpose of the present invention is the shortcoming that overcomes prior art.The present invention by before losing power supply output, thereby the fault that senses the AC main supply at the very start that is preferably in power off periods realizes above-mentioned fundamental purpose.Interruption is produced, and processor calls a routine in response to this interruption, before the power supply of losing the job system environments, memory environments, preliminary election CPU and configuration surroundings and video memory (optional) is stored on the volatile memory.Then, during breaking down, the AC main supply powers to above-mentioned volatile memory by standby power supply.

In one embodiment, standby power is fed to the input of computer power supply.The interruption routine of processor sends to above-mentioned power supply with logic high PS_ON# signal, and all power supplys that this power supply has been closed except that standby power in response to this logic high signal are exported.In exemplary embodiment, before the output that loses the AC main supply, this interruption routine is reduced to power demand the value that can obtain from standby power supply.In another embodiment, any short-term electric energy mismatch is stored by the energy in the capacitor and is supported that this capacitor preferably is arranged to store high-tension energy.Thus, the standby power by computing machine is above-mentioned volatile memory power supply, and the electric energy of standby power passes over from standby power supply.

In one embodiment, interruption routine makes those receptions descend from the device power of the electric energy of above-mentioned power supply, the result, and power demand has reduced.In typical embodiment, control hub or south bridge power are descended, thus power demand is reduced to the level that standby power supply can be supported.

In another embodiment, standby power supply is operated a plurality of DC/DC converters, and each during its output is exported with a plurality of voltages of computer power supply is carried out inclusive-OR operation.For all devices of computing machine, thereby electric power has been kept the sufficiently long time and is made interruption routine can finish its storage operation.In one embodiment, interruption routine descends each plant capacity, total power demand is reduced to be less than or equal to the value that standby power supply can provide thus.In typical embodiment, control hub or south bridge power are descended, thus power demand is reduced to the level that standby power supply can be supported.Thus, be above-mentioned volatile memory power supply by an independent power supply that is separated with the principal computer power supply, this independent power supply receives the electric energy from standby power supply.

In one embodiment, routine of above-mentioned interrupt call, this routine produces as the described S3 sleep state of ACPI 3.0 standards.In another embodiment, produced S2 sleep state in the above-mentioned standard.In one embodiment, provide standby power supply by battery to volatile memory.

The invention provides a kind of system that computing machine is placed and maintains standby mode between turnoff time, this system comprises: the device that is used for sensing main supply fault; Be used to provide the device of standby power, the available horsepower of this standby power when working fully; Volatile memory is arranged to be used to provide the device of standby power to power by above-mentioned; And processor, this processor operationally is not more than the value that can obtain from the device that is used to provide standby power in response to the device that is used for the sensing fault status information is stored on the volatile memory and the power demand of computing machine is reduced to.

In one embodiment, this processor by system management interrupt operationally in response to the device of sensing fault.In another embodiment, this processor is by a device that interrupts operationally in response to the sensing fault.

In one embodiment, this system also comprises a power supply that presents output of first power supply and the output of at least one second source, this power supply in response to the signal of from processor so that in first power supply output power supply, ending to above-mentioned at least one second source output power supply, this power supply is arranged to just receive the electric energy that is used to provide the device of standby power from above-mentioned when main supply breaks down sensing, volatile memory is arranged to export by first power supply and powers, and is used to provide the device of standby power to power by above-mentioned therefrom.Preferably, operationally power demand is reduced to the performance number that to obtain from the above-mentioned device that is used for providing standby power in response to the power supply of above-mentioned signal.

In one embodiment, this system also comprises the DC/DC converter that is associated with the above-mentioned device that is used to provide standby power, this volatile memory is arranged to be used to provide the device of standby power to power by above-mentioned, above-mentionedly is used to provide the device of standby power then to power by above-mentioned DC/DC converter.In another embodiment, this processor is operationally stored above-mentioned status information sensing within the 17ms that main supply breaks down.

In one embodiment, volatile memory comprises disk cache.In another embodiment, this status information comprises at least some contents of video memory.

In one embodiment, this status information comprises at least one the configuration in network interface card and the sound card.In another embodiment, above-mentionedly be used to provide the device of standby power to comprise the charging equipment controller, it operationally receives electric energy by telecommunication cable.Preferably, this system also comprises the device that is used for the electric energy that sensing receives, and above-mentioned processor is operationally in response to the device that is used for the sensing fault be used for the device of the electric energy that sensing receives.Preferably, the charging equipment controller meets IEEE 802.3af standard.

In one embodiment, the device that is used for the sensing fault comprises analog to digital converter, and the above-mentioned device that is used for the sensing fault operationally compares the output and a reference value of analog to digital converter.In another embodiment, the above-mentioned device that is used for the sensing fault comprises digital to analog converter, and operationally the output of this converter and signal in response to main supply is compared.

In one embodiment, processor can be worked with storaging state information in the kernel program pattern.In another embodiment, processor can be worked with storaging state information under the BIOS routine.

In one embodiment, this system comprises that also being used for the main supply that sensing breaks down recovers normal device, and this processor operationally is used for device that sensing recovers so that obtain status information again from volatile memory in response to above-mentioned.In another embodiment, it is one of following that the above-mentioned device that is used to provide standby power comprises: battery, and capacitor, the flywheel energy storage system, and Ethernet connects power supply.In another embodiment, the above-mentioned device that is used to provide standby power comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.

Individually, the invention provides a kind of system that computing machine is placed and maintains standby mode between turnoff time, this system comprises: the main supply fault sensor; Standby power, the power of this standby power available horsepower when working fully; Volatile memory is arranged to power by above-mentioned standby power when main supply breaks down; And processor, this processor operationally stores on the volatile memory in response to the main supply fault sensor so that with status information and the power demand of this processor and relevant device is reduced to the available horsepower that is not more than above-mentioned standby power.

In one embodiment, this processor passes through system management interrupt operationally in response to the main supply fault sensor.In another embodiment, this processor can the work in one of kernel program pattern and BIOS routine in response to the main supply fault sensor.

In one embodiment, it is one of following that above-mentioned standby power comprises: battery, and capacitor, the flywheel energy storage system, and Ethernet connects power supply.In another embodiment, the above-mentioned device that is used to provide standby power comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.

In one embodiment, this system comprises that also main supply recovers sensor, and described processor further operationally recovers sensor so that recover described status information from described volatile memory in response to described main supply.In another embodiment, this processor operationally recovers described status information not needing to restart under the situation of computing machine.

Individually, the invention provides a kind of method that when main supply breaks down computing machine is backed up, described method comprises: standby power is provided; Volatile memory is provided; The fault of sensing main supply; The interrupt handler in response to above-mentioned sensing; Will with above-mentioned processor associated state information stores on the volatile memory that is provided; And power to above-mentioned volatile memory from the standby power that is provided, during breaking down, main supply keeps the status information of being stored sensing thus.

In one embodiment, above-mentioned interrupt procedure is undertaken by system management interrupt.In another embodiment, this method also comprises: a kind of power supply that presents output of first power supply and the output of at least one second source is provided; When main supply breaks down, from of the power supply power supply of above-mentioned standby power to being provided; And, wherein above-mentioned volatile memory power supply to small part is undertaken by above-mentioned power supply from above-mentioned standby power in above-mentioned first power supply output power supply, ending to export power supply to above-mentioned at least one second source.Preferably, the step of above-mentioned termination power supply eases down to available horsepower value less than above-mentioned standby power with the power demand of computing machine.

In one embodiment, said method also comprises, and the electric pressure converter that is associated with the standby power that is provided is provided, and wherein from the standby power that is provided volatile memory being powered is that the electric pressure converter that passes through to be provided to small part carries out.In another embodiment, the step of above-mentioned storaging state information is to realize sensing within the 17ms that main supply breaks down.

In one embodiment, volatile memory comprises disk cache.In another embodiment, above-mentioned status information comprises at least some contents in the video memory.In another storer, above-mentioned status information comprises at least a configuration in network interface card and the sound card.

In one embodiment, the standby power that is provided is associated with POE.In another embodiment, above-mentioned storing step is to be finished by the processor that can work in one of kernel program pattern and BIOS routine.In another embodiment, said method also comprises: the main supply that sensing breaks down recovers normal; And from volatile memory, obtain above-mentioned status information again.

In one embodiment, it is one of following that the standby power that is provided comprises: battery, and capacitor, the flywheel energy storage system, and Ethernet connects power supply.In another embodiment, the standby power that is provided comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.

According to following accompanying drawing and description, it is clear that other features and advantages of the present invention all will become.

Description of drawings

How the present invention is tried out in order to understand the present invention better and to demonstrate, now with reference to the accompanying drawing that only provides as example, wherein identical label specifies corresponding element or part to run through whole.

In detail with reference to accompanying drawing, shown various details only only are to illustrate better embodiment of the present invention as example and its purpose now, and the content that this paper provided is to be considered to the most useful and description of easy understanding about aspects such as the principle of the invention and notions.At this on the one hand, except that the present invention being made the necessary content of basic comprehension, do not attempt to show in greater detail out CONSTRUCTED SPECIFICATION of the present invention, given in conjunction with the accompanying drawings description makes that see in practice can be with implementing the present invention by some kinds of forms with it will be apparent to those skilled in that.In the accompanying drawings:

Fig. 1 a shows according to prior art and supports the high level schematic diagram that the power supply of the computing machine of Advanced Configuration and Power Interface connects;

Fig. 1 b shows the high level schematic diagram according to the chipset system chart of the computing machine of prior art support Advanced Configuration and Power Interface;

Fig. 2 a is the high level block diagram that principle according to the present invention is used to realize the network of the POE from switch to a plurality of nodes;

Fig. 2 b is the high level block diagram that principle according to the present invention is used to realize the network of therefrom cross-module POE to a plurality of nodes;

Fig. 3 a is the high level block diagram of first embodiment of principle according to the present invention architecture that standby power supply is provided by POE;

Fig. 3 b is the high level block diagram of second embodiment of principle according to the present invention architecture that standby power supply is provided by POE;

Fig. 3 c is the high level block diagram of the 3rd embodiment of principle according to the present invention architecture that standby power supply is provided by POE;

Fig. 3 d is the high level block diagram of the 4th embodiment of principle according to the present invention architecture that standby power supply is provided by POE;

Fig. 3 e is the high level block diagram of the embodiment of principle according to the present invention architecture that standby power supply is provided to volatile memory by battery;

Fig. 4 a shows the timing diagram of the relation between the signal specific of principle according to the present invention in the architecture of Fig. 3 a;

Fig. 4 b shows the timing diagram of principle according to the present invention relation between signal specific and the overall power requirement in the architecture of Fig. 3 b;

Fig. 4 c shows the timing diagram of principle according to the present invention relation between signal specific and the overall power requirement in the architecture of Fig. 3 c;

Fig. 4 d shows the timing diagram of principle according to the present invention relation between signal specific and the overall power requirement in the architecture of Fig. 3 d;

Fig. 4 e shows the timing diagram of the relation between the signal specific of principle according to the present invention in the architecture of Fig. 3 e;

Fig. 5 shows according to the CPU of schematic diagram 3a of the present invention and the chipset high level flow chart in response to the embodiment of the operation of power fail interrupt;

Fig. 6 a shows the high level flow chart according to the embodiment of the operation of the architecture of schematic diagram 3a of the present invention;

Fig. 6 b shows the high level flow chart according to the embodiment of the operation of the architecture of schematic diagram 3b of the present invention;

Fig. 6 c shows the high level flow chart according to the embodiment of the operation of the architecture of schematic diagram 3c of the present invention;

Fig. 6 d shows the high level flow chart according to the embodiment of the operation of the architecture of schematic diagram 3d of the present invention;

Fig. 6 e shows the high level flow chart according to the embodiment of the operation of the architecture of schematic diagram 3e of the present invention;

Fig. 7 a shows the high level, functional block diagram according to first embodiment of principle AC proof scheme of the present invention;

Fig. 7 b shows the high level, functional block diagram according to second embodiment of principle AC proof scheme of the present invention;

Fig. 7 c shows the high level flow chart according to this operation of principle AC proof scheme of the present invention;

Fig. 8 is the high level flow chart of this operation of the embodiment of the principle according to the present invention BIOS routine of utilizing system management interrupt; And

Fig. 9 is the high level flow chart according to the operation of the embodiment of the operation of arbitrary architecture among the schematic diagram 3a-3d of the present invention, is used at the high power POE or has one of these two kinds of patterns of POE work of the Power Limitation of IEEE802.3af.

Embodiment

Each embodiment of this paper can be by powering to volatile memory, preferably by the use POE computing machine being backed up when outage.Particularly, the main supply fault sensed to and produce one to processor and interrupt, interruption routine is saved in each position of volatile memory with environmental information and data, this volatile memory receives standby power supply when main supply breaks down.In typical embodiment, above-mentioned interruption routine starts the sleep state by operating system management.

Before in detail explaining at least one embodiment of the present invention, be appreciated that the present invention is not limited to hereinafter to describe or details such as the structure of the shown various assemblies of accompanying drawing and arrangement.The present invention can be applied to other embodiment or can put into practice or realize by variety of way.In addition, should be appreciated that phrase used herein and term only are used for describing, and should not be regarded as having restricted.

Fig. 2 a is the high level block diagram that principle according to the present invention is used to realize the network 100 of the POE from switch to a plurality of nodes.Network 100 comprises switch 120, UPS 125, AC main line connection 70, IP phone 130, desk-top computer 140 and laptop computer 145.The AC main line connects 70 and is connected to UPS125, and UPS 125 is used for to switch 120 power supplies.IP phone 130, desk-top computer 140 and laptop computer 145 all are connected to switch 120 by star like arrangement.Switch 120 is supported 6 ports among the figure, yet this does not also mean that by any way and limit, can support more port or less port under the situation that does not surmount scope of the present invention.Switch 120 preferably provides exchanges data and POE according to IEEE 802.3af.The power supply of PoE is also referred to as power supply equipment (PSE).When the AC main supply breaks down, use power supply for PoE by UPS 125.In addition, during the AC main supply broke down, UPS 125 was switch 120 power supplies.In this article, being also referred to as PoE by the PoE power supply connects or the PoE passage.

Fig. 2 b is the high level block diagram that principle according to the present invention is used to realize the network 150 of therefrom cross-module POE to a plurality of nodes.Network 150 comprise switch 160, in stride PSE 170, IP phone 130, desk-top computer 140, laptop computer 145, UPS 125 and the AC main line connects 70.The AC main line connects 70 and is connected to UPS 125, and UPS 125 is used for to switch 160 and strides PSE 170 power supplies.IP phone 130, desk-top computer 140 and laptop computer 145 are striden PSE170 in being connected to star like arrangement.During being connected to, each port of switch 160 strides the corresponding port of power supply equipment 170.

Among the figure switch 160 and in stride PSE 170 and support 6 ports respectively, yet this does not also mean that by any way and limits, can support more port or less port under the situation that does not surmount scope of the present invention.Switch 160 and in stride PSE 170 and do not require the port of supporting equal number.Switch 160 provides exchanges data for nodes that all link to each other, and in stride PSE 170 and preferably provide PoE for nodes that all link to each other according to IEEE 802.3af.When the AC main supply breaks down, by UPS 125 in stride the electric energy that PSE 170 provides PoE to use, also provide and therefrom stride the electric energy that PSE 170 uses to the PoE of the charged node of each PoE.Preferably, during the AC main supply broke down, UPS 125 also was switch 160 power supplies.

Fig. 3 a is that first embodiment of the Computer Architecture of standby power supply is provided by POE is the high level block diagram of architecture 200 to principle according to the present invention.Architecture 200 comprises: PoE shunt and LAN card 210; Optional power supply signature (MPS) function 220 of keeping; Boost converter 230; Holding capacitor 235; PoE checking 240; Power supply selector switch 250; The AC main line connects 70; Power supply 20, it is made of electromagnetic interface filter 260, diode bridge 270, holding capacitor 275 and power supply unit 280, and power supply unit 280 is made of controlled source 282 and standby power 284; CPU and chipset 290, it comprises power-management interface 295; Hard disk drive 300, it comprises cache memory 305; Volatile memory 310; AC proof scheme 320; Phase inverter 330; AND gate 340; AND gate 350; Set-reset flip-floop 360; And interruptable controller 370.

PoE shunt and LAN card 210 are connected to the Ethernet switch (such as the switch 120 of Fig. 2 a) that is used for data communication by communication cable thereby PoE are provided, and perhaps are connected to the switch 160 that is used for providing data communication among Fig. 2 b and are used to provide that PoE's stride PSE 170.PoE shunt and LAN card 210 are described as single card in this article, yet this does not also mean that by any way and limit.Under the situation that does not surmount scope of the present invention, the PoE that describes above with reference to IEEE 802.3af standard function along separate routes can separate from LAN card function.In addition, under the situation that does not surmount scope of the present invention, do not need to provide LAN card function and can transmit PoE by the non-twisted-pair feeder that is effective to transmit data.

Such as known to those skilled in the art, PoE shunt and LAN card 210 one is connected and is connected to data and connects, and this connection comprises that the Physical layer that is called as PHY connects in exemplary embodiment.The power supply output of PoE shunt and LAN card 210 is connected to boost converter 230.Optional MPS function 220 is connected to boost converter 230 with parallel way, and is integrated in typical embodiment within the boost converter 230.The output of boost converter 230 is connected to power supply selector switch 250, and is connected to PoE checking 240 and holding capacitor 235 in parallel.The output of power supply selector switch 250 strides across the input that holding capacitor 275 is connected to power supply unit 280.The output (being labeled as " PoE is good ") of PoE checking 240 is connected to first input of AND gate 340 and first input of AND gate 350.

The AC main line connects 70 and is connected to the electromagnetic interface filter 260 of the input of power supply 20, and is connected to AC proof scheme 320 in parallel.The output of electromagnetic interface filter 260 is connected to the input of diode bridge 270, and the input of crossing over holding capacitor 275 and being connected to power supply unit 280 is exported in the rectification of diode bridge 270.The output of AC proof scheme 320 is connected to second of AND gate 340 by phase inverter 330 and imports, and is also connected to the input that resets of set-reset flip-floop 360.The output of power supply unit 280 (being labeled as " DC is good ") is connected to the 3rd input of AND gate 340, is also connected to second input of AND gate 350, and is also connected to the input of CPU and chipset 290.The output of AND gate 340 is connected to set-reset flip-floop 360 set inputs.The output of set-reset flip-floop 360 (being labeled as " control of power supply selector switch ") is fed to the input of interruptable controller 370, and is fed to the control input of power supply selector switch 250.The output of interruptable controller 370 is fed to the input of CPU and chipset 290, and the output of AND gate 350 is fed to the input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " PS_ON# ") is connected to the remote power feeding control input of power supply unit 280.The power supply of power supply unit 280 output (being labeled as 3.3V, 12V, 5V and 5VSTBY) is shown and is connected to CPU and chipset 290, yet this does not also mean that by any way and limit.These power supply outputs are connected to each element that needs electric energy in the architecture 200 on request.Particularly, no matter the state of PS_ON# how, hard disk drive 300 is connected to 5V and the 12V output that receives power supply unit 280, and volatile memory 310 connects into the electric energy of reception from power supply unit 280.Should be appreciated that passing through under the situation of PS_ON# signal at stop controlled source 282, each equipment that is connected to the 5VSTBY circuit is arranged to receive the electric energy from power supply unit 280, this electric energy is from controller power source 282 or from standby power 284.

CPU described herein and chipset 290 comprise independent power-management interface 295, yet this does not also mean that by any way and limit, and only is in order clearly to carry out functional description.In typical embodiment, power-management interface 295 comprises the power management software function that runs on the operating system on CPU and the chipset 290.In another typical embodiment, this software function comprises ACPI.In typical embodiment, CPU and chipset 290 comprise super I/O chip, can operate to produce the PS_ON# signal.

In the course of the work, PoE shunt and LAN card 210 are provided for the data-interface of architecture 200, and tell electric energy from communication cable.PoE shunt and LAN card 210 preferably further provide appropriate signature impedance, optional classification and disconnector function according to IEEE 802.3af.Optional MPS function 220 guarantees that thereby obtaining enough electric energy by the PoE connection guarantees not cut off the power supply.In typical embodiment, according to IEEE 802.3af standard, when PSE monitored DC MPS component, optional MPS function 220 reduced 10mA at least in being no more than the 75ms minimum duration of losing all after dates of 250ms, guaranteed effective DC MPS composition thus.In another embodiment, above-mentioned PSE only monitors AC MPS component, and optional MPS function 220 is optional.Specified 48 volts of PoE electric energy that boost converter 230 will receive convert the voltage of the input that is fit to power supply unit 280 to.Holding capacitor 235 is stored enough big energy to support electric energy and any moment between the architecture 200 needed electric energy that PoE was provided non-equilibrium, and this can further explain hereinafter.Only when the output of boost converter 230 when being available and stable, PoE checking 240 is the high PoE of output logic " well " signals.Power supply selector switch 250 operationally is connected to the output of boost converter 230 in switchable mode the input of power supply unit 280.

In replacing the embodiment (not shown), PoE shunt and LAN card 210 provide the function of carrying out additional communication with PSE, and this PSE is the PoE power supply.In typical embodiment, transmission is used to represent that PoE connects the information that is used for the standby use, no longer needs the MPS function of choosing wantonly 220 thus.In response to having sent of receiving be used to represent that PoE is used for stand-by information, stride PSE 170 among the switch 120 of Fig. 2 a and Fig. 2 b and enable the PoE standby power supply respectively, and no matter effectively how many DC MPS components is.In another embodiment, in response to the information that receives, exclusively monitor AC MPS component.Further described this communication capacity in the pending U.S. Patent Application of submitting on October 12nd, 2,004 10/961,108 that is entitled as " Powered Device Interface Circuit ", its full content is quoted at this as a reference.

It is filtered by electromagnetic interface filter 260 to connect the AC electric energy that receives 70 from the AC main line, by rectification, makes it level and smooth by holding capacitor 275 by diode bridge 270, and by feed-in power supply unit 280.After electric energy was stable, power supply unit 280 export multiple voltage and is exported DC " well " signal in response to controlled source 282 from controlled source 282 and standby power 284.The AC electric energy monitors that by AC proof scheme 320 this AC proof scheme 320 is used to identify losing of electric energy.In typical embodiment, AC proof scheme 320 monitors the AC voltage waveforms, and when the AC electric energy is good the high signal of output logic, and when the shape that does not have AC waveform or AC waveform is used to represent that electric energy is lost the output logic low signal.In typical embodiment, this be by to the sampling of input AC voltage waveform and the waveform after will sample compare with the reference waveform that is written in advance, sense thus and expect any variation of waveform, thus realization.In one embodiment, the high signal of AC proof scheme 320 output logic within predetermined amount of time is preferably within 4 milliseconds or comparing with reference waveform within 1/4 cycle length that change to surpass 20% input AC voltage waveform.Before second input with the output feed-in AND gate 340 of AC proof scheme 320, phase inverter 330 makes the output of AC proof scheme 320 anti-phase.AND gate 340 is only at DC " well " high signal of output logic just when signal is in logic high, the decay of AC proof scheme 320 indication AC electric energy, and the output of boost converter 230 is available and stable as PoE " well " signal is pointed.Notice that the reason that DC " well " signal presents logic high has following two kinds: even identified after the AC main supply breaks down at AC proof scheme 320, the intrinsic hold-up time of controlled source 282 also can be kept AC " well " signal; Electric energy by power supply selector switch 250 from boost converter 230 feed-in power supply units 280.

The logic high output set set-reset flip-floop 360 of AND gate 340, and the Q of set-reset flip-floop 360 output is by feed-in interruptable controller 370.The output of interruptable controller 370 is interrupted by feed-in CPU and chipset 290 as one.In typical embodiment, this interruption is system management interrupt (SMI).The Q output of set-reset flip-floop 360 further is connected to the control input of power supply selector switch 250 as the power supply selector control signal.In response to this power supply selector control signal, the output of boost converter 230 is by the input of feed-in power supply unit 280.In one embodiment, power supply selector switch 250 comprises OR circuit, the voltage of boost converter 230 is the voltage that is lower than diode bridge 270 two ends when having the AC electric energy by chosen in advance, and power supply selector switch 250 does not need the power supply selector signal as input thus.When the voltage at diode bridge 270 two ends descends, from the low voltage output of boost converter 230, automatically present electric energy.In typical embodiment, boost converter 230 comprises big output holding capacitor 235, because the initial power demand of power supply unit 280 is greater than the power value that receives by PoE passage (this passage comprises PoE shunt and LAN card 210).This causes temporary transient power imbalances, and holding capacitor 235 supports this power imbalances up to this unbalance being resolved, and this will give an explaination hereinafter.

CPU and chipset 290 are in response to interruption that interruptable controller 370 produced and call a routine, this routine be saved in environmental information on the volatile memory 310 and operating power management interface 295 to produce logic high signal about PS_ON#, close the output of controlled source 282 thus.Standby power 284 is still to 5VSTBY output power supply.Power supply unit 280 is less than the power that can obtain by the PoE passage in response to the power demand about the logic high signal of PS_ON#.Thus, the capacitor of boost converter 230 235 is supported above-mentioned temporary transient power imbalances, has proofreaied and correct up to the operation of PS_ON# signal that this is unbalance.

Only as DC " well " when signal presents logic high, AND gate 350 is the high signal of output logics, and the output of boost converter 230 is available with stable as logic high PoE " well " signal is pointed.This input can be utilized by power-management interface 295, thereby can make the user in response to the available PoE that senses based on standby power supply suitable software setting is set.

When the AC main supply is resumed, AC proof scheme 320 senses available AC electric energy and output be used to the to reset logic high signal of set-reset flip-floop 360, this has removed the input of interruptable controller 370, and be scavenged into the interruption of CPU and chipset 290 in response to this interruptable controller 370 of the input that is eliminated, and this point is come sensing by power-management interface 295.Power-management interface 295 in response to interruption that is eliminated and appropriate delay is arranged to logic low with PS_ON#.Controlled source 282 is in response to about the logic low of PS_ON# and the AC main line input voltage in the tolerance limit and export the dc voltage that is used to operate CPU and chipset 290 and other equipment.In the embodiment of replacing, thereby CPU and chipset 290 are pressed power knob in response to the user PS_ON# are made as logic low.Enable all voltage output on request in response to PS_ON# controlled source 282, and further DC " well " signal is made as logic high.CPU and chipset 290 in response to the DC that switches to logic high " well " thus signal and the interruption that before had been eliminated and recover environmental information and start normal running and withdraw from this interruption routine.

Preferably, when recovering, this computing machine begins operate as normal and need not to restart.Just can realize thisly restarting rapidly by storaging state information.

In one embodiment, can provide power backup block, it comprises PoE shunt and LAN card 210, boost converter 230, PoE checking 240, power supply selector switch 250 and AC proof scheme 320.This power backup block can advantageously be added in the existing computing machine, the power backup block that is used for original equipment that perhaps is designed to use separately.

Fig. 4 a shows the timing diagram of the relation between some signal in the architecture of Fig. 3 a, wherein x axle reflection time.Do not attempt to draw in proportion this timing diagram, the distance between the drawn thus variety of event is not passed in all senses.At moment T1, it is stable receiving PoE and detect this PoE by operation PoE checking 240, and PoE " well " signal presents logic high.At moment T2, the AC main supply has been received and has been in the predetermined scope, and the output of AC proof scheme 320 presents logic high.Moment T3 (in typical embodiment, this moment may appear at the user and press after the power knob), DC " well " thus it is available that signal presents the regulated power that logic high points out from controlled source 282.In response to the logic high signal of the input that resets of set-reset flip-floop 360, the power supply selector control signal presents logic low.Under the control of power-management interface 295, PS_ON# (it is effective low signal) presents logic low in this cycle, enable controlled source 282 thus and from the AC main supply to the power supply of all connection devices.

At moment T4, the output of AC proof scheme 320 presents logic low, thereby points out that the AC electric energy is outside preset range.It should be appreciated by those skilled in the art that in prior art systems, after the hold-up time termination that loses AC electric energy controlled source 282, DC " well " signal will present logic low.The logic low output of AC proof scheme 320 is made as logic high with the Q output of set-reset flip-floop 360, and the Q output of set-reset flip-floop 360 is marked as the power supply selector control signal and further is input to interruptable controller 370.As mentioned above, logic high power supply selector control signal can be powered to power supply unit 280 by enough electric energy that receives by PoE, and the interruption that produces CPU and chipset 290.At moment T5, CPU and chipset 290 have been finished and have been stored environmental information into volatile memory 310, and volatile memory 310 will receive the stand-by electric energy from boost converter 230 when the AC main line breaks down.Power-management interface 295 is made as logic high with PS_ON#, and all output powers of controlled source unit 282 are descended.In one embodiment, power-management interface 295 is further closed various device, thereby they is made as sleep or park mode before PS_ON# is made as logic high.In typical embodiment, close heat radiation (CPU) fan.PS_ON# is made as this way of logic high to be reduced to the power demand of architecture 200 to be less than or equal to the value that can obtain by the PoE passage from boost converter 230.At T6, be set as logic high in response to the PS_ON# signal, DC " well " signal becomes logic low, thereby points out from the DC of controlled source 282 electric energy no longer availablely, and the electric energy from standby power 284 is only arranged is available.

Be appreciated that when DC " well " when signal presents logic high architecture 200 to CPU and chipset 290 interruption is set, the AC validation signal presents logic low, and PoE " well " signal presents logic high.Thus, this interruption reflects that controlled source unit 282 provides effective output, and standby power supply is available, and AC checking 320 has sensed the AC main supply and is in outside the preset range.Shown in moment T7, when AC checking 320 points out that the AC main supply is within the predetermined scope, just above-mentioned interruption is through with.The power supply selector control signal becomes logic low, thereby has made the End of Interrupt of CPU and chipset 290, and the output of boost converter 230 is connected with the input disconnection of power supply unit 280.Preferably, before being disconnected connection, the output of boost converter 230 allowing to realize that above-mentioned disconnection connects after the AC electric energy increases to that section delay of input of power supply unit 280.Be embedded in the embodiment of OR circuit (the shared arrangement such as diode) at power supply selector switch 250, this is the automatic result of effective AC electric energy of occurring in the input of power supply unit 280.At moment T8, power supply unit 280 provides the dc voltage through regulating on request, and CPU and chipset 290 hereinafter recover environmental information with the mode of explaining and work on a kind of in response to above-mentioned End of Interrupt.

Fig. 3 b is that second embodiment of the Computer Architecture of standby power supply is provided by POE is the high level block diagram of architecture 400 to principle according to the present invention.Architecture 400 comprises: PoE shunt and LAN card 210; Optional electric energy signature (MPS) function 220 of keeping; Boost converter 230; Holding capacitor 235; PoE checking 240; Power supply selector switch 250; The AC main line connects 70; Power supply 20, this power supply 20 comprises electromagnetic interface filter 260, diode bridge 270, holding capacitor 275 and power supply unit 280, this power supply unit 280 comprises controlled source 282 and standby power 284; CPU and chipset 290, it comprises power-management interface 295; Hard disk drive 300, it comprises cache memory 305; Volatile memory 310; AC proof scheme 320; Phase inverter 330; AND gate 340; AND gate 350; And interruptable controller 370.

Such as known to those skilled in the art, PoE shunt and LAN card 210 one is connected and is connected to data and connects, and this connection comprises that the Physical layer that is called as PHY connects in exemplary embodiment.The power supply output of PoE shunt and LAN card 210 is connected to boost converter 230 and is connected to optional MPS function 220 in parallel.In typical embodiment, optional MPS function 220 is integrated within the boost converter 230.The output of boost converter 230 is connected to power supply selector switch 250, and is connected to PoE checking 240 and holding capacitor 235 in parallel.The output of power supply selector switch 250 is connected to the input of power supply unit 280.The output (being labeled as " PoE is good ") of PoE checking 240 is connected to first input of AND gate 340 and first input of AND gate 350.

The AC main line connects 70 and is connected to the electromagnetic interface filter 260 of the input of power supply 20, and is connected to AC proof scheme 320 in parallel.The output of electromagnetic interface filter 260 is connected to the input of diode bridge 270, and the input of crossing over holding capacitor 275 and being connected to power supply unit 280 is exported in the rectification of diode bridge 270.The output of AC proof scheme 320 is connected to second input of AND gate 340 by phase inverter 330.The output of power supply unit 280 (being labeled as " DC is good ") is connected to the 3rd input of AND gate 340, is connected to second input of AND gate 350, and is also connected to the input of CPU and chipset 290.The output of AND gate 340 (being labeled as " control of power supply selector switch ") is fed to the input of interruptable controller 370, and is fed to the control input of power supply selector switch 250.The output of interruptable controller 370 is fed to the input of CPU and chipset 290, and the output of AND gate 350 is fed to the independent input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " device power supply (DPS) control ") is comprised the power supply control input of all connection device (not shown) of hard disk drive 300 by feed-in.The output of CPU and chipset 290 (being labeled as " PS_ON# ") is connected to the remote power feeding control input of power supply unit 280.The power supply of power supply unit 280 output (being labeled as 3.3V, 12V, 5V and 5VSTBY) is shown and is connected to CPU and chipset 290, yet this does not also mean that by any way and limit.These power supply outputs are connected to each element that needs electric energy in the architecture 400 on request.Particularly, no matter the state of PS_ON# how, hard disk drive 300 is connected to the 5V and the 12V output of receiving slave power supply unit 282, and volatile memory 310 connects into the electric energy of reception from power supply unit 280.Should be appreciated that passing through under the situation of PS_ON# signal at stop controlled source 282, each equipment that is connected to the 5VSTBY circuit is arranged to receive the electric energy from power supply unit 280, this electric energy is from controlled source 282 or from standby power 284.

CPU described herein and chipset 290 comprise independent power-management interface 295, yet this does not also mean that by any way and limit, and only is in order clearly to carry out functional description.In typical embodiment, power-management interface 295 comprises the power management software function that runs on the operating system on CPU and the chipset 290.In another typical embodiment, this software function comprises ACPI.In typical embodiment, CPU and chipset 290 comprise super I/O chip, can operate to be used to produce the PS_ON# signal.

In the course of the work, PoE shunt and LAN card 210 are provided for the data-interface of architecture 400, and tell electric energy from communication cable.PoE shunt and LAN card 210 preferably further provide appropriate signature impedance, optional classification and disconnector function according to IEEE 802.3af.Optional MPS function 220 guarantees that thereby obtaining enough electric energy by the PoE connection guarantees not cut off the power supply.In typical embodiment, according to IEEE 802.3af standard, when PSE monitored DC MPS component, optional MPS function 220 reduced 10mA at least in being no more than the 75ms minimum duration of losing all after dates of 250ms, guaranteed effective DC MPS composition thus.In another embodiment, above-mentioned PSE only monitors AC MPS component, and optional MPS function 220 is optional.Specified 48 volts of PoE electric energy that boost converter 230 will receive convert the voltage of the input that is fit to power supply unit 280 to.Holding capacitor 235 is stored enough big energy to support electric energy and any moment between the architecture 400 needed electric energy that PoE was provided non-equilibrium, and this can further explain hereinafter.Only when the output of boost converter 230 when being available and stable, PoE checking 240 is the high PoE of output logic " well " signals.Power supply selector switch 250 operationally is connected to the output of boost converter 230 in switchable mode the input of power supply unit 280.

It is filtered by electromagnetic interface filter 260 to connect the AC electric energy that receives 70 from the AC main line, by rectification, makes it level and smooth by holding capacitor 275 by diode bridge 270, and by feed-in power supply unit 280.After electric energy was stable, power supply unit 280 was exported multiple voltage and in response to DC " well " signal of controlled source 282 from controlled source 282 and standby power 284.Only in response to the logic low input (may be to produce by the power supply (not shown) that the user presses on the switch) about PS_ON#, controlled source 282 is output voltage.The AC electric energy monitors that by AC proof scheme 320 this AC proof scheme 320 is used to identify the decay of electric energy.In typical embodiment, AC proof scheme 320 monitors the AC voltage waveforms, and when AC electric energy " well " the high signal of output logic, output logic low signal then when the shape that does not have AC waveform or AC waveform represents that electric energy has been decayed.In typical embodiment, this is to compare with the reference waveform that is written in advance by the waveform after input AC voltage waveform is sampled and will be sampled to realize, detects any variation for the expection waveform thus.In one embodiment, the high signal of AC proof scheme 320 output logic within predetermined amount of time is preferably within 4 milliseconds or comparing with reference waveform within 1/4 cycle length that change to surpass 20% input AC voltage waveform.Before second input with the output feed-in AND gate 340 of AC proof scheme 320, phase inverter 330 makes the output of AC proof scheme 320 anti-phase.AND gate 340 is the high signal of ability output logic when having DC " well " signal only, the decay of AC proof scheme 320 indication AC electric energy, and the output of boost converter 230 is available and stable as PoE " well " signal that presents logic high is pointed.Notice that the reason that DC " well " signal presents logic high has following two kinds:, also can keep AC " well " signal in the intrinsic hold-up time of controlled source 282 even identified after the AC main supply breaks down at AC proof scheme 320; Perhaps since electric energy by power supply selector switch 250 from boost converter 230 feed-in power supply units 280.

The logic high output of AND gate 340 is by feed-in interruptable controller 370, and interruptable controller 370 is translated into interrupt event with the rising edge or the logic high of the output of AND gate 340.The output of interruptable controller 370 is interrupted by feed-in CPU and chipset 290 as one.In typical embodiment, this interruption is system management interrupt (SMI).The output of AND gate 340 further is connected to the control input of power supply selector switch 250 as the power supply selector control signal.In response to this power supply selector control signal, the output of boost converter 230 is by the input of feed-in power supply unit 280.In one embodiment, power supply selector switch 250 comprises OR circuit, the voltage of boost converter 230 is the voltage that is lower than diode bridge 270 two ends when having the AC electric energy by chosen in advance, and power supply selector switch 250 does not need the power supply selector signal as input thus.When the voltage at diode bridge 270 two ends descends, from the low voltage output of boost converter 230, automatically present electric energy.In typical embodiment, boost converter 230 comprises big output holding capacitor 235, because the initial power demand of power supply unit 280 is greater than the power value that receives by PoE passage (this passage comprises PoE shunt and LAN card 210).This causes temporary transient power imbalances, and holding capacitor 235 supports this power imbalances up to this unbalance being resolved, and this will give an explaination hereinafter.

CPU and chipset 290 be in response to interruption that interruptable controller 370 produced and call a routine, each connection device is placed reduces power mode thereby this routine is saved in environmental information on the volatile memory 310 and next move this device power supply (DPS) control signal by power-management interface 295.Preferably, this reduces power mode is sleep pattern, has wherein preserved facility environment.When CPU and chipset 290 store facility environment on the volatile memory 310, this equipment can be placed closed condition to save extra electric energy.In response to being placed in above-mentioned each connection device that reduces in the power mode, the power demand of architecture 400 is less than or equal to the power that can obtain by the PoE passage.Operating power management interface 295 can be used up some times with the power demand that reduces all connection devices, and the capacitor 235 of boost converter 230 provides required electric energy for temporary transient power imbalances, thereby unbalance up to proofreaied and correct this by the power demand that successfully reduces connection device.Should be appreciated that, CPU and chipset 290 in response to power-management interface 295 to move on to standby low power mode.Notice that in the above-described embodiment, DC " well " signal remains positive, because power supply unit 280 receives from the AC main line or from the input electric energy of boost converter 230 when the AC fault occurring.In typical embodiment, do not require that controlled source 282 power descend.

When the AC main supply was resumed, AC proof scheme 320 sensed available AC electric energy and output by the anti-phase logic high signal of phase inverter 330, and the output with AND gate 340 becomes logic low thus, and then has removed the input of interruptable controller 370.In response to the input that is eliminated, this interruptable controller 370 has been removed the interruption of CPU and chipset 290, and this comes sensing by power-management interface 295.Power-management interface 295 in response to the interruption that is eliminated and appropriate delay (this delay allows controlled source 282 to restart) thus and recover above-mentioned environmental information and make it possible to normal running and withdraw from this interruption routine.In typical embodiment, power-management interface 295 confirms that PS_ON# has been set as logic low before making it possible to normal running.Advantageously, do not need computing machine to restart, normal running is just continued.

Fig. 4 b shows the timing diagram of the relation between some signal in the architecture 400 of Fig. 3 b, wherein the x axle reflection time.Do not attempt to draw in proportion this timing diagram, the distance between the drawn thus variety of event is not passed in all senses.At moment T11, the operation by PoE checking 240 receives PoE and detects this PoE is stable, and PoE " well " signal presents logic high.At moment T12, the AC main supply has been received and has been in the predetermined scope, and the output of AC proof scheme 320 presents logic high.Moment T13 (in typical embodiment, this moment may appear at the user and press after the power knob), DC " well " thus it is available that signal presents the regulated power that logic high points out from controlled source 282.In response to the logic high output of AC proof scheme 320, the power supply selector control signal presents logic low.

At moment T14, the output of AC proof scheme 320 presents logic low, thereby points out that the AC electric energy is outside preset range.It should be appreciated by those skilled in the art that in prior art systems, after losing AC electric energy power supply 20 particularly the hold-up time of controlled source 282 stops, DC " well " signal will present logic low.The output of the logic low of AC proof scheme 320 by phase inverter 330 anti-phase and by AND gate 340 as the logic high input by feed-in interruptable controller 370.As mentioned above, logic high power supply selector control signal makes it possible to use the electric energy that receives by PoE to power supply unit 280 power supplies, and the interruption that produces CPU and chipset 290.At moment T15, CPU and chipset 290 have been finished and have been stored environmental information into volatile memory 310, and volatile memory 310 will receive from boost converter 230 and the electric energy by power-management interface 295, and relevant device power supply (DPS) control signal begins to reduce total power demand.At moment T16, total power demand has been reduced to and has been equal to or less than the power that can obtain by boost converter 230 from the PoE passage.In one embodiment, CPU and chipset 290 all store all environmental informations into volatile memory 310, and in another embodiment, when keeping environment, all equipment all is placed in its lowest power state.The high-speed cache 305 of hard disk drive 300 remains in the low power state, and receives the electric energy from power supply unit 280.In another embodiment, power-management interface 295 is further closed various device, and they are made as sleep or park mode.In a typical embodiment, closed heat radiation (CPU) fan at moment T16.

Be appreciated that architecture 400 is provided with an interruption to CPU and chipset 290 as DC " well " when signal presents logic high, the AC validation signal presents logic low, and PoE " well " signal presents logic high.Thus, this interruption reflects that controlled source unit 282 provides effective output, and standby power supply is available, and AC checking 320 has sensed AC main supply power and is in outside the preset range.Shown in moment T17, when AC checking 320 points out that the AC main supply is within the predetermined scope, just above-mentioned interruption is through with.The power supply selector control signal becomes logic low, thereby has made the End of Interrupt of CPU and chipset 290, and the output of boost converter 230 is connected with the input disconnection of power supply unit 280.Preferably, before the output of boost converter 230 is disconnected connection, allowing to realize that above-mentioned disconnection connects after the AC electric energy increases to that section delay of input of power supply unit 280.Be embedded in the embodiment of OR circuit (shared the arranging such as diode) at power supply selector switch 250, this is the automatic result of effective AC electric energy of occurring in the input of power supply unit 280.CPU and chipset 290 be in response to this End of Interrupt, after one section suitable delay that the electric energy that allows to connect from the AC main line 70 increases, hereinafter the mode of explaining recovered environmental information and work on a kind of.Advantageously, do not need to restart, CPU and chipset 290 just work on.

Fig. 3 c is that the 3rd embodiment of the Computer Architecture of standby power supply is provided by POE is the high level block diagram of architecture 450 to principle according to the present invention.Architecture 450 comprises: PoE shunt and LAN card 210; Optional power supply signature (MPS) function 220 of keeping; Holding capacitor 235; PoE checking 240; DC/DC converter 410; OR circuit 420; The AC main line connects 70; Power supply 20, power supply 20 is made of electromagnetic interface filter 260, diode bridge 270, holding capacitor 275 and power supply unit 280, and power supply unit 280 is made of controlled source 282 and standby power 284; CPU and chipset 290, it comprises power-management interface 295; Hard disk drive 300, it comprises cache memory 305; Volatile memory 310; AC proof scheme 320; Phase inverter 330; AND gate 340; AND gate 350; Set-reset flip-floop 360; And interruptable controller 370.

Such as known to those skilled in the art, PoE shunt and LAN card 210 one is connected and is connected to data and connects, and in exemplary embodiment, this connection comprises that the Physical layer that is called as PHY connects.The power supply output of PoE shunt and LAN card 210 is connected to DC/DC converter 410 and is connected to optional MPS function 220, PoE checking 240 and holding capacitor 235 in parallel.In exemplary embodiment, optional MPS function 220 is integrated in the DC/DC converter 410.The output of DC/DC converter 410 is connected to each voltage output of standby power supply unit 280 by each OR circuit 420 (depict as " or " diode) herein, and this will further describe hereinafter.The output (being labeled as " PoE is good ") of PoE checking 240 is connected to first input of AND gate 340 and first input of AND gate 350.

The AC main line connects 70 and is connected to the electromagnetic interface filter 260 of the input of power supply 20, and is connected to AC proof scheme 320 in parallel.The output of electromagnetic interface filter 260 is connected to the input of diode bridge 270, and the input of crossing over holding capacitor 275 and being connected to power supply unit 280 is exported in the rectification of diode bridge 270.The output of AC proof scheme 320 is connected to second input of AND gate 340 by phase inverter 330.The output of power supply unit 280 (being labeled as " DC is good ") is connected to the 3rd of AND gate 340 and imports, imports to second of AND gate 350, and is also connected to the input of CPU and chipset 290.The output of AND gate 340 is connected to the set input of set-reset flip-floop 360, and the Q of set-reset flip-floop 360 output (being labeled as " control of power supply selector switch ") is connected to the input of interruptable controller 370, and is connected to the control input of DC/DC converter 410 in parallel.The output of interruptable controller 370 is fed to the input of CPU and chipset 290, and the output of AND gate 350 is fed to an independent input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " device power supply (DPS) control ") is fed to the power supply control input of all connection device (not shown) that comprise hard disk drive 300.The output of CPU and chipset 290 (being labeled as " PS_ON# ") is connected to the remote power feeding control input of power supply unit 280.The power supply of power supply unit 280 output (being labeled as 3.3V, 12V, 5V and 5VSTBY) is shown and is connected to CPU and chipset 290, yet this does not also mean that by any way and limit.These power supply outputs are connected to each element that needs electric energy in the architecture 450 on request.Particularly, no matter in one embodiment how from the state of the PS_ON# signal of standby power 284, hard disk drive 300 is connected to the 5V and the 12V output of receiving slave power supply unit 282, and volatile memory 310 connects into the electric energy of reception from power supply unit 280.Should be appreciated that passing through under the situation of PS_ON# signal at stop controlled source 282, each equipment that is connected to the 5VSTBY circuit is arranged to receive the electric energy from power supply unit 280, this electric energy is from controller power source 282 or from standby power 284.

In the course of the work, PoE shunt and LAN card 210 are provided for the data-interface of architecture 450, and tell electric energy from communication cable.PoE shunt and LAN card 210 preferably further provide appropriate signature impedance, optional classification and disconnector function according to IEEE 802.3af.Optional MPS function 220 guarantees that thereby obtaining enough electric energy by the PoE connection guarantees not cut off the power supply.In typical embodiment, according to IEEE 802.3af standard, when PSE monitored DC MPS component, optional MPS function 220 reduced 10mA at least in being no more than the 75ms minimum duration of losing all after dates of 250ms, guaranteed effective DC MPS composition thus.In another embodiment, above-mentioned PSE only monitors AC MPS component, and optional MPS function 220 is optional.In practice, DC/DC converter 410 can be designed to include MPS function 220, and does not therefore need independent MPS function.Specified 48 volts of PoE electric energy that DC/DC converter 410 will receive convert the voltage of each the voltage output that is suitable for standby power unit 280 to.Holding capacitor 235 is stored enough big energy to support electric energy and any moment between the architecture 450 needed electric energy that PoE was provided non-equilibrium, and this will further explain hereinafter.When the PoE electric energy that is input to DC/DC converter 410 when being available and stable, PoE checking 240 is the high PoE of output logic " well " signals.The power supply selector control signal can be used for opening DC/DC converter 410 so that output fully.In typical embodiment, the power supply selector control signal is as the input of DC/DC converter 410, thereby and DC/DC converter 410 increase its power supply in response to the electric energy of the increase that obtains by OR circuit 420 and export.

In replacing the embodiment (not shown), PoE shunt and LAN card 210 provide the function of carrying out additional communication with PSE, and this PSE is the PoE power supply.In typical embodiment, transmission is used to represent that PoE connects the information that is used for the standby use, no longer needs the MPS function of choosing wantonly 220 thus.In response to having sent of receiving be used to represent that PoE is used for stand-by information, stride PSE 170 among the switch 120 of Fig. 2 a and Fig. 2 b and enable the PoE standby power supply respectively, and no matter effectively how many DC MPS components is.In another embodiment, in response to the information that receives, exclusively monitor AC MPS component.Further described this communication capacity in the pending U.S. Patent Application 10/961,108 that is entitled as " Powered Device InterfaceCircuit " that submit to the 12 days October in 2004 of formerly quoting.

It is filtered by electromagnetic interface filter 260 to connect the AC electric energy that receives 70 from the AC main line, by rectification, makes it level and smooth by holding capacitor 275 by diode bridge 270, and by feed-in power supply unit 280.After electric energy was stable, power supply unit 280 was exported multiple voltage and in response to DC " well " signal of controlled source 282 from controlled source 282 and standby power 284.Only in response to the logic low input (may be to produce by the power supply (not shown) that the user presses on the switch) about PS_ON#, controlled source 282 is output voltage.AC power supplies monitors that by AC proof scheme 320 this AC proof scheme 320 is used to identify the decay of power supply.In typical embodiment, AC proof scheme 320 monitors the AC voltage waveforms, and when AC power supplies is good the high signal of output logic, output logic low signal then when the shape that does not have AC waveform or AC waveform is represented the power supply decay.In typical embodiment, this is to compare with the reference waveform that is written in advance by the waveform after input AC voltage waveform is sampled and will be sampled to realize, detects any variation of relative expection waveform thus.In one embodiment, the high signal of AC proof scheme 320 output logic within predetermined amount of time is preferably within 4 milliseconds or comparing with reference waveform within 1/4 cycle length that change to surpass 20% input AC voltage waveform.Before following output after anti-phase was connected to second input of AND gate 340, phase inverter 330 made the output of AC proof scheme 320 anti-phase.AND gate 340 is the high signal of ability output logic when having DC " well " signal only, the decay of AC proof scheme 320 indication AC electric energy, and as PoE " well " signal that presents logic high pointed, PoE can be used for supporting the operation of DC/DC converter 410.Notice, DC " well " signal may present logic high when the input AC power supplies breaks down, even because identified after the AC main supply breaks down at AC proof scheme 320, particularly the intrinsic hold-up time of controlled source 282 also can be kept AC " well " signal to power supply 20.

The logic high of AND gate 340 output set set-reset flip-floop 360 makes Q output the becoming logic high of set-reset flip-floop 360.The Q output of set-reset flip-floop 360 is by feed-in interruptable controller 370, and interruptable controller 370 is translated into interrupt event with the rising edge or the logic high of above-mentioned Q output.The output of interruptable controller 370 is interrupted by feed-in CPU and chipset 290 as one.In typical embodiment, this interruption is system management interrupt (SMI).The Q output of set-reset flip-floop 360 further is connected to the control input of DC/DC converter 410 as the power supply selector control signal.In one embodiment, in response to above-mentioned logic high power supply selector control signal, DC/DC converter 410 is set as provides whole electric energy.In another embodiment, DC/DC converter 410 is set as the voltage higher a little than the specified output of power supply unit 280, when the output of power supply unit 280 descends, automatically power thus, and DC/DC converter 410 does not need above-mentioned power supply selector control signal as input thus by OR circuit 420.In typical embodiment, holding capacitor 235 has relatively large value, with the power demand of each equipment and any temporary transient power imbalances between the power that can obtain from PoE passage (this passage comprises PoE shunt and LAN card 210) in the reply architecture 450.

CPU and chipset 290 are in response to interruption that interruptable controller 370 produced and call a routine, this routine is saved in environmental information on the volatile memory 310 and next and operates the said equipment power control signal by power-management interface 295, reduces power mode so that each connection device placed.Preferably, this reduces power mode is sleep pattern, has wherein preserved facility environment.When CPU and chipset 290 store facility environment on the volatile memory 310, this equipment can be placed closed condition to save extra electric energy.In response to being placed in above-mentioned each connection device that reduces in the power mode, the power demand of architecture 450 is less than or equal to the power that can obtain by the PoE passage.Some times that operating power management interface 295 can be used up limited with the power demand that reduces all connection devices, and the temporary transient power imbalances of capacitor 235 supports, unbalance up to proofreaied and correct this by the power demand that successfully reduces connection device.Should be appreciated that, CPU and chipset 290 in response to power-management interface 295 to transfer to standby low power mode.Notice that in the above-described embodiment, after the AC main line broke down, power supply unit 280 quit work, and DC " well " signal becomes logic low.

Only as DC " well " when signal presents logic high, AND gate 350 is the high signal of output logics, and as logic high PoE " well " signal is pointed, and the output of DC/DC converter 410 is available with stable.This input can be utilized by power-management interface 295, thereby can make the user in response to the standby power supply that senses based on available PoE suitable software setting is set.

When the AC main supply was resumed, AC proof scheme 320 sensed available AC power supplies, and output is by the anti-phase logic high signal of phase inverter 330, and the output with AND gate 340 becomes logic low thus, thereby has removed the input of interruptable controller 370.In response to the input that is eliminated, this interruptable controller 370 has been removed the interruption of CPU and chipset 290, and this point is come sensing by power-management interface 295.In response to the power-management interface 295 set PS_ON# signals of interruption that is eliminated and appropriate delay to enable controlled source 282, and in response to the logic high DC " well " that receives thus signal storage environment information and enable normal running and then withdraws from above-mentioned interruption routine.In another embodiment, need the user to import (such as pressing the power knob (not shown)) and restart controlled source 282.Advantageously, do not need to restart, CPU and chipset 290 just work on.

Fig. 4 c shows the timing diagram of the relation between some signal in the architecture 450 of Fig. 3 c, wherein the x axle reflection time.Do not attempt to draw in proportion this timing diagram, the distance between the drawn thus variety of event is not passed in all senses.At moment T21, it is stable receiving PoE and detect this PoE by operation PoE checking 240, and PoE " well " signal presents logic high.At moment T22, the AC main supply has been received and has been in the predetermined scope, and the output of AC proof scheme 320 presents logic high.Moment T23 (in typical embodiment, this moment may appear at the user and press after the power knob), DC " well " signal becomes positive, thereby the stabilized power source of pointing out from controlled source 282 is available.In response to the logic high output of AC proof scheme 320, the power supply selector control signal presents logic low.

At moment T24, the output of AC proof scheme 320 presents logic low, thereby points out that AC power supplies is outside preset range.It should be appreciated by those skilled in the art that in prior art systems, after losing AC power supplies, after particularly the hold-up time of controlled source 282 stops, DC " well " signal will become negative at power supply 20.The output of the logic low of AC proof scheme 320 is anti-phase and carry out feed-in so that set set-reset flip-floop 360 by AND gate 340 by phase inverter 330, and the Q of set-reset flip-floop 360 output is imported as logic high by feed-in interruptable controller 370, and next interruptable controller 370 produces an interruption to CPU and chipset 290.At moment T25, CPU and chipset 290 have been finished and have been stored environmental information into volatile memory 310, and volatile memory 310 will receive the electric energy from DC/DC converter 410, and power-management interface 295 begins to reduce total power demand by the relevant device power control signal.In another embodiment, at moment T25, thereby CPU and chipset 290 particularly power management interface 295 started by placing standby mode to reduce the process of power demand each equipment.At moment T26, power supply 20 particularly the hold-up time of controlled source 282 stop, and DC " well " signal presents logic low.Be noted that this moment, by 410 power supplies of DC/DC converter, exceeding simultaneously all just to be provided by holding capacitor 235 by any temporary transient power demand that the PoE passage obtains.

At moment T27, total power demand be reduced to be equal to or less than can by PoE shunt and LAN card 210 from PoE be connected or passage the power that obtains.In one embodiment, CPU and chipset 290 all store all environmental informations into volatile memory 310, and in another embodiment, when keeping environment, all equipment all is placed in its lowest power state.The high-speed cache 305 of hard disk drive 300 still is in the low power state, and by the electric energy of OR circuit 420 receptions from DC/DC converter 410.In another embodiment, power-management interface 295 is further closed various device, and they are made as sleep or park mode.In typical embodiment,, closed heat radiation (CPU) fan at moment T27.

Be appreciated that when DC " well " when signal presents logic high architecture 450 to CPU and chipset 290 interruption is set, the AC validation signal presents logic low, and PoE " well " signal presents logic high.Thus, this interruption reflects that controlled source unit 282 has provided effective output, and standby power supply is available, and AC checking 320 has sensed the AC main supply and is in outside the preset range.Shown in moment T28, when AC checking 320 pointed out that the AC main supply is within the predetermined scope, just above-mentioned interruption is through with, set-reset flip-floop 360 thus resetted.The power supply selector control signal becomes and presents logic low, thereby has made the End of Interrupt of CPU and chipset 290, and has reduced the output of DC/DC converter 410 in one embodiment.Preferably, before the output that reduces DC/DC converter 410, allowing to realize above-mentioned reducing after AC power supplies increases to that section delay of input of power supply unit 280.In another embodiment, in response to from the reappearing of power supply unit 280 specified outputs, the output of DC/DC converter 410 that is connected to each output of power supply unit 280 by OR circuit 420 has reduced its each output.CPU and chipset 290 be in response to this End of Interrupt, after one section suitable delay that the electric energy that allows to connect from the AC main line 70 increases, hereinafter the mode of explaining recovered environmental information and work on a kind of.

Fig. 3 d is that the 4th embodiment of the Computer Architecture of standby power supply is provided by POE is the high level block diagram of architecture 500 to principle according to the present invention.Architecture 500 comprises: PoE shunt and LAN card 210; Optional power supply signature (MPS) function 220 of keeping; Holding capacitor 235; PoE checking 240; DC/DC converter 410; OR circuit 420; The AC main line connects 70; Power supply 20, power supply 20 is made of electromagnetic interface filter 260, diode bridge 270, holding capacitor 275 and power supply unit 280, and power supply unit 280 is made of controlled source 282 and standby power 284; CPU and chipset 290, it comprises power-management interface 295; Hard disk drive 300, it comprises cache memory 305; Volatile memory 310; Phase inverter 330; AND gate 350; Interruptable controller 370; And power knob 510.

PoE shunt and LAN card 210 are connected to the Ethernet switch (such as the switch 120 of Fig. 2 a) that is used for data communication by communication cable thereby PoE are provided, and perhaps are connected to the switch 160 that is used for providing data communication among Fig. 2 b and are used to provide that PoE's stride PSE 170.PoE shunt and LAN card 210 are described as single card in this article, yet this does not also mean that by any way and limit.Under the situation that does not surmount scope of the present invention, the PoE that describes above with reference to IEEE 802.3af standard function along separate routes can separate from LAN card function.In addition, under the situation that does not surmount scope of the present invention, not requiring provides LAN card function and can transmit PoE by the non-twisted-pair feeder that is effective to transmit data.

Such as known to those skilled in the art, PoE shunt and LAN card 210 one is connected and is connected to data and connects, and in exemplary embodiment, this connection comprises that the Physical layer that is called as PHY connects.The power supply output of PoE shunt and LAN card 210 is connected to DC/DC converter 410 and is connected to optional MPS function 220, PoE checking 240 and holding capacitor 235 in parallel.In exemplary embodiment, optional MPS function 220 is integrated in the DC/DC converter 410.The output of DC/DC converter 410 is connected to each voltage output of standby power supply unit 280 by each OR circuit 420 (depict as " or " diode) herein, and this will be described hereinafter.The output (being labeled as " PoE is good ") of PoE checking 240 is connected to first input of AND gate 350.

AC main line connection 70 is connected to the electromagnetic interface filter 260 of the input of power supply 20.The output of electromagnetic interface filter 260 is connected to the input of diode bridge 270, and the input of crossing over holding capacitor 275 and being connected to power supply unit 280 is exported in the rectification of diode bridge 270.The output of the controlled source unit 282 of power supply unit 280 (being labeled as " DC is good ") is connected to second input of AND gate 350, and is also connected to the input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " PS_ON# ") is connected to the remote power feeding control input of power supply unit 280.The output of AND gate 350 is connected to the input of CPU and chipset 290 and is connected to the input of interruptable controller 370 and the control input of DC/DC converter 410 by phase inverter 330.The output of interruptable controller 370 is fed to an independent input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " device power supply (DPS) control ") is fed to the power supply control input of all connection device (not shown) that comprise hard disk drive 300.The power supply of power supply unit 280 output (being labeled as 3.3V, 12V, 5V and 5VSTBY) is shown and is connected to CPU and chipset 290, yet this does not also mean that by any way and limit.These power supply outputs are connected to each element that needs electric energy in the architecture 500 on request.Particularly, no matter in one embodiment how from the state of the PS_ON# signal of standby power 284, hard disk drive 300 is connected to the 5V and the 12V output of receiving slave power supply unit 282, and volatile memory 310 connects into the electric energy of reception from power supply unit 280.Should be appreciated that passing through under the situation of PS_ON# signal at stop controlled source 282, each equipment that is connected to the 5VSTBY circuit is arranged to receive the electric energy from power supply unit 280, this electric energy is from controller power source 282 or from standby power 284.

In the course of the work, PoE shunt and LAN card 210 are provided for the data-interface of architecture 500, and tell electric energy from communication cable.PoE shunt and LAN card 210 preferably further provide appropriate signature impedance, optional classification and disconnector function according to IEEE 802.3af.Optional MPS function 220 guarantees that thereby obtaining enough electric energy by the PoE connection guarantees not cut off the power supply.In typical embodiment, according to IEEE 802.3af standard, when PSE monitored DC MPS component, optional MPS function 220 reduced 10mA at least in being no more than the 75ms minimum duration of losing all after dates of 250ms, guaranteed effective DC MPS composition thus.In another embodiment, above-mentioned PSE only monitors AC MPS component, and optional MPS function 220 is optional.In one embodiment, DC/DC converter 410 can be designed to include MPS function 220, no longer requires independent MPS function thus.Specified 48 volts of PoE electric energy that DC/DC converter 410 will receive convert the voltage of each the voltage output that is suitable for standby power unit 280 to.Holding capacitor 235 is stored enough big energy to support electric energy and any moment between the architecture 500 needed electric energy that PoE was provided non-equilibrium, and this can further explain hereinafter.When the PoE electric energy that is input to DC/DC converter 410 when being available and stable, PoE checking 240 is the high PoE of output logic " well " signals.The power supply selector control signal can be used as the input of DC/DC converter 410, thereby and DC/DC converter 410 increase its power supply output in response to the electric energy of the increase that obtains by OR circuit 420.

In replacing the embodiment (not shown), PoE shunt and LAN card 210 provide the function of carrying out additional communication with PSE, and this PSE is the PoE power supply.In typical embodiment, transmission is used to represent that PoE connects the information that is used for the standby use, no longer needs the MPS function of choosing wantonly 220 thus.In response to having sent of receiving be used to represent that PoE is used for stand-by information, stride PSE 170 among the switch 120 of Fig. 2 a and Fig. 2 b and enable the PoE standby power supply respectively, and no matter effectively how many DC MPS components is.In another embodiment, in response to the information that receives, exclusively monitor AC MPS component.What formerly be cited has further described this communication capacity in the pending U.S. Patent Application of submitting on October 12nd, 2,004 10/961,108 that is entitled as " Powered Device InterfaceCircuit ".

It is filtered by electromagnetic interface filter 260 to connect the AC electric energy that receives 70 from the AC main line, by rectification, makes it level and smooth by holding capacitor 275 by diode bridge 270, and by feed-in power supply unit 280.After electric energy was stable, power supply unit 280 was exported multiple voltage and in response to DC " well " signal of controlled source 282 from controlled source 282 and standby power 284.Only in response to the logic low input (may be to produce by the power supply (not shown) that the user presses on the switch) about PS_ON#, controlled source 282 is output voltage.AND gate 350 is only at DC " well " high signal of output logic just when signal presents logic high, and as PoE " well " signal that presents logic high was pointed, PoE can be used for supporting the operation of DC/DC converter 410.Notice that DC " well " signal can be after the AC main supply breaks down presents logic high in very short time cycle, this is because of power supply 20 particularly due to intrinsic hold-up time of controlled source 282.

When AC power supplies broke down, after any intrinsic hold-up time had stopped, DC " well " signal presented logic low, and thus, the output of AND gate 350 presents logic low.In one embodiment, the pull down resistor (not shown) guarantees that logic low appears at the input of AND gate 350 under the situation that does not have effective DC " well " signal.The output of AND gate 350 is fed to the input of interruptable controller 370 by phase inverter 330, and interruptable controller 370 is translated into interrupt event with logic high output or its rising edge of phase inverter 330.The output of interruptable controller 370 is interrupted by feed-in CPU and chipset 290 as one.In typical embodiment, this interruption is system management interrupt (SMI).The output of phase inverter 330 further is connected to the control input of DC/DC converter 410 as the power supply selector control signal.In one embodiment, in response to the logic high of above-mentioned power supply selector control signal, DC/DC converter 410 is set as provides whole electric energy.In another embodiment, DC/DC converter 410 is set as the voltage higher a little than the specified output of power supply unit 280, when the output of power supply unit 280 descends, automatically power thus, and DC/DC converter 410 does not need above-mentioned power supply selector control signal as input thus by OR circuit 420.In typical embodiment, holding capacitor 235 has relatively large value, with the power demand of each equipment and any temporary transient power imbalances between the power that can obtain from PoE passage (this passage comprises PoE shunt and LAN card 210) in the reply architecture 500.

CPU and chipset 290 are in response to interruption that interruptable controller 370 produced and call a routine, this routine is saved in environmental information on the volatile memory 310 and next and operates the said equipment power control signal by power-management interface 295, reduces power mode so that each connection device placed.Preferably, this reduces power mode is sleep pattern, has wherein preserved facility environment.When CPU and chipset 290 store facility environment on the volatile memory 310, this equipment can be placed closed condition to save extra electric energy.In response to being placed in above-mentioned each connection device that reduces in the power mode, the power demand of architecture 500 is less than or equal to the power that can obtain by the PoE passage.Operating power management interface 295 can be used up some times with the power demand that reduces all connection devices, and the temporary transient power imbalances of capacitor 235 supports, and is unbalance up to proofreaied and correct this by the power demand that successfully reduces connection device.Should be appreciated that, CPU and chipset 290 in response to power-management interface 295 to transfer to standby low power mode.Notice that in the above-described embodiment, after the AC main line broke down, power supply unit 280 quit work, and DC " well " signal becomes logic low.

As mentioned above, only as DC " well " when signal presents logic high, AND gate 350 is the high signal of output logic, this logic high signal is transfused to CPU and chipset 290, and as logic high PoE " well " signal was pointed, the output of DC/DC converter 410 was available with stable.This input can be utilized by power-management interface 295, thereby can make the user in response to the standby power supply that senses based on available PoE suitable software setting is set.

When main supply was resumed, in response to user's input (such as pushing power knob 510), controlled source 282 was exported stable power and DC " well " signal is made as logic high.PoE " well " signal remains logic high, thereby points out once to have kept electric energy when the AC main supply breaks down, and the interruption that interruptable controller 370 is produced is eliminated thus.Power-management interface 295 recovers environmental information again and enables normal running, and then withdraw from above-mentioned interruption routine in response to logic high DC " well " signal and the interruption that is eliminated.Advantageously, do not need to restart, power-management interface 295 just works on.

Fig. 4 d shows the timing diagram of the relation between some signal in the architecture 500 of Fig. 3 d, wherein the x axle reflection time.Do not attempt to draw in proportion this timing diagram, the distance between the drawn thus variety of event is not passed in all senses.At moment T31, it is stable receiving PoE and detect this PoE by operation PoE checking 240, and PoE " well " signal presents logic high.Moment T32 (in typical embodiment, this moment may appear at the user and press after the power knob), DC " well " signal becomes logic high, thereby the regulated power of pointing out from controlled source 282 is available.After moment T32, in response to above-mentioned DC " well " and PoE " well " signal, above-mentioned power supply selector control signal presents logic low.

At moment T33, above-mentioned DC " well " signal becomes logic low because of the AC main supply breaks down, and produces an interruption by interruptable controller 370 to CPU and chipset 290.Electric energy is provided by DC/DC converter 410, and this electric energy is from the electric energy that receives by PoE passage (it comprises PoE shunt and LAN card 210).Any temporary transient power imbalances all provides from holding capacitor 235.At moment T34, CPU and chipset 290 have been finished and have been stored environmental information into volatile memory 310, and volatile memory 310 will receive the electric energy from DC/DC converter 410 when the AC main line breaks down, and power-management interface 295 begins to reduce total power demand by relevant device power supply (DPS) control signal.In another embodiment, at moment T34, thereby CPU and chipset 290 have started by placing standby mode to reduce the process of power demand each equipment.At moment T35, total power demand be reduced to be equal to or less than can by PoE shunt and LAN card 210 from PoE be connected or passage the power that obtains.In one embodiment, CPU and chipset 290 all store all environmental informations into volatile memory 310, and in another embodiment, when safeguarding environment, all equipment all is placed in its lowest power state.The high-speed cache 305 of hard disk drive 300 still is in the low power state, and by the electric energy of OR circuit 420 receptions from DC/DC converter 410.In another embodiment, power-management interface 295 is further closed various device, and they are made as sleep or park mode.In typical embodiment,, closed heat radiation (CPU) fan at moment T35.

Be appreciated that when DC " well " signal can't present logic high and PoE " well " when signal presents logic high, architecture 500 is provided with an interruption to CPU and chipset 290.Thus, this interruption reflects that controlled source unit 282 does not provide effective output, and standby power supply is available.Shown in moment T36, the AC main supply is resumed and the user presses that power switch is made as PS_ON# logic low thus and from controlled source 282 the high DC of receive logic " well " signal, consequently when DC " well " when signal is resumed above-mentioned interruption just be through with.The power supply selector control signal becomes and presents logic low, thereby has made the End of Interrupt of CPU and chipset 290, and has reduced the output of DC/DC converter 410 in one embodiment.In another embodiment, in response to from the reappearing of power supply unit 280 specified outputs, the output of DC/DC converter that is connected to the output of power supply unit 280 by OR circuit 420 has reduced its each output.CPU and chipset 290 hereinafter recover environmental information with the mode of explanation and work on a kind of in response to this End of Interrupt and DC " well " logic high that receives.

It is the high level block diagram of architecture 600 that Fig. 3 e show principle according to the present invention to provide an embodiment of the Computer Architecture of standby power supply.Architecture 600 comprises: the AC main line connects 70; Power supply 20, power supply 20 is made of electromagnetic interface filter 260, diode bridge 270, holding capacitor 275 and power supply unit 280, and power supply unit 280 is made of controlled source 282 and standby power 284; CPU and chipset 290, it comprises power-management interface 295; Hard disk drive 300, it comprises cache memory 305; Volatile memory 610; AC proof scheme 320; Phase inverter 330; Interruptable controller 370; Supply unit 620; Indicator 640; And power knob 510.

The AC main line connects 70 and is connected to the electromagnetic interface filter 260 of the input of power supply 20, and is connected to AC proof scheme 320 in parallel.The output of electromagnetic interface filter 260 is connected to the input of diode bridge 270, and the input of crossing over holding capacitor 275 and being connected to power supply unit 280 is exported in the rectification of diode bridge 270.The output of AC proof scheme 320 is connected to the input of interruptable controller 370 by phase inverter 330, and the output of interruptable controller 370 is fed to the input of CPU and chipset 290.The output of CPU and chipset 290 (being labeled as " PS_ON# ") is connected to the remote power feeding control input of power supply unit 280.Power knob 510 is arranged to the signal of expression user expectation close computing machine is connected to CPU and chipset 290.Indicator 640 is connected to interruptable controller 370.The power supply of power supply unit 280 output (being labeled as 3.3V, 12V, 5V and 5VSTBY) is shown and is connected to CPU and chipset 290, yet this does not also mean that by any way and limit.These power supply outputs are connected to each element that needs electric energy in the architecture 600 on request.Particularly, in one embodiment,, from the state of the PS_ON# signal of standby power 284 how hard disk drive 300 is connected to 5V and the 12V output that receives power supply unit 280, and volatile memory 310 connects into the electric energy of reception from power supply unit 280 no matter.Should be appreciated that passing through under the situation of PS_ON# signal at stop controlled source 282, each equipment that is connected to the 5VSTBY circuit is arranged to receive the electric energy from power supply unit 280, this electric energy is from controller power source 282 or from standby power 284.Controlled source 282 is also exported DC " well " signal, and all outputs of this signal indication controlled source 282 all are that effectively this DC " well " signal is connected to the input of CPU and chipset 290.Power supply 620 (in typical embodiment, it comprises battery) is arranged to provide standby power to volatile memory 610.In one embodiment, volatile memory comprises static RAM.In another embodiment, power supply 620 comprises capacitor, and for of short duration power failure cycle (such as continuing several seconds to a few minutes), this capacitor provides enough electric energy to keep the content of volatile memory 610.In another embodiment, power supply 620 comprises the high voltage capacitor on the input two ends that are connected power supply 20, for of short duration power failure cycle (such as continuing several seconds to a few minutes), this high voltage capacitor provides enough electric energy to keep the content of volatile memory 610.In another embodiment, power supply 620 comprises the flywheel energy storage system, and preferably, this flywheel energy storage system is MEMS (micro electro mechanical system) (MEMS) type.

In the course of the work, it is filtered by electromagnetic interface filter 260 to connect the AC power supplies that receives 70 from the AC main line, by rectification, makes it level and smooth by holding capacitor 275 by diode bridge 270, and by feed-in power supply unit 280.After electric energy was stable, power supply unit 280 was exported multiple voltage and in response to DC " well " signal of controlled source 282 from controlled source 282 and standby power 284.Controlled source 282 is only in response to about the logic low of PS_ON# signal output voltage, and the PS_ON# signal may be in response to that the user presses power knob 510 and produce.AC power supplies monitors that by AC proof scheme 320 this AC proof scheme 320 is used to identify the decay of power supply.In typical embodiment, AC proof scheme 320 monitors the AC voltage waveforms, and when AC power supplies is good the high signal of output logic, output logic low signal then when the shape that does not have AC waveform or AC waveform is used to represent the power supply decay.In typical embodiment, thereby this is to compare with the reference waveform that is written in advance by the waveform after input AC voltage waveform is sampled and will be sampled to realize, and detects any variation with respect to the expection waveform thus.In one embodiment, the high signal of AC proof scheme 320 output logic within predetermined amount of time is preferably within 4 milliseconds or comparing with reference waveform within 1/4 cycle length that change to surpass 20% input AC voltage waveform.Before the output feed-in interruptable controller 370 with AC proof scheme 320, phase inverter 330 makes the output of AC proof scheme 320 anti-phase.The output of interruptable controller 370 is interrupted by feed-in CPU and chipset 290 as one.In typical embodiment, this interruption is system management interrupt (SMI).

CPU and chipset 290 are in response to interruption that interruptable controller 370 produced and call a routine, and this routine is saved in environmental information on the volatile memory 610 and by power-management interface 295 comes the operating equipment power control signal so that each connection device is placed sleep pattern or closed condition.Any environment to be preserved preferably is saved on the volatile memory 610 of being powered by power supply 620.Operating power management interface 295 can take the regular hour with the power demand that reduces all connection devices, and capacitor 275 is kept effective DC power supply output so that CPU and chipset 290 can the information that all are essential all store on the volatile memory 610 in the sufficiently long time.As mentioned above, volatile memory 610 supported by power supply (such as battery 620), thus loss of information not when the AC main supply breaks down.

When the AC main supply was resumed, AC proof scheme 320 sensed available AC power supplies and the high signal of output logic, and the input of having removed interruptable controller 370 anti-phase by phase inverter 330 of this signal.In response to the input that is eliminated, this interruptable controller 370 has been removed the interruption of CPU and chipset 290, and this point is come sensing by power-management interface 295.In response to user's input (such as pressing power knob 510), controlled source 282 is exported stable electric energy and DC " well " signal is made as logic high.Power-management interface 295 in response to this logic high DC " well " thus signal and the interruption that is eliminated and from volatile memory 610, recover environmental information and start normal running and withdraw from this interruption routine.In typical embodiment, indicator 640 may be a visible indicator (such as LED) or can audible indicator, this indicator 640 latchs from the set of the interruption of interruptable controller 370 and resets, thereby points out power fail to take place and environmental information has been kept to the user.Advantageously, power-management interface 295 does not need computing machine to restart just permission continuation normal running.

Fig. 4 e shows the timing diagram of the relation between some signal in the architecture 600 of Fig. 3 e, wherein x axle reflection time.Do not attempt to draw in proportion this timing diagram, the distance between the drawn thus variety of event is not passed in all senses.At moment T41, the AC main supply has been received and has been in the predetermined scope, and the output of AC proof scheme 320 presents logic high.At moment T42 (in typical embodiment, this moment may occur in response to the user presses power knob 510), DC " well " signal presents logic high, thereby the stabilized power source of pointing out from controlled source 282 is available.In response to the logic high output of AC proof scheme 320, above-mentioned interruption input signal is in logic low.

At moment T43, the output of AC proof scheme 320 becomes logic low, thereby points out AC power supplies outside preset range, thereby and above-mentioned interruption become logic high and interrupted CPU and chipset 290.Thereby CPU and chipset 290 particularly power-management interface 295 are replied by at once all environmental informations being saved in volatile memory 610 in response to the interruption that receives.In one embodiment, the information in the high-speed cache 305 is saved on the volatile memory 610.In another embodiment, independent power supply (not shown) is supported high-speed cache 305.In another embodiment, high-speed cache 305 is written into hard disk drive 300.At moment T44, CPU and chipset 290 have been finished and have been stored environmental information into volatile memory 610, and DC " well " signal stops to be supported on logic high, thereby point out to stop causing there has not been power supply because of the intrinsic hold-up time of power supply 20.

At moment T45, AC checking 320 points out that the AC main supply has turned back within the predetermined scope, and above-mentioned interruption end of input.At moment T46, press power knob 510 in response to the recovery of AC main supply and user and thus PS_ON# is made as logic low, the high DC of controlled source 282 output logics " well " signal, thus point out that power supply output is provided reliably.CPU and chipset 290 in response to End of Interrupt and the logic high DC " well " that receives thus signal hereinafter recovers environmental information with the mode of explanation and works on a kind of from volatile memory 610.

Fig. 5 shows according to the CPU of schematic diagram 3a of the present invention and the chipset high level flow chart in response to the embodiment of the operation of power fail interrupt.In the stage 1000, receive an interruption.In typical embodiment, this interruption is encoded into SMI.In the stage 1010, call interrupt handling routine.In typical embodiment, interrupt handling routine is forbidden all other threads that just moving.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine is the part of operating system.Be no more than under the situation of scope of the present invention, this operating system can be based on the operating system of Windows, based on the operating system of LINUX, based on Macintosh OS operating system or any other operating system.

In the stage 1020, do not appear at by the memory environments on the storer of 5VSTBY line powering and be stored in volatile memory by the 5VSTBY line powering.In typical embodiment, the disk cache storer 305 of Fig. 3 a is stored on the volatile memory by the 5VSTBY line memory.In another embodiment, the disk cache storer is written into hard disk drive.In the stage 1030, the CPU configuration surroundings is saved to the volatile memory by the 5VSTBY line powering.Randomly, in the stage 1040, video memory information is saved to the volatile memory by the 5VSTBY line powering.In the stage 1050, PS_ON# is drawn high, and forbids the power supply of all outputs of power supply unit 280 thus except each output for the 5VSTBY line powering.

Fig. 6 a shows the high level flow chart of embodiment of operation of the architecture 200 of Fig. 3 a.In the stage 2000, sense AC power and be in outside the predetermined reference range.In typical embodiment, before the dc voltage that provides departs from regulation, just carry out above-mentioned sensing from AC power.Preferably, in the time period in 1/4 cycle of specified main supply, carry out above-mentioned sensing.Advantageously, before the dc voltage that provides from AC power departed from regulation, this sensing provided the time period at least 3/4 cycle of specified main supply.

In the stage 2010, in response to the sensing in stage 2000, one interrupts being sent to CPU.In one embodiment, this interruption is that SMI interrupts.In the stage 2020, the interrupt handling routine that is associated with interrupt source is called.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine comprises the operating system routine that runs in the operating system nucleus.

In the stage 2030, environment is saved to volatile memory.In typical embodiment, environment be included in the AC main supply recover after reboot operation system and with the content of operating system recovery to necessary all memory locations of current state and position and register.This can comprise in following any ad lib: processor state is stored in when entering System Management Mode among the system management RAM (SMRAM) usually; Control register is not stored when entering System Management Mode; Debug registers; Multimedia extension (MMX) register; Floating point unit (FPU) register; The keyboard controller byte; Interrupt register and pointer; The video memory environment; And restart necessary mark.The environment that stage 2030 is preserved is saved to those volatile memory positions that receive standby power supply when the AC main supply breaks down.

In the stage 2040, the primary power of architecture 200 drops to only keeps the 5VSTBY circuit.In typical embodiment, the power-management interface 295 of CPU and chipset 290 is made as logic high with the PS_ON# signal.Therefore, the power supply of not used by all devices of 5VSTBY line powering is removed.Power demand under this state is less than the power that can provide by the PoE passage.

In the stage 2050, utilizing power supply unit 280 during the AC main supply breaks down is that the 5VSTBY of stand-by unit 284 exports and keeps the electric energy that is used for volatile memory, once environment is saved on this volatile memory in the stage 2030.In typical embodiment,, power through the PoE passage by keeping primary power.Time value about volatile memory reception electric energy does not have intrinsic qualification.Be used to support the electric energy of the PSE of PoE passage to connect from independent AC main line, the UPS and/or the generator of centralization, to guarantee that the environmental information that the stage 2030 stored is kept.

In the stage 2060, AC power supplies is recovered and senses AC power supplies to be within the benchmark.In typical embodiment, before the DC output voltage that provides within the specialized range, carry out above-mentioned sensing.In the stage 2070, the interruption that the stage 2010 is sent is removed.In the stage 2080, preferably enable complete DC power supply by opening power remotely.In another embodiment, the user must activate to open and close (on off) above-mentioned power supply.

In the stage 2090, descend and be placed in the hardware state of those equipment that reduce in the power mode before being restored to them at stages 2040 power.In typical embodiment, this also comprises enables heat (CPU) fan and make CPU and chipset 290 comes out from standby mode.In the stage 2100, the environment that is stored on the volatile memory as the part in stage 2030 is resumed.Preferably, all RS content and those registers of being associated with the equipment that recovered in the stage 2090 all are resumed.In the stage 2110, this system reverts to the state of AC main supply before breaking down fully, and realizes returning from the interruption routine of being called in the stages 2020.Thus, preferable and advantageously, after power up, do not need just to restart to work on.

Fig. 6 b shows the high level flow chart of embodiment of operation of the architecture 400 of Fig. 3 b.In the stage 2500, sense AC power supplies and be in outside the predetermined reference range.In typical embodiment, before the dc voltage that provides departs from regulation, just carry out above-mentioned sensing from AC power supplies.Preferably, in the time period in 1/4 cycle of specified main supply, carry out above-mentioned sensing.Advantageously, before the dc voltage that provides from AC power departed from regulation, this sensing provided the time period at least 3/4 cycle of specified main supply.

In the stage 2510, in response to the sensing in stage 2500, one interrupts being sent to CPU.In one embodiment, this interruption is that SMI interrupts.In the stage 2520, the interrupt handling routine that is associated with interrupt source is called.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine comprises the operating system routine that runs in the operating system nucleus.

In the stage 2530, environment is saved to volatile memory.In typical embodiment, environment be included in the AC main supply recover after reboot operation system and with the content of operating system recovery to necessary all memory locations of current state and position and register.This can comprise in following any ad lib: processor state is stored in when entering System Management Mode among the system management RAM (SMRAM) usually; Control register is not stored when entering System Management Mode; Debug registers; Multimedia extension (MMX) register; Floating point unit (FPU) register; The keyboard controller byte; Interrupt register and pointer; The video memory environment; And restart necessary mark.The environment that stage 2530 is preserved is saved to those volatile memory positions that receive standby power supply when the AC main supply breaks down.

In the stage 2540, utilize power-management interface 295 that each plant capacity is descended.In one embodiment, this realizes by south bridge power is descended, and in another embodiment, each equipment relevant with architecture 400 is endowed power decline respectively orders.In typical embodiment, CPU and chipset 290 are placed in minimum power state, and in another embodiment, CPU and chipset 290 are placed in sleep pattern.In typical embodiment, as part forbidding heat (CPU) fan in this stage.Power demand under this state is less than the power that can provide by the PoE passage.

In the stage 2550, during the AC main supply breaks down, utilize the power supply of power supply unit 280 to export and keep the power supply that is used for volatile memory, once environment was saved on this volatile memory in the stage 2530.Advantageously, all voltages all are available, and the data in the high-speed cache 305 can be unaffected thus.In typical embodiment,, power through the PoE passage by keeping primary power.Time value about volatile memory reception electric energy does not have intrinsic qualification.Be used to support the electric energy of the PSE of PoE passage to connect from independent AC main line, the UPS and/or the generator of centralization, be maintained to guarantee the environmental information that the stage 2530 stored.

In the stage 2560, AC power supplies is resumed and senses AC power supplies and is within the benchmark.In typical embodiment, before the DC output voltage that provides within the specialized range, carry out above-mentioned sensing.In the stage 2570, the interruption that the stage 2510 is sent is removed.In the stage 2580, power descends or the various device that is placed in the sleep pattern is restored to its previous hardware state in the stage 2540, i.e. operational mode fully.In typical embodiment, this also comprises enables heat (CPU) fan and make CPU and chipset 290 comes out from standby mode.In the stage 2590, the environment that is stored on the volatile memory as the part in stage 2530 is resumed.Preferably, all RS content and those registers of being associated with the equipment that recovered in the stage 2580 all are resumed.In the stage 2600, this system reverts to the state of AC main supply before breaking down fully, and realizes returning from the interruption routine of being called in the stages 2520.Thus, preferable and advantageously, after power up, do not need just to restart to work on.

Fig. 6 c shows the high level flow chart of embodiment of operation of the architecture 450 of Fig. 3 c.In the stage 3000, sense AC power and be in outside the predetermined reference range.In typical embodiment, before the dc voltage that provides departs from regulation, just carry out above-mentioned detection from AC power.Preferably, in the time period in 1/4 cycle of specified main supply, carry out above-mentioned detection.Advantageously, before the dc voltage that provides from AC power departed from regulation, this sensing provided the time period at least 3/4 cycle of specified main supply.

In the stage 3010, in response to the sensing in stage 3000, one interrupts being sent to CPU.In one embodiment, this interruption is that SMI interrupts.In the stage 3020, the interrupt handling routine that is associated with interrupt source is called.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine comprises the operating system routine that runs in the operating system nucleus.

In the stage 3030, environment is saved to volatile memory.In typical embodiment, environment be included in the AC main supply recover after reboot operation system and with the content of operating system recovery to necessary all memory locations of current state and position and register.This can comprise in following any ad lib: processor state is stored in when entering System Management Mode among the system management RAM (SMRAM) usually; Control register is not stored when entering System Management Mode; Debug registers; Multimedia extension (MMX) register; Floating point unit (FPU) register; The keyboard controller byte; Interrupt register and pointer; The video memory environment; And restart necessary mark.The environment that stage 3030 is preserved is saved to those volatile memory positions that receive standby power supply when the AC main supply breaks down.

In the stage 3040, utilize power-management interface 295 that each plant capacity is descended.In one embodiment, this realizes by south bridge power is descended, and in another embodiment, each equipment relevant with architecture 450 is endowed power decline respectively orders.In typical embodiment, CPU and chipset 290 are placed in minimum power state, and in another embodiment, CPU and chipset 290 are placed in sleep pattern.In typical embodiment, as the part in this stage, forbidding heat (CPU) fan.Power demand under this state is less than the power that can provide by the PoE passage.

In the stage 3050, during breaking down, the AC main supply utilize the voltage that from the PoE passage, obtains by DC/DC converter 410 to keep the power supply that is used for volatile memory, once environment was saved on this volatile memory in the stage 3030.The principal computer power supply is not exercisable.Advantageously, all voltages all are available, and the data in the high-speed cache 305 can be unaffected thus.Time value about volatile memory reception electric energy does not have intrinsic qualification.Be used to support the power supply of the PSE of PoE passage to connect from independent AC main line, the UPS and/or the generator of centralization, be maintained to guarantee the environmental information that the stage 2530 stored.

In the stage 3060, AC power supplies is resumed and senses AC power supplies and is within the benchmark.In typical embodiment, before the DC output voltage that provides within the specialized range, carry out above-mentioned sensing.In the stage 3070, the interruption that the stage 3010 is sent is removed.In the stage 3080, thereby preferably enable controlled source 282 by PS_ON# being made as logic low, and DC " well " thus power availability is determined in logic high in the sensed source of signal.Power descends or the various device that is placed in the sleep pattern is restored to its previous hardware state in the stage 3040, i.e. operational mode fully.In typical embodiment, this also comprises enables heat (CPU) fan and make CPU and chipset 290 comes out from standby mode.In the stage 3090, the environment that is stored on the volatile memory as the part in stage 3030 is resumed.Preferably, all RS content and those registers of being associated with the equipment that recovered in the stage 3080 all are resumed.In the stage 3110, this system reverts to the state of AC main supply before breaking down fully, and realizes returning from the interruption routine of being called in the stages 3020.Thus, preferable and advantageously, after power up, do not need just to restart to work on.

Fig. 6 d shows the high level flow chart of embodiment of operation of the architecture 500 of Fig. 3 d.In the stage 3500, the AC main supply breaks down and causes supporting DC " well " signal to be in logic high, thereby points out that the DC electric energy that provides from the AC main supply has departed from specialized range.

In the stage 3510, lack logic high in DC " well " signal in response to the stage 3500, one interrupts being sent to CPU.In one embodiment, this interruption is that SMI interrupts.In the stage 3520, necessary all voltages of architecture 500 and relevant device are all provided by the PoE passage, and simultaneously any temporary transient mismatch between the architecture 500 necessary power and the power that can obtain from the PoE passage is all supported by holding capacitor 235.In the stage 3530, the interrupt handling routine that is associated with interrupt source is called.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine comprises the operating system routine that runs in the operating system nucleus.

In the stage 3540, environment is saved to volatile memory.In typical embodiment, environment be included in the AC main supply recover after reboot operation system and with the content of operating system recovery to necessary all memory locations of current state and position and register.This can comprise in following any ad lib: processor state is stored in when entering System Management Mode among the system management RAM (SMRAM) usually; Control register is not stored when entering System Management Mode; Debug registers; Multimedia extension (MMX) register; Floating point unit (FPU) register; The keyboard controller byte; Interrupt register and pointer; The video memory environment; And restart necessary mark.The environment that stage 3030 is preserved is saved to those volatile memory positions that receive standby power supply when the AC main supply breaks down.

In the stage 3550, utilize power-management interface 295 that each plant capacity is descended.In one embodiment, this realizes by south bridge power is descended, and in another embodiment, each equipment relevant with architecture 500 is endowed power decline respectively orders.In typical embodiment, CPU and chipset 290 are placed in minimum power state, and in another embodiment, CPU and chipset 290 are placed in sleep pattern.In typical embodiment, as the part in this stage, forbidding heat (CPU) fan.The power that can provide by the PoE passage is provided power demand under this state.CPU and chipset 290 are placed in the power drop mode, and wherein it is still in response to interruptable controller 370.In one embodiment, CPU and chipset 290 are kept logic low PS_ON# signal.

In the stage 3560, during breaking down, the AC main supply utilize the voltage that from the PoE passage, obtains to keep the power supply that is used for volatile memory, once environment was saved on this volatile memory in the stage 3540.The principal computer power supply is not exercisable.Advantageously, all voltages all are available, and the data in the high-speed cache 305 can be unaffected thus.Time value about volatile memory reception electric energy does not have intrinsic qualification.Be used to support the power supply of the PSE of PoE passage to connect from independent AC main line, the UPS and/or the generator of centralization, to guarantee that the environmental information that the stage 3540 stored is kept.

In the stage 3570, AC power supplies is resumed, and in response to logic low PS_ON# signal, CPU and chipset 290 receive logic high DC " well " signal.In addition, the interruption that receives in the step 3510 is removed.In another embodiment, press power knob by the user and just produced logic low PS_ON# signal, and CPU and chipset 290 receive logic high DC " well " signal in response to the user presses power knob.In the stage 3580, power descends or the various device that is placed in the sleep pattern is restored to its previous hardware state in the stage 3550, i.e. operational mode fully.In typical embodiment, this also comprises enables heat (CPU) fan and make CPU and chipset 290 comes out during stage 3550 from the standby mode that is provided with.In the stage 3590, the environment that is stored on the volatile memory as the part in stage 3540 is resumed.Preferably, all RS content and those registers of being associated with the equipment that recovered in the stage 3580 all are resumed.In the stage 3600, this system reverts to the state of AC main supply before breaking down fully, and realizes returning from the interruption routine of being called in the stages 3530.Thus, preferable and advantageously, after power up, do not need just to restart to work on.

Fig. 6 e shows the high level flow chart of embodiment of operation of the architecture 600 of Fig. 3 e.In the stage 4000, sense AC power and be in outside the predetermined reference range.In typical embodiment, before the dc voltage that provides departs from regulation, just carry out above-mentioned sensing from AC power.Preferably, in the time period in 1/4 cycle of specified main supply, carry out above-mentioned sensing.Advantageously, before the dc voltage that provides from AC power departed from regulation, this sensing provided the time period at least 3/4 cycle of specified main supply.

In the stage 4010, in response to the sensing in stage 4000, one interrupts being sent to CPU.In one embodiment, this interruption is that SMI interrupts.In the stage 4020, the interrupt handling routine that is associated with interrupt source is called.In one embodiment, interrupt handling routine is the BIOS routine, and in another embodiment, interrupt handling routine comprises the operating system routine that runs in the operating system nucleus.

In the stage 4030, environment is saved to volatile memory.In typical embodiment, environment be included in the AC main supply recover after reboot operation system and with the content of operating system recovery to necessary all memory locations of current state and position and register.This can comprise in following any ad lib: processor state is stored in when entering System Management Mode among the system management RAM (SMRAM) usually; Control register is not stored when entering System Management Mode; Debug registers; Multimedia extension (MMX) register; Floating point unit (FPU) register; The keyboard controller byte; Interrupt register and pointer; The video memory environment; And restart necessary mark.The environment that stage 4030 is preserved is saved to those volatile memory positions that receive standby power supply when the AC main supply breaks down.

In the stage 4040, during breaking down, the AC main supply utilizes standby power to keep to be used for the electric energy of volatile memory, once environment was saved on this volatile memory in the stage 4030.In typical embodiment, standby power is a battery.The principal computer power supply is not exercisable.

In the stage 4050, AC power supplies is resumed with sensed.In typical embodiment, before the DC output voltage that provides within the specialized range, carry out above-mentioned sensing.In the stage 4060, the interruption that the stage 4010 is sent is removed.In the stage 4070, preferably start indicator, thereby point out to have recovered power supply and during power supply breaks down, once preserved environmental information to the user.In the stage 4080, the user recovers power supply by pressing power knob 510 from power supply 20.In another embodiment, when receiving tolerance limit with interior AC main supply, power supply 20 is configured to automatically restart and DC is provided output.In this embodiment, the user action in stage 4080 is optional, and power supply is automatically recovered.In the stage 4090, the environment that is stored on the volatile memory as the part in stage 4030 is resumed.In the stage 4100, this system reverts to the state of AC main supply before breaking down fully, and realizes returning from the interruption routine of being called in the stages 4020.Thus, preferable and advantageously, after power up, do not need just to restart to work on.

Fig. 7 a shows the high level, functional block diagram of first embodiment of AC proof scheme 320, and it comprises A/D converter 710, waveform reference generator 720, comparing function 730 and departs from scope and determine function 740.The input of AC sample is connected to the input of A/D converter 710, and the output of A/D converter 710 is fed to first input of comparing function 730.The output of waveform reference generator 720 is connected to second input of comparing function 730, and the feedback output of comparing function is connected to the feedback input of waveform reference generator 720.The output of comparing function 730 is connected to and departs from the input that scope is determined function 740, departs from output that scope determines function 740 then as the output of AC proof scheme 320 and connect.

In the course of the work, A/D converter 710 receives the AC sample waveform of importing from AC and this sample conversion is become digital form.In typical embodiment, this sample obtains by resistive divider network.Waveform reference generator 720 produces the digital form of expection waveform.In typical embodiment, waveform reference generator 720 is kept phase information by receiving from the feedback of comparing function 730, and this further describes hereinafter.Comparing function 730 can realize that it will import the digital form of AC waveform and the output of waveform reference generator 720 compares with general microcontroller or digital signal processor.In typical embodiment, the multiple voltage waveform is stored in the waveform reference generator 720, and in the initialization phase place, has determined suitable waveform (comprising voltage and cycle length).

If phase shifts or initial phase lock are arranged, then phase information sends to waveform reference generator 720 from comparing function 730, so that the waveform that waveform reference generator 720 is produced aligns with the AC waveform of input.Depart from scope determine function 740 more above-mentioned differences (if comparing function 730 is found words of any difference) with the AC waveform of determining input whether within the preset range of reference waveform.If the AC waveform of input is confirmed as being within the predetermined scope, then the high signal of output logic.If the AC waveform of input is confirmed as not being within the predetermined scope, then the output logic low signal.

Fig. 7 b shows the high level, functional block diagram of second embodiment of AC proof scheme 320, and it comprises waveform reference generator 720, D/A converter 760, comparing function 770 and departs from scope and determine function 780.The input of AC sample is connected to first input of comparing function 770.The output of waveform reference generator 720 is connected to the input of D/A converter 760, and the output of D/A converter 760 is connected to second input of comparing function 770.The feedback output of comparing function 770 is connected to the feedback input of waveform reference generator 720.The output of comparing function 770 is connected to and departs from the input that scope is determined function 780.Depart from output that scope determines function 780 then as the output of AC proof scheme 320 and connect.

In the course of the work, waveform reference generator 720 produces the digital form of expection waveform.In typical embodiment, waveform reference generator 720 is kept phase information by receiving from the feedback of comparing function 730, and this further describes hereinafter.The digital form that D/A converter 760 is exported waveform reference generator 720 converts the aanalogvoltage of suitable amplitude to so that compare with input AC sample.Comparing function 770 (may realize with mimic channel) compares the simulation output of AC sample input with D/A converter 760.In typical embodiment, the multiple voltage waveform is stored in the waveform reference generator 720, and in the initialization phase place, has determined suitable waveform (comprising voltage and cycle length).

If phase shifts or initial phase lock are arranged, then phase information sends to waveform reference generator 720 from comparing function 730, so that the waveform that waveform reference generator 720 is produced aligns with the AC waveform of input.Like this, the amplitude difference between the AC sample of any moment input and the expection waveform that waveform reference generator 720 is produced has been represented in the output of comparing function 770.Depart from scope determine function 740 more above-mentioned differences (if comparing function 770 is found words of any difference) with the AC waveform of determining input whether within the preset range of reference waveform.If the AC waveform of input is confirmed as being within the predetermined scope, then the high signal of output logic.If the AC waveform of input is confirmed as not being within the predetermined scope, then the output logic low signal.

Fig. 7 c shows the high level flow chart of the operation of AC proof scheme 320.In the stage 4000, receive the AC waveform sample of representing the AC main supply.In typical embodiment, the AC waveform sample that receives is a little sampling section of AC main supply.In the stage 4010, selected suitable reference waveform by voltage and frequency.In the stage 4020, AC waveform sample and the AC reference waveform of importing compared.In one embodiment, the AC reference waveform is produced by the digital form of expection waveform, preferably at any phase differential between this benchmark and the AC waveform sample it is carried out dynamic adjustments.

In the stage 4030, AC reference waveform and above-mentioned AC waveform sample are compared to judge whether these two waveforms are in preset range each other.In one embodiment, shown in Fig. 7 a, the AC waveform sample at first carries out digitizing through A/D converter, and in another embodiment, shown in Fig. 7 b, the AC reference waveform is converted into the simulation reference waveform.If these two waveforms are within predetermined scope, then at the high AC validation signal of stages 4040 output logic.If be not within the predetermined scope at these two waveforms of stages 4030, then at the low AC validation signal of stages 4050 output logic.

Fig. 8 is that principle according to the present invention utilizes the SMI of the embodiment of Fig. 3 b to operate the higher level operation process flow diagram of an embodiment of BIOS routine.In the stage 5000, SMI interrupts being received and being identified as being produced by AC proof scheme 320.In typical embodiment, the power supply selector control signal is connected to the open circuit pin of CPU and chipset 290, can be discerned by the SMI handling procedure thus.In the stage 5010, the interruption that CPU and chipset 290 were identified in response to the stage 5000 enters System Management Mode (SMM), and in typical embodiment, this sends signal by CPU to chipset and realizes.In typical embodiment, this signal is SMIACT#.In the stage 5020, CPU and chipset 290 are preserved the stage that the major part of its current state is saved within the system management RAM (SMRAM) in the mapping table, and some registers of initialization are to provide SMM execution environment, and then, beginning is carried out within SMM.If necessary, the basis of this system management is re-mapped in the suitable physical system memory.It is also noted that SMRAM is included within the volatile memory 310.

In the stage 5030, the register that CPU and chipset 290 are not preserved when entering SMM preferably is stored among the SMRAM.In the stage 5040, the state of real-time timepiece chip is stored in the volatile memory, preferably stores among the SMRAM.In the stage 5050, interrupt phase preferably is saved among the SMRAM, and disable interrupts.Disable interrupts allows to preserve routine within short time quantum.

In the stage 5060, the previous system status information of not preserving preferably is stored among the SMRAM.Stage 5060 comprises preserves at least a in following: coprocessor state, the state of port 92h, keyboard controller command byte, A20 state, COM port state, LPT port state, and video state.Preferably, foregoing is saved among the SMRAM, or is saved in the annex memory position of being distributed in the volatile memory 310.

In the stage 5070, specific plant capacity is descended.The selection of particular device is based on the architecture of reality, particularly relates to the understanding that those is configured to treat down the actual relevant device of adjusting power.Preferably, those equipment as adjusting power under the part in stage 5070 comprise the Hot-air fan relevant with CPU.In the stage 5080, specific equipment is placed in the standby mode.Select particular device and make it place this process of standby mode to be based on the practical systems structure, particularly relate to the understanding that those is configured to be placed in the actual relevant device in the standby mode.In typical embodiment, particular device comprises at least one in following: PS/2 port, lan device, audio frequency apparatus, USB port, IEEE 1394 ports and IDE hard disk.

In the stage 5090, enable the standby refresh mode.Volatile memory 310 generally includes dynamic ram, and must enable the circuit that is used to refresh dynamic ram to avoid loss of information during the standby mode.In the stage 5100, in real pattern, preserve programmable interrupt controller.In the stage 5110, the standby mark is set, make CPU recognizes it is at standby mode when restarting.Stage 5110 comprises that also standby is set recovers the execution incident.In typical embodiment, this is meant removing and low level power supply selector control signal of SMI interruption.In the stage 5120, those equipment that are not in the decline of standby or power in the present architecture are placed in the sleep state.In typical embodiment, this realizes by south bridge.

Fig. 9 is the higher level operation process flow diagram according to the embodiment of the operation of arbitrary architecture among the schematic diagram 3a-3d of the present invention, is used for working at high power POE (be also referred to as PoE additional) or one of these two kinds of patterns of POE of having the Power Limitation of IEEE802.3af.The high power POE allows power to surpass the restriction of IEEE802.3af, and the U.S. Patent application of submitting on January 22nd, 2004 that awaits the reply jointly 10/761 that is entitled as " HighPower Architecture for Power Over Ethernet ", further describe in 327, its content whole is quoted at this as a reference.By using high power (preferably surpassing 40 watts power, better), just there are enough electric energy to support the operation of the computing machine in the dormancy above 60 watts.Term hibernation is meant and comprises that computing machine cuts out fully that wherein all volatile memory and environment are all stored on the nonvolatile memory rightly.

In the stage 6000, this routine comprises at first being written into and is used for indicating the information of current hardware configuration and the suitable routine of selecting from the routine of Fig. 6 a-6d.In the stage 6010, inquiry PoE connects to determine whether it is that high power connects or low-power connects, and its power limit is the requirement according to IEEE 802.3af boundary.By machine transferring data as calculated, or, just can realize above-mentioned poll by to supporting the automatic sensing of high-power a plurality of paths power supply.

If determine to obtain the electric energy that magnitude is the boundary of IEEE 802.3af in the stage 6010, then be written into and carry out the routine of from the routine of Fig. 6 a-6d, selecting in the stage 6000 in the stage 6020.

If determine to obtain the electric energy that magnitude exceeds the border of IEEE 802.3af in stage 6010, then determine to obtain high power and be written into hereinafter with the routine of explaining in the stage 6030.In the embodiment of replacing,, be written into the pointer that is used for work so that use in response to input from the AC proof scheme.

In the stage 6040, AC proof scheme 320 senses AC power supplies and departs from benchmark.In the stage 6050, interrupt sending to CPU with one, thereby point out to take place a power events and CPU should enter dormancy immediately.

In the stage 6060, during all storeies and environmental information were stored on the nonvolatile memory, high power connects supported computer operation completely.In the stage 6070, dormancy has been finished, and CPU has started fully and closes.

Above-mentioned embodiment is described in conjunction with single cpu, yet this does not mean that by any way and limits.Particularly, it means and comprises the computing machine with a plurality of chips nuclear that one of wherein a plurality of chips nuclears operationally represent that in response to being used to the interruption of power falling event is to reduce power consumption, just as above described in conjunction with Fig. 6 a-6e.

Above-mentioned embodiment is described as has special-purpose PoE connection, yet this does not mean that by any way and limits.In an embodiment (not shown), the electric energy that receives by PoE is forwarded to another equipment (such as IP phone), and simultaneously a part gives over to standby requirement (such as the charging of the capacitor 235 of Fig. 3 a).If the AC main line breaks down, then electric energy is transmitted preferably and is interrupted, and PoE connect be specifically designed to realize above-mentioned standby.

Thus, present embodiment is enabled the standby power supply of computing machine when power supply breaks down, thereby makes volatile memory receive electric energy by use PoE during main supply breaks down.Particularly, sense the fault of main supply, and produced the interruption to processor, this interruption routine is saved in the volatile memory position that is used to receive standby power supply with environmental information and data simultaneously.During main line broke down, PoE connects provided the standby power supply that is used for the volatile memory position.In typical embodiment, this interruption routine starts a sleep state by operating system management.In one embodiment, this interruption is encoded into SMI.

Should be appreciated that, in single embodiment, provided for clear and some feature of the present invention that describe in independent embodiment also can combine.On the contrary, for simplicity and the various features of describing in single embodiment of the present invention also can be provided separately or provided in any suitable recombinant mode.

Except as otherwise noted, otherwise all technology used herein and scientific terminology all have the identical meanings of those skilled in the art's common sense.Although the practice or test in the process of the present invention and can use the method similar or identical with this paper, again this described herein be suitable method.

Mentioned all publications, patented claim, patent and other reference of this paper all quoted at this with its full content.If contradictory, then be as the criterion with patent specification (comprising various definition).In addition, material, method and example all only are exemplary and are not intended to limit.

It should be appreciated by those skilled in the art, the invention is not restricted to this paper illustrate especially and describe.Scope of the present invention is limited and comprises the combination and the recombinant of various feature described herein and modification thereof, variation by appended claims, above-mentioned modifications and variations then are that those skilled in the art make when reading above-mentioned instructions and not in the scope in prior art.

Claims

1. one kind places computing machine and maintain the system of standby mode in outage, and described system comprises:

The device that is used for sensing main supply fault;

Be used to provide the device of standby power, described standby power is less than the power that can be used for working fully;

Volatile memory is arranged to be used to provide the device of standby power to power by described; And

Processor, described processor operationally store on the described volatile memory in response to the described device that is used for the sensing fault so that with status information and the power demand of described computing machine are reduced to and be not more than the power that can obtain from the described device that is used to provide standby power.

2. the system as claimed in claim 1, also comprise the power supply that presents output of first power supply and the output of at least one second source, described power supply is in response to from the signal of described processor so that at least one power supply of ending in described first power supply output power supply in described second source output, described power supply is arranged to when sensing the main supply fault to receive the electric energy that is used to provide the device of standby power from described, and described volatile memory is arranged to export by described first power supply and powers and be used to provide the device of standby power to power by described thus.

3. system as claimed in claim 2 is characterized in that, described power supply is reduced to described power demand less than the power value that can obtain from the described device that is used to provide standby power in response to described signal.

4. the system as claimed in claim 1 is characterized in that, described processor by system management interrupt operationally in response to the described device that is used for the sensing fault.

5. the system as claimed in claim 1 is characterized in that, described processor interrupts operationally in response to the described device that is used for the sensing fault by one.

6. the system as claimed in claim 1, also comprise the DC/DC converter that is associated with the described device that is used to provide standby power, described volatile memory is arranged to be used to provide the device of standby power to power by described, describedly is used to provide the device of standby power then to power by described DC/DC converter.

7. the system as claimed in claim 1 is characterized in that, is sensing within 17 milliseconds of main supply fault, and described processor is operationally stored described status information.

8. the system as claimed in claim 1 is characterized in that, described volatile memory comprises disk cache.

9. the system as claimed in claim 1 is characterized in that, described status information comprises at least some contents in the video memory.

10. the system as claimed in claim 1 is characterized in that, described status information comprises at least a configuration in network interface card and the sound card.

11. the system as claimed in claim 1 is characterized in that, describedly is used to provide the device of standby power to comprise charged device controller, operationally is used for receiving electric energy by telecommunication cable.

12. system as claimed in claim 11 also comprises the device that is used for the described electric energy that receives of sensing, described processor is operationally in response to described device and the described device that is used for the described electric energy that receives of sensing that is used for the sensing fault.

13. system as claimed in claim 11 is characterized in that, described charged device controller meets the IEEE802.3af standard.

14. the system as claimed in claim 1 is characterized in that, the described device that is used for the sensing fault comprises analog to digital converter, and the described device that is used for the sensing fault operationally compares the output and a benchmark of described analog to digital converter.

15. the system as claimed in claim 1 is characterized in that, the described device that is used for the sensing fault comprises digital to analog converter, and the described device that is used for the sensing fault operationally compares the output and the signal in response to described main supply of described converter.

16. the system as claimed in claim 1 is characterized in that, described processor works in the kernel program pattern to store described status information.

17. the system as claimed in claim 1 is characterized in that, described processor works under the BIOS routine to store described status information.

18. the system as claimed in claim 1 also comprises being used for the device that the described fault main supply of sensing recovers, described processor operationally is used for device that sensing recovers so that obtain described status information again from described volatile memory in response to described.

19. the system as claimed in claim 1 is characterized in that, it is one of following that the described device that is used to provide standby power comprises: battery, and capacitor, the flywheel energy storage system, and connect power supply by Ethernet.

20. the system as claimed in claim 1 is characterized in that, the described device that is used to provide standby power comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.

21. one kind places computing machine and maintain the system of standby mode in outage, described system comprises:

The main supply fault sensor;

Standby power, the power of described standby power is less than the power that can be used for working fully;

Volatile memory is arranged to obtain power supply from described standby power during main supply breaks down; And

Processor, described processor operationally store on the described volatile memory in response to described main supply sensor so that with status information and the power demand of described processor and relevant device are reduced to and be not more than the power that can obtain from described standby power.

22. system as claimed in claim 21 is characterized in that, described processor passes through system management interrupt operationally in response to described main supply fault sensor.

23. system as claimed in claim 21 is characterized in that, described processor works in one of kernel program pattern and BIOS routine in response to described main supply fault sensor.

24. system as claimed in claim 21 is characterized in that, it is one of following that described standby power comprises: battery, and capacitor, the flywheel energy storage system, and connect power supply by Ethernet.

25. system as claimed in claim 21 is characterized in that, described standby power comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.

26. system as claimed in claim 21 comprises that also main supply recovers sensor, described processor further operationally recovers sensor so that recover described status information from described volatile memory in response to described main supply.

27. system as claimed in claim 21 is characterized in that, described processor operationally recovers described status information and need not to restart computing machine.

28. system as claimed in claim 21 also comprises electric pressure converter, described volatile memory obtains power supply by described electric pressure converter from described standby power when described main supply breaks down.

29. the method that stand-by electric energy is provided for computing machine when main supply breaks down, described method comprises:

Standby power is provided;

Volatile memory is provided;

The fault of sensing main supply;

In response to described sensing processor is interrupted;

Store the status information relevant into provided volatile memory with described processor; And

Power to described volatile memory from described standby power, keep described canned data during main supply breaks down sensing thus.

30. method as claimed in claim 29 is characterized in that, described interrupt procedure realizes by system management interrupt.

31. method as claimed in claim 29 also comprises:

The power supply that presents output of first power supply and the output of at least one second source is provided;

When main supply breaks down, power to described power supply from described standby power; And

In at least one power supply of in described first power supply output power supply, ending in described second source output,

Be to realize by described power supply at least in part to described volatile memory power supply wherein from described standby power.

32. method as claimed in claim 31 is characterized in that, described termination power supply is reduced to the power demand of described computing machine less than the power value that can obtain from described standby power.

33. method as claimed in claim 29 also comprises:

The electric pressure converter relevant with described standby power is provided, and is to realize by described electric pressure converter at least in part from described standby power to described volatile memory power supply wherein.

34. method as claimed in claim 29 is characterized in that, described storaging state information is to realize sensing within 17 milliseconds of main supply fault.

35. method as claimed in claim 29 is characterized in that, described volatile memory comprises disk cache.

36. method as claimed in claim 29 is characterized in that, described status information comprises at least some contents in the video memory.

37. method as claimed in claim 29 is characterized in that, described status information comprises at least a configuration in network interface card and the sound card.

38. method as claimed in claim 29 is characterized in that, described standby power is associated with POE.

39. method as claimed in claim 29 is characterized in that, described storage is to realize by the described processor that works in one of kernel program pattern and BIOS routine.

40. method as claimed in claim 29 also comprises:

The recovery of the described fault main supply of sensing; And

From described volatile memory, obtain described status information again.

41. method as claimed in claim 29 is characterized in that, it is one of following that described standby power supply comprises: battery, and capacitor, the flywheel energy storage system, and connect power supply by Ethernet.

42. method as claimed in claim 29 is characterized in that, described standby power comprises the flywheel energy storage system of MEMS (micro electro mechanical system) (MEMS) type.