CN113687994B - Memory programming time system for multi-station concurrent test and programming method thereof - Google Patents
Memory programming time system for multi-station concurrent test and programming method thereof Download PDFInfo
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- CN113687994B CN113687994B CN202111242592.4A CN202111242592A CN113687994B CN 113687994 B CN113687994 B CN 113687994B CN 202111242592 A CN202111242592 A CN 202111242592A CN 113687994 B CN113687994 B CN 113687994B
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Abstract
The invention relates to a memory programming time system for multi-station concurrent testing and a programming method thereof, belonging to the technical field of chip detection. The system of the invention comprises a storage unit, a time sequence generator, a data register, a test pattern generator, a serial time sequence generator, a time measuring unit and an electronic pin. The invention does not need to provide an independent processor for each tested device, thereby reducing the testing cost; the invention can complete the test of programming time in multiple stations; the invention is controlled by the PATTERN file, and the programming is simple and convenient.
Description
Technical Field
The invention relates to a memory programming time system for multi-station concurrent testing and a programming method thereof, belonging to the technical field of chip detection.
Background
In the test process of the programming time, whether writing is performed or not needs to be judged by inquiring a read-write flag bit or a register, so that the programming time is calculated, and whether the chip reaches the index specified by the designed writing speed or not is judged.
The existing test adopts a continuous query mode, and the write-in completion time is obtained through the query times and the query period. Generally, the Memory test has high test coverage rate requirement and further has long test time. In order to reduce the testing cost and improve the testing efficiency, multi-station testing is often adopted. The test of programming time requires high requirements on the architecture of ATE during multi-station parallel test, and each device under test needs to be allocated with an independent processing unit to perform parallel test and parallel processing. The frame structure is high in cost and not widely adopted, so that efficient parallel testing with low cost cannot be realized, serial testing of each station is forced to be carried out under the condition of sacrificing testing efficiency, and testing time is long.
Disclosure of Invention
The invention aims to solve the technical problem that aiming at the defects of the prior art, the memory programming time system for multi-station concurrent testing and the programming method thereof are provided, and the multi-station concurrent testing can be realized at low cost.
In order to achieve the purpose, the technical scheme adopted by the method is as follows: a memory programming time system for multi-station concurrent test is disclosed, the system is connected with a computer through a high-speed bus, and the system comprises a storage unit, a time sequence generator, a data register, a test pattern generator, a serial time sequence generator, a time measuring unit and an electronic pin; the computer timing sequence test system comprises a storage unit, a timing sequence generator, a data register, a serial timing sequence generator, a time measurement unit and an electronic pin, wherein the storage unit, the timing sequence generator and the data register are connected with the computer through a high-speed bus, the timing sequence generator, the test pattern generator and the serial timing sequence generator are sequentially connected, the storage unit is connected with the timing sequence generator and the test pattern generator, the data register is connected with the serial timing sequence generator, the time measurement unit is connected with the electronic pin, the serial timing sequence generator is connected with the time measurement unit and the electronic pin, and the test pattern generator is connected with the time measurement unit. The plurality of electronic pins are respectively connected with the tested device, the plurality of tested devices are respectively distributed with the independent serial timing generator and the independent time measuring unit, and the serial timing generator, the time measuring unit and the electronic pins are controlled by the test pattern generator in a unified mode.
The further improvement of the technical scheme is as follows: the computer implements a function of generating a PATTERN file; the storage unit realizes the function of storing the PATTERN file.
The further improvement of the technical scheme is as follows: the time sequence generator realizes the function of generating the accurate time sequence signal of each test period according to the time sequence requirement specified by the PATTERN file.
The further improvement of the technical scheme is as follows: the data register comprises a sending register and an uploading register, the sending register realizes the function of storing data to be sent, and the uploading register realizes the functions of storing, reading and uploading the data to a computer.
The further improvement of the technical scheme is as follows: the test PATTERN generator realizes the function of generating the control time sequence required by the PATTERN test according to the time sequence requirement specified by the PATTERN file.
The further improvement of the technical scheme is as follows: the serial time sequence generator realizes the operation of loading and assigning values to the data register according to the instruction of the PATTERN file, and is a per-pin structure serial time sequence generator.
The further improvement of the technical scheme is as follows: the time measuring unit realizes the function of generating measuring time and frequency through the triggering of the serial time sequence generator and the test pattern generator, and is a per-pin structure time measuring unit.
The further improvement of the technical scheme is as follows: the electronic pin realizes the function of driving and receiving feedback of the tested device according to the time sequence output level of the PATTERN file, and is of a per-pin structure.
The further improvement of the technical scheme is as follows: the high-speed bus realizes the function of data exchange between the storage unit, the time sequence generator and the data register and the computer.
A memory programming method for multi-station concurrent testing applied to the memory programming time system for multi-station concurrent testing according to any one of claims 1 to 6, the method being used for testing the programming time of a device under test, and comprising the following steps:
s1: before the test is started, connecting a tested device to an electronic pin, determining the test requirement of the tested device corresponding to the test subsystem to be used, and generating a PATTERN file by the computer according to the test requirement;
s2: the computer transmits the PATTERN file to the storage unit through the bus controller;
s3: when programming starts, the time measuring unit is operated and measuring time and frequency required by programming are generated, the time sequence generator generates an accurate time sequence signal of each test period according to the time sequence requirement specified by the PATTERN file, and the test PATTERN generator generates a control time sequence required by testing;
s4: the serial time sequence generator continuously receives the output and the read-write state of the tested device according to the instruction of the PATTERN file through the feedback of the electronic pin until the serial time sequence generator is matched with the read-write bit of the PATTERN file, and the serial time sequence generator obtains the programming time of the tested device;
s5: the time measuring unit stops timing, the serial time sequence generator assigns the programming time to a data register, and the data register uploads the programming time to a computer;
s6: the programming time of the device under test is completed and obtained.
The invention has the following beneficial effects: the invention does not need to provide an independent processor for each tested device, thereby reducing the testing cost; the invention can complete the test of programming time in multiple stations; the invention is controlled by the PATTERN file, and the programming is simple and convenient.
Drawings
The invention will be further described with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
FIG. 2 is a schematic diagram of a device under test connection according to an embodiment of the invention.
Detailed Description
The following description of the embodiments with reference to the accompanying drawings will provide further detailed description of the embodiments of the present invention, such as the mutual positions and connection relationships between the related parts, the functions and working principles of the parts, and the operation and use methods, to help those skilled in the art to more completely, accurately and deeply understand the concept and technical solutions of the present invention.
Examples
As shown in fig. 1, a memory programming time system for multi-station concurrent testing is connected to a computer through a high-speed bus, and comprises a memory unit, a timing generator, a data register, a test pattern generator, a serial timing generator, a time measuring unit and an electronic pin; the storage unit, the time sequence generator and the data register are connected with a computer through a high-speed bus, the time sequence generator, the test pattern generator and the serial time sequence generator are sequentially connected, the storage unit is connected with the time sequence generator and the test pattern generator, the data register is connected with the serial time sequence generator, the time measuring unit is connected with the electronic pin, the serial time sequence generator is connected with the time measuring unit and the electronic pin, and the test pattern generator is connected with the time measuring unit. The plurality of electronic pins are respectively connected with the tested device, the plurality of tested devices are respectively distributed with independent serial time sequence generators and time measuring units, and the serial time sequence generators, the time measuring units and the electronic pins are uniformly controlled by the test pattern generator.
The computer realizes the function of generating the PATTERN file; the storage unit realizes the function of storing the PATTERN file. The timing generator implements the function of generating a precise timing signal for each test period according to the timing requirements specified by the PATTERN file. The data register comprises a sending register and an uploading register, the sending register realizes the function of storing data to be sent, and the uploading register realizes the function of storing and reading data and uploading the data to a computer. The test PATTERN generator implements the function of generating the control timing sequence required by the PATTERN test according to the timing sequence requirement specified by the PATTERN file. The serial time sequence generator realizes the operation of loading and assigning values to the data register according to the instruction of the PATTERN file, and is in a per-pin structure. The time measuring unit realizes the function of generating measuring time and frequency by triggering the serial time sequence generator and the test pattern generator, and is a per-pin structure time measuring unit. The electronic pin realizes the function of driving and receiving feedback of the tested device according to the time sequence output level of the PATTERN file, and is an electronic pin with a per-pin structure. The high-speed bus implements the function of data exchange between the memory cells, the timing generator and the data registers and the computer.
As shown in fig. 2, each of the plurality of devices under test may be assigned a separate serial timing generator (abbreviated SDG) and time measurement unit (abbreviated TMU), such as a first device under test, a second device under test, and a third device under test, connected to the first electronic pin, the second electronic pin, and the third electronic pin, respectively, and assigned the first serial timing generator and the first time measurement unit, the second serial timing generator and the second time measurement unit, the third serial timing generator and the third time measurement unit, respectively. And then, uniformly controlling by a test pattern generator to realize the test of the multi-station programming time.
Table 1 below is an example of a patern file:
in table 1, (1) is a Pattern Head command for defining external file information referenced by a Pattern file. (2) The instruction name of the Pattern file is used for controlling the execution sequence of the test Pattern generator. (3) Is the time sequence code of Pattern file, each time sequence code can define a group of information, including period, time edge, waveform, etc. (4) The channel data of the Pattern file is provided, each column represents a channel, each symbol represents a channel level, wherein 1 is a high level, and 0 is a low level, and the channel data are used for the input of a tested device; h is high level, L is low level, and is used for comparing with the output of the tested device; x is not of interest.
A memory programming method of multi-station concurrent test applied to a memory programming time system of multi-station concurrent test is used for testing the programming time of a tested device and comprises the following steps:
s1: before the test starts, connecting the tested device to the electronic pin, determining the test requirement of the tested device corresponding to the test subsystem to be used, and generating a PATTERN file by the computer according to the test requirement;
s2: the computer transmits the PATTERN file to the storage unit through the bus controller;
s3: when programming starts, the time measuring unit is operated and measuring time and frequency required by programming are generated, the time sequence generator generates an accurate time sequence signal of each test period according to the time sequence requirement specified by the PATTERN file, and the test PATTERN generator generates a control time sequence required by testing;
s4: the serial time sequence generator continuously receives the output and the read-write state of the tested device according to the instruction of the PATTERN file through the feedback of the electronic pin until the serial time sequence generator is matched with the read-write bit of the PATTERN file, and the serial time sequence generator obtains the programming time of the tested device;
s5: the time measuring unit stops timing, the serial time sequence generator assigns the programming time to a data register, and the data register uploads the programming time to a computer;
s6: the programming time of the device under test is completed and obtained.
The present invention is not limited to the above embodiments, and any technical solutions formed by equivalent substitutions fall within the scope of the claims of the present invention.
Claims (2)
1. A memory programming time system for multi-station concurrent test is connected with a computer through a high-speed bus, and is characterized in that: the system comprises a storage unit, a time sequence generator, a data register, a test pattern generator, a serial time sequence generator, a time measuring unit and an electronic pin; the memory unit, the time sequence generator and the data register are connected with the computer through a high-speed bus, the time sequence generator, the test pattern generator and the serial time sequence generator are sequentially connected, the memory unit is connected with the time sequence generator and the test pattern generator, the data register is connected with the serial time sequence generator, the time measuring unit is connected with the electronic pin, the serial time sequence generator is connected with the time measuring unit and the electronic pin, and the test pattern generator is connected with the time measuring unit; the plurality of electronic pins are respectively connected with a device to be tested, the plurality of devices to be tested are respectively distributed with the independent serial timing generator and the independent time measuring unit, and the serial timing generator, the time measuring unit and the electronic pins are uniformly controlled by the test pattern generator;
the computer implements a function of generating a PATTERN file; the storage unit realizes the function of storing the PATTERN file;
the time sequence generator realizes the function of generating an accurate time sequence signal of each test period according to the time sequence requirement specified by the PATTERN file;
the data register comprises a sending register and an uploading register, the sending register realizes the function of storing data to be sent, and the uploading register realizes the functions of storing, reading and uploading the data to a computer;
the test PATTERN generator realizes the function of generating a control time sequence required by PATTERN test according to the time sequence requirement specified by the PATTERN file;
the serial time sequence generator is used for loading and assigning the data register according to an instruction of the PATTERN file, and is of a per-pin structure;
the time measuring unit realizes the function of generating measuring time and frequency by triggering the serial time sequence generator and the test pattern generator, and is a per-pin structure time measuring unit;
the electronic pin realizes the function of driving and receiving feedback of the tested device by the PATTERN file according to time sequence output level, and is of a per-pin structure;
the high-speed bus realizes the function of data exchange between the storage unit, the time sequence generator and the data register and the computer.
2. A memory programming method for multi-station concurrent testing applied to the memory programming time system for multi-station concurrent testing according to claim 1, the method is used for testing the programming time of a device under test, and is characterized by comprising the following steps:
s1: before the test is started, connecting the tested device to the electronic pin, determining the test requirement of the tested device corresponding to the test subsystem to be used, and generating a PATTERN file by the computer according to the test requirement;
s2: the computer transmits the PATTERN file to the storage unit through the high-speed bus;
s3: when programming starts, the time measuring unit is operated and measuring time and frequency required by programming are generated, the time sequence generator generates an accurate time sequence signal of each test period according to the time sequence requirement specified by the PATTERN file, and the test PATTERN generator generates a control time sequence required by PATTERN test;
s4: the serial time sequence generator continuously receives the output and the read-write state of the tested device according to the instruction of the PATTERN file through the feedback of the electronic pin until the serial time sequence generator is matched with the read-write bit of the PATTERN file, and the serial time sequence generator obtains the programming time of the tested device;
s5: the time measuring unit stops timing, the serial time sequence generator assigns the programming time to a data register, and the data register uploads the programming time to a computer;
s6: the programming time of the device under test is completed and obtained.
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