CN113676182B - MDAC circuit for reducing mismatch error by channel randomization - Google Patents

MDAC circuit for reducing mismatch error by channel randomization Download PDF

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CN113676182B
CN113676182B CN202110820818.8A CN202110820818A CN113676182B CN 113676182 B CN113676182 B CN 113676182B CN 202110820818 A CN202110820818 A CN 202110820818A CN 113676182 B CN113676182 B CN 113676182B
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sampling
channel
switch
capacitor
reset
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CN113676182A (en
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郭瑞
初飞
王宗民
张铁良
冯文晓
靳翔
纪亚飞
邴兆航
方贤朋
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
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Abstract

A MDAC circuit for reducing mismatch errors by channel randomization comprises a four-channel sampling switch capacitor array and a margin amplifier module, wherein in a sampling stage, an input signal is sampled by randomly selecting one channel from the four-channel sampling switch capacitor array, and the mismatch errors of the capacitors are averaged, so that the influence of mismatch on the circuit is reduced. According to the invention, a plurality of sampling switch capacitor array channels are designed, and one channel is randomly selected to sample an input signal in each working period of the allowance amplifier, so that the effect of reducing capacitance mismatch errors is achieved, and the performances of the whole MDAC and the analog-to-digital converter are improved.

Description

MDAC circuit for reducing mismatch error by channel randomization
Technical Field
The invention relates to an MDAC design of a pipeline analog-to-digital converter, in particular to an MDAC circuit for reducing capacitance mismatch errors by channel randomization, and belongs to the field of analog-to-digital converters.
Background
In the design of pipeline analog-to-digital converter, the MDAC circuit is usually implemented by a switched capacitor circuit, in an actual circuit, due to process deviation and the like, a capacitance value deviates from an ideal value in the manufacturing process, so that the output of the MDAC is affected, namely, a transmission curve of the MDAC is affected by capacitance mismatch, and the output error of the MDAC is caused, so that the linearity of the whole ADC is affected.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an MDAC circuit with a randomized channel for reducing capacitance mismatch errors, which is used for improving the performance of the whole MDAC and an analog-to-digital converter.
The above object of the present invention is mainly achieved by the following technical solutions:
the MDAC circuit comprises a four-channel sampling switch capacitor array and a residual amplifier module, wherein in a sampling stage, one channel is randomly selected from the four-channel sampling switch capacitor array to sample an input signal, and at most one sampling is carried out on the same channel in three continuous sampling periods, and the sampled signal is sent to the residual amplifier module to be amplified and output, so that mismatch error averaging is realized, and the influence of the mismatch error on the circuit is reduced.
The four-channel sampling switch capacitor array consists of four sampling switch capacitor arrays with identical structures;
the sampling switch capacitor array of the m-th channel includes sampling switches sws_pm and sws_nm, sampling capacitors csp_m and csn_m, reference level switches swdi_pm and swdj_nm, capacitance reset switches swr_m and swc_m and swh_m, and transfer switches swt_pm and swt_nm; m=1, 2,3,4;
the first end of the sampling capacitor CSP_m is connected with one end of a sampling switch SWS_Pm and one end of a reference level switch SWDi_Pm at the same time, the other end of the sampling switch SWS_Pm is connected with an input signal VP, and the other end of the reference level switch SWDi_Pm is connected with a reference voltage Di, i=0 or 1; the first end of the sampling capacitor CSN_m is connected with one end of the sampling switch SWS_Nm and one end of the reference level switch SWDj_Nm at the same time, the other end of the sampling switch SWS_Nm is connected with the input signal VN, and the other end of the reference level switch SWDj_Nm is connected with the reference voltage Dj, j=0 or 1;
the first end of the sampling capacitor CSP_m is connected with the first end of the CSN_m through a capacitor reset switch SWR_m, the second end of the sampling capacitor CSP_m is simultaneously connected with one ends of capacitor reset switches SWC_m and SWH_m and a transmission switch SWT_Pm, the second end of the sampling capacitor CSN_m is simultaneously connected with the other ends of the capacitor reset switches SWC_m and SWH_m, one end of the transmission switch SWT_Nm is connected with the second end of the sampling capacitor CSN_m, the other end of the transmission switch SWT_Pm is used as the positive output end of the sampling switch capacitor array of the m-th channel to be connected with the positive input end of the residual amplifier module, and the other end of the transmission switch SWT_Nm is used as the negative output end of the sampling switch capacitor array of the m-th channel to be connected with the negative input end of the residual amplifier module.
Reference voltage D0 represents a low reference level, and reference voltage D1 represents a high reference level;
when i=0, j=1; when i=1, j=0.
In one working period of the residual amplifier module, in the sampling switch capacitor arrays of four channels, the sampling switch capacitor array of one channel works at a sampling time sequence, the sampling switch capacitor array of one channel works at a holding time sequence, and the sampling switch capacitor arrays of the remaining two channels work at a resetting time sequence;
in the sampling switch capacitor array of the m-th channel, SWS_Pm, SWS_Nm and SWH_m are only turned on at sampling time sequences and turned off at other time sequences; the switches SWDi_Pm, SWDj_Nm, SWT_Pm and SWT_Nm are only turned on at the maintaining time sequence and turned off at other time sequences; the switches swr_m and swc_m are turned on only at the reset timing and turned off at other timings.
For the sampling switch capacitor array of each channel, the sampling time sequence and the holding time sequence are non-overlapped clock phases, and the interval between the holding time sequence and the sampling time sequence is one working period of the margin amplifier module; the reset sequence occurs before each sampling sequence begins.
The residual amplifier module is of a differential structure and comprises an input reset switch SWA_IN, an output reset switch SWA_OUT, feedback capacitors CF1 and CF2 and an amplifier AMP;
the positive input end of the amplifier AMP is simultaneously connected with a reset switch SWA_IN and one end of a feedback capacitor CF1, the other end of the reset switch SWA_IN is simultaneously connected with the negative input end of the amplifier AMP and one end of a feedback capacitor CF2, the negative output end of the amplifier AMP is simultaneously connected with the other end of the feedback capacitor CF1 and one end of an output reset switch SWA_OUT, and the positive output end of the amplifier AMP is simultaneously connected with the other end of the feedback capacitor CF2 and the other end of the output reset switch SWA_OUT;
the positive input end of the amplifier AMP is used as the positive input end of the allowance amplifier module, and the negative input end of the amplifier AMP is used as the negative input end of the allowance amplifier module; the positive output of the amplifier AMP serves as the positive output of the headroom amplifier module, and the negative output of the amplifier AMP serves as the negative output of the headroom amplifier module.
At the beginning of each working period of the allowance amplifier module, the amplifier AMP receives a reset signal phi A When the reset phase is started, resetting the input end and the output end; and amplifying and outputting the received signal at other moments of the working period.
The reset switches swa_in and swa_out are only IN the reset phase Φ of the amplifier AMP A On, off at other times.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the invention, on the basis of an MDAC structure, a four-channel sampling switch capacitor array and a residual amplifier structure are adopted, and the capacitor mismatch error is reduced through random sampling work of the four-channel sampling switch capacitor array.
(2) The multi-channel sampling switch capacitor array adopted by the invention has the advantages that the structures of all channels are completely consistent, the proper sampling switch capacitor array can be designed according to the system requirements, and then the design of the multi-channel sampling switch capacitor array is carried out, so that the technical portability is strong.
(3) The invention designs the matched time sequence signals according to the channel condition, and has large design space.
Drawings
FIG. 1 is a schematic diagram of an MDAC circuit for reducing mismatch error by channel randomization in accordance with the present invention;
FIG. 2 is a schematic diagram of the overall MDAC operation sequence according to the present invention;
FIG. 3 shows the overall MDAC at phi A A phase circuit schematic;
FIG. 4 shows the overall MDAC sampling phase Φ of the present invention S A schematic circuit diagram;
FIG. 5 shows the overall MD of the present inventionAC hold phase Φ H Schematic of the circuit.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
the invention provides a four-channel sampling switch capacitor array MDAC circuit, which reduces the mismatch of MDAC capacitors through channel randomization, thereby improving the performance of the whole assembly line analog-to-digital converter.
As shown in fig. 1, the MDAC circuit of the present invention is composed of a four-way sampling switched capacitor array 100 and a margin amplifier module 200. In the sampling stage, one channel is randomly selected from the four-channel sampling switch capacitor array to sample an input signal, and the mismatch error of the sampling capacitor is averaged, so that the influence of the mismatch of the capacitor on a circuit is reduced.
The four-channel sampling switched capacitor array 100 is composed of four sampling switched capacitor arrays having identical structures, and the mth-channel sampling switched capacitor array includes sampling switches sws_pm (m=1, 2,3,4. It is set here that m=1 represents the first-channel sampling switched capacitor array, m=2 represents the second-channel sampling switched capacitor array, m=3 represents the third-channel sampling switched capacitor array, and m=4 represents the fourth-channel sampling switched capacitor array.) and sws_nm, sampling capacitors csp_m and csn_m, reference level switches swdi_pm and swdj_nm, capacitor reset switches swr_m and swc_m and swh_m, and transmission switches swt_pm and swt_nm.
The first end of the sampling capacitor CSP_m is connected with one end of the sampling switch SWS_Pm and one end of the reference level switch SWDi_Pm at the same time, the other end of the sampling switch SWS_Pm is connected with the input signal VP, the other end of the reference level switch SWDi_Pm is connected with the reference voltage Di (i=0, 1, D0 represents a low reference level, and D1 represents a high reference level); the first terminal of the sampling capacitor csn_m is simultaneously connected to one terminal of the sampling switch sws_nm and one terminal of the reference level switch swdj_nm, the other terminal of the sampling switch sws_nm is connected to the input signal VN, and the other terminal of the reference level switch swdj_nm is connected to the reference voltage Dj. When i=0, j=1; when i=1, j=0.
The first end of the sampling capacitor CSP_m is connected with the first end of the CSN_m through a capacitor reset switch SWR_m, a parallel circuit of the capacitor reset switches SWC_m and SWH_m is connected between the second end of the sampling capacitor CSP_m and the second end of the CSN_m, meanwhile, the second end of the sampling capacitor CSP_m is connected with one end of a transmission switch SWT_Pm, and the second end of the sampling capacitor CSN_m is connected with one end of the transmission switch SWT_Nm.
The other ends of the transmission switches SWT_Pm of the four sampling switch capacitor arrays with the same structure are connected to form a positive output end and connected with the positive input end of the amplifier AMP, and the other ends of the transmission switches SWT_Nm of the four sampling switch capacitor arrays with the same structure are connected to form a negative output end and connected with the negative input end of the amplifier AMP.
The margin amplifier module 200 is of a differential structure, and is composed of an input reset switch swa_in, an output reset switch swa_out, feedback capacitors CF1 and CF2, and an amplifier AMP.
The differential input ends of the amplifier AMP are connected through an input reset switch SWA_IN, the differential output ends of the amplifier AMP are connected through an output reset switch SWA_OUT, a feedback capacitor CF1 is connected between the positive input end and the negative output end of the amplifier AMP, a feedback capacitor CF2 is connected between the negative input end and the positive output end, and the positive output end of the amplifier AMP is used for outputting V OUTP The negative output of the amplifier AMP is used for outputting V OUTN 。
As shown in FIG. 2, the operation sequence of the whole MDAC is mainly composed of three sequences phi of four-channel sampling switch capacitor arrays S _m、Φ H M and phi C M, and the reset clock Φ of the amplifier AMP A Composition is prepared.
The timing of the sampling switch capacitor array of the m-th channel comprises a sampling timing phi S M and hold timing Φ H M, and reset timing Φ of the sampling capacitance C M. For each channel Φ S M and phi H M is the non-overlapping clock phase, Φ H M and phi S One duty cycle, Φ, of m-spaced margin amplifier modules C M is only at each sampling timing Φ S M occurs before the start; one duty cycle for the amplifier AMP is T A At each working period T A At the beginning have oneReset signal phi A The amplifier AMP is at reset timing Φ A Resetting the input and output, and amplifying and outputting at other moments; for the whole MDAC, sampling time sequence phi of four channels S_ 1、Φ S_ 2、Φ S_ 3、Φ S_ 4 are randomly generated and satisfy: at each working period T of the amplifier AMP A In which a sampling switched capacitor array with only one channel samples the input signal and in three successive operating periods T A The same channel is sampled at most once.
Specifically, the switches SWS_P1, SWS_N1, SWH_1 are only in the sampling phase Φ S_ 1 is turned on and turned off at other moments; switches SWDi_P1, SWDj_N1, SWT_P1, SWT_N1 are only in hold phase Φ H_ 1 is turned on and turned off at other moments; the switches SWR_1 and SWC_1 are only in the capacitance reset phase phi C_ 1 is on and off at other times. The switches SWS_P2, SWS_N2, SWH_2 are only in the sampling phase Φ S_ 2, switching on and switching off at other moments; switches SWDi_P2, SWDj_N2, SWT_P2, SWT_N2 are only in hold phase Φ H_ 2, switching on and switching off at other moments; the switches SWR_2 and SWC_2 are only in the capacitance reset phase phi C_ 2 is on and off at other times. The switches SWS_P3, SWS_N3, SWH_3 are only in the sampling phase Φ S_ 3, switching on and switching off at other moments; switches SWDi_P3, SWDj_N3, SWT_P3, SWT_N3 are only in hold phase Φ H_ 3, switching on and switching off at other moments; the switches SWR_3 and SWC_3 are only in the capacitance resetting phase phi C_ 3 is turned on and turned off at other times. The switches SWS_P4, SWS_N4, SWH_4 are only in the sampling phase Φ S_ 4, switching on and switching off at other moments; switches SWDi_P4, SWDj_N4, SWT_P4, SWT_N4 are only in hold phase Φ H_ 4, switching on and switching off at other moments; the switches SWR_4 and SWC_4 are only in the capacitance resetting phase phi C_ 4 is turned on and turned off at other times. The switches swa_in and swa_out are only IN the reset phase Φ of the amplifier AMP A On, off at other times.
The sampling time sequence of the four channels is a random time sequence in actual working, fig. 2 is a time sequence diagram, taking the stage of sampling 6 in which the first channel in fig. 2 samples the input signal as an example, and explaining the working condition of the whole MDAC.
As shown in fig. 3, taking the sample 6 stage of the first channel preparation as an example, the reset clock Φ of the amplifier AMP A Under the condition, the switches SWA_IN and SWA_OUT are conducted and are controlled by the phase phi S _1、Φ S _2、Φ S _3、Φ S 4, and phi H _1、Φ H _2、Φ H _3、Φ H The switch controlled by_4 is turned off, the first sampling switch capacitor array is ready for sampling, and the reset switch phi is used for resetting C Switch conduction controlled by phi 1 C _2、Φ C _3、Φ C The switch controlled by_4 is turned off. In the four-channel sampling switched capacitor array 100, swr_1 and swc_1 are turned on, all the other switches are turned off, one end of csp_1 is connected to one end of csn_1 through swr_1, and the other end of csp_1 is connected to the other end of csn_1 through swc_1. IN the margin amplifier module 200, the switches swa_in and swa_out are turned off, the positive input terminal and the negative input terminal of the amplifier AMP are connected, and the positive output terminal and the negative output terminal are connected. And the positive input end is connected with the negative output end through a feedback capacitor CF1, and the negative input end is connected with the positive output end through a feedback capacitor CF 2.
As shown in fig. 4, taking the example that the first channel enters the sampling 6 stage, the first channel samples the sampling timing Φ of the switched capacitor array S_ Under 1, from the phase phi S_ 1 and phi H_ 3, by phase phi S_ 2、Φ S_ 3、Φ S_ 4、Φ H_ 1、Φ H_ 2、Φ H_ 4、Φ C_ 1、Φ C_ 2、Φ C_ 3、Φ C_ 4 and phi A The controlled switch is turned off. One ends of the sampling capacitors CSP_1 and CSN_1 are respectively connected to the inputs VP and VN of the MDAC, and the other ends of the sampling capacitors CSP_1 and CSN_1 are short-circuited together through a switch SWH_1. One ends of the sampling capacitors csp_3 and csn_3 are connected to the reference signal D0 or D1, respectively. The specific connection to which reference level is determined by the digital code generated by the DAC in the pipeline stage, the digital code being only in the case of both 0 and 1. Here, when the digital code is set to 0, csp_m is connected to D0, csn_m is connected to D1, and when the digital code is set to 1, csp_m is connected to D1, csn_m is connected to D0, and the opposite is true. CollectingThe other end of the sampling capacitor CSN_3 is connected with the positive input end of the amplifier through a switch SWT_P1, and the other end of the sampling capacitor CSN_3 is connected with the negative input end of the amplifier through a switch SWT_N1. The positive input terminal of the residual amplifier AMP is connected to the negative output terminal through a feedback capacitor CF1, and the negative input terminal is connected to the positive output terminal through a feedback capacitor CF 2.
As shown in fig. 5, the sample 6 phase is completed with the first channel, and the hold phase Φ is entered H For example, 1, the hold timing Φ of the sample switched capacitor array of the first channel H_ Under 1, from the phase phi H_ 1 and phi S_ 4, by phase phi S_ 1、Φ S_ 2、Φ S_ 3、Φ H_ 2、Φ H_ 3、Φ H_ 4、Φ C_ 1、Φ C_ 2、Φ C_ 3、Φ C_ 4 and phi A The controlled switch is turned off. One ends of the sampling capacitors csp_1 and csn_1 are connected to the reference signal D0 or D1, respectively. The other end of the sampling capacitor CSN_1 is connected with the positive input end of the amplifier through a switch SWT_P1, and the other end of the sampling capacitor CSN_1 is connected with the negative input end of the amplifier through a switch SWT_N1. One ends of the sampling capacitors CSP_4 and CSN_4 are respectively connected to the inputs VP and VN of the MDAC, and the other ends of the sampling capacitors CSP_4 and CSN_4 are short-circuited together through a switch SWH_1. The positive input terminal of the residual amplifier AMP is connected to the negative output terminal through a feedback capacitor CF1, and the negative input terminal is connected to the positive output terminal through a feedback capacitor CF 2.
Sampling timing Φ of four channels in multiple successive duty cycles S_ 1、Φ S_ 2、Φ S_ 3、Φ S_ 4 is random, and the sampling switch capacitor array is selected from the four-channel sampling switch capacitor array to sample the input signal, so that mismatch errors existing in the sampling capacitors in the actual circuit are averaged, mismatch accumulation caused by continuous sampling of the same sampling capacitor array is reduced, and the effect of reducing the mismatch errors of the MDAC capacitors is achieved.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.

Claims (5)

1. An MDAC circuit for reducing mismatch error by channel randomization, comprising: the four-channel sampling switch capacitor array comprises a four-channel sampling switch capacitor array (100) and a residual amplifier module (200), wherein in a sampling stage, one channel is randomly selected from the four-channel sampling switch capacitor array to sample an input signal, and the same channel is only sampled once at most in three continuous sampling periods, and the sampled signal is sent to the residual amplifier module (200) to be amplified and output, so that mismatch error averaging is realized, and the influence of the mismatch error on a circuit is reduced;
the four-channel sampling switch capacitor array (100) consists of four sampling switch capacitor arrays with identical structures;
the sampling switch capacitor array of the m-th channel includes sampling switches sws_pm and sws_nm, sampling capacitors csp_m and csn_m, reference level switches swdi_pm and swdj_nm, capacitance reset switches swr_m and swc_m and swh_m, and transfer switches swt_pm and swt_nm; m=1, 2,3,4;
the first end of the sampling capacitor CSP_m is connected with one end of a sampling switch SWS_Pm and one end of a reference level switch SWDi_Pm at the same time, the other end of the sampling switch SWS_Pm is connected with an input signal VP, and the other end of the reference level switch SWDi_Pm is connected with a reference voltage Di, i=0 or 1; the first end of the sampling capacitor CSN_m is connected with one end of the sampling switch SWS_Nm and one end of the reference level switch SWDj_Nm at the same time, the other end of the sampling switch SWS_Nm is connected with the input signal VN, and the other end of the reference level switch SWDj_Nm is connected with the reference voltage Dj, j=0 or 1;
the first end of the sampling capacitor CSP_m is connected with the first end of the CSN_m through a capacitor reset switch SWR_m, the second end of the sampling capacitor CSP_m is simultaneously connected with one ends of capacitor reset switches SWC_m and SWH_m and a transmission switch SWT_Pm, the second end of the sampling capacitor CSN_m is simultaneously connected with the other ends of the capacitor reset switches SWC_m and SWH_m, one end of the transmission switch SWT_Nm is connected with the second end of the sampling capacitor CSN_m, the other end of the transmission switch SWT_Pm is used as the positive output end of the sampling switch capacitor array of the m-th channel to be connected with the positive input end of the residual amplifier module (200), and the other end of the transmission switch SWT_Nm is used as the negative output end of the sampling switch capacitor array of the m-th channel to be connected with the negative input end of the residual amplifier module (200);
reference voltage D0 represents a low reference level, and reference voltage D1 represents a high reference level;
when i=0, j=1; when i=1, j=0;
in one working period of the residual amplifier module (200), in the sampling switch capacitor arrays of four channels, the sampling switch capacitor array of one channel works at a sampling time sequence, the sampling switch capacitor array of one channel works at a holding time sequence, and the sampling switch capacitor arrays of the remaining two channels work at a resetting time sequence;
in the sampling switch capacitor array of the m-th channel, SWS_Pm, SWS_Nm and SWH_m are only turned on at sampling time sequences and turned off at other time sequences; the switches SWDi_Pm, SWDj_Nm, SWT_Pm and SWT_Nm are only turned on at the maintaining time sequence and turned off at other time sequences; the switches swr_m and swc_m are turned on only at the reset timing and turned off at other timings.
2. The MDAC circuit of claim 1, wherein the channel randomization reduces mismatch errors, wherein: for each channel of the switched capacitor array, the sampling timing and the holding timing are non-overlapping clock phases, the holding timing and the sampling timing being separated by a duty cycle of the margin amplifier module (200); the reset sequence occurs before each sampling sequence begins.
3. The MDAC circuit of claim 2, wherein the channel randomization reduces mismatch errors, wherein: the residual amplifier module (200) is of a differential structure and comprises an input reset switch SWA_IN, an output reset switch SWA_OUT, feedback capacitors CF1 and CF2 and an amplifier AMP;
the positive input end of the amplifier AMP is simultaneously connected with a reset switch SWA_IN and one end of a feedback capacitor CF1, the other end of the reset switch SWA_IN is simultaneously connected with the negative input end of the amplifier AMP and one end of a feedback capacitor CF2, the negative output end of the amplifier AMP is simultaneously connected with the other end of the feedback capacitor CF1 and one end of an output reset switch SWA_OUT, and the positive output end of the amplifier AMP is simultaneously connected with the other end of the feedback capacitor CF2 and the other end of the output reset switch SWA_OUT;
the positive input of the amplifier AMP is used as the positive input of the allowance amplifier module (200), and the negative input of the amplifier AMP is used as the negative input of the allowance amplifier module (200); the positive output of the amplifier AMP serves as the positive output of the residual amplifier module (200), and the negative output of the amplifier AMP serves as the negative output of the residual amplifier module (200).
4. A channel randomization reduced mismatch error MDAC circuit according to claim 3, wherein: at the beginning of each working period of the residual amplifier module (200), the amplifier AMP receives a reset signal phi A When the reset phase is started, resetting the input end and the output end; and amplifying and outputting the received signal at other moments of the working period.
5. The MDAC circuit of claim 4, wherein said MDAC circuit is configured to reduce mismatch errors by channel randomization: the reset switches swa_in and swa_out are only IN the reset phase Φ of the amplifier AMP A On, off at other times.
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Citations (1)

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Publication number Priority date Publication date Assignee Title
CN110233623A (en) * 2019-04-25 2019-09-13 北京时代民芯科技有限公司 A kind of circuit applied to MDAC alignment common-mode voltage

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CN103178852B (en) * 2013-03-20 2016-05-11 中国电子科技集团公司第二十四研究所 A kind of high-speed sampling front-end circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110233623A (en) * 2019-04-25 2019-09-13 北京时代民芯科技有限公司 A kind of circuit applied to MDAC alignment common-mode voltage

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