CN113675087B

CN113675087B - Semiconductor structure and forming method thereof

Info

Publication number: CN113675087B
Application number: CN202010406717.1A
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-05-14
Filing date: 2020-05-14
Publication date: 2024-03-19
Anticipated expiration: 2040-05-14
Also published as: CN113675087A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate, and the drift region is provided with a drain region; forming a grid structure on the substrate at the junction of the well region and the drift region; forming a silicide blocking material layer on the gate structure and the exposed substrate of the gate structure; doping ions in the silicide blocking material layer, wherein the doping ions are doped at the bottom of the silicide blocking material layer; and patterning the silicide blocking material layer to form a silicide blocking layer on the drift region between the drain region and the gate structure. The doped ions are combined with the dangling bond at the bottom of the silicide blocking material layer to form a saturated bond, so that the electric charge of the interface at the bottom of the silicide blocking material layer can be reduced, and the ions doped at the bottom of the silicide blocking material layer have own electric field, so that the original electric field line distribution in the silicide blocking layer can be disturbed, and the electric charge in the silicide blocking layer is not easy to enter the drift region, so that the breakdown voltage of the semiconductor structure is higher.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In the development of power integrated circuits, a single chip process developed for integrating a power switch and a control circuit, especially a lateral double diffused metal oxide semiconductor (lateral double diffusion MOS, LDMOS) process currently used for fabricating monolithic integrated circuits, is a mainstream trend. The LDMOS process is to perform planar diffusion (planar diffusion) on the surface of the semiconductor substrate to form a lateral main current path, and because the LDMOS is manufactured by a typical IC process, the control circuit and the LDMOS can be integrated on a monolithic power IC, and the LDMOS process can achieve the goal of high voltage and low on-resistance by using a surface electric field reduction (reduced surface electric field, RESURE) technique and a low thickness epitaxy (BPI) or N-well (N-well).

An LDMOS device is a field effect transistor device (FET) that approximates a conventional Field Effect Transistor (FET) device, and includes a pair of source/drain regions separated by a channel region formed in a semiconductor substrate and a gate electrode formed in turn over the channel region, however, unlike conventional FET devices in which a pair of source/drain regions are made symmetrical to the gate electrode, a drain region in the LDMOS device is farther from the gate electrode than the source region, and the drain region is simultaneously formed in a doped well (having the same polarity as the drain region) that separates the channel region from the drain region.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent to each other are formed in the substrate, and the drift region is provided with a drain region; forming a grid structure on the substrate at the junction of the well region and the drift region; forming a drain electrode in the drain region; forming a silicide blocking material layer on the gate structure and the substrate exposed by the gate structure; doping ions in the silicide blocking material layer, wherein the doping ions are doped at the bottom of the silicide blocking material layer; and after doping ions, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the gate structure.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: a substrate, wherein the substrate is internally provided with a well region and a drift region which are adjacent; the grid structure is positioned on the substrate at the junction of the well region and the drift region; the drain electrode is positioned in the drift region at one side of the gate structure; and the silicide blocking layer is positioned on the drift region between the gate structure and the drain electrode, doped ions are arranged in the silicide blocking layer, and the doped ions are positioned at the bottom of the silicide blocking layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure of the embodiment of the invention, a well region and a drift region which are adjacent are arranged in a substrate, and a grid structure is formed on the substrate at the junction of the well region and the drift region; forming a silicide blocking material layer on the gate structure and the substrate exposed by the gate structure; the method comprises the steps that ions are doped in the silicide blocking material layer, the doped ions are doped at the bottom of the silicide blocking material layer, the doped ions are combined with dangling bonds on the bottom surface of the silicide blocking material layer to form saturated bonds, and accordingly charges on the bottom surface of the silicide blocking material layer can be reduced, so that when a semiconductor structure works, the coupling effect of carriers in a drift region and charges on the bottom of the silicide blocking layer is small, charges in the corresponding silicide blocking layer are not easy to enter the drift region, breakdown voltage of the semiconductor structure is high, and electrical performance of the semiconductor structure is improved; and the ions doped at the bottom of the silicide blocking material layer have own electric field, so that the original electric field line distribution in the silicide blocking layer can be disturbed, the electric field lines in the silicide blocking layer are not easy to couple into the drift region below the silicide blocking layer, and charges in the silicide blocking layer are not easy to enter into the drift region below the silicide blocking layer, so that the breakdown voltage of the semiconductor structure is higher, and the electrical property of the semiconductor structure is further improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 12 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;

fig. 13 is a schematic diagram illustrating a method of forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As can be seen from the background art, the semiconductor structure formed at present still has the problem of poor electrical performance. The reason for the poor performance of the semiconductor structure is analyzed by combining a forming method of the semiconductor structure.

Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure shows a design of a high voltage LDMOS, the semiconductor structure comprising: a substrate 10, wherein a well region 11 and a drift region 12 are formed in the substrate 10; a gate structure 20 located on the substrate 10 at the junction of the well region 11 and the drift region 12, wherein the gate structure 20 includes a gate oxide layer 21 and a gate layer 22 located on the gate oxide layer 21; a source region 31 located in the well region 11 at one side of the gate structure 20; a drain region 32 located in the drift region 12 on the other side of the gate structure 20; a silicide blocking layer 33 on the substrate 10 between the gate structure 20 and the drain region 32, the silicide blocking layer 33 further extending to a sidewall and a portion of a top of the gate structure 20 on a side near the drain region 32; a dielectric layer (not shown) on the substrate 10 where the gate structure 20 is exposed, the dielectric layer also covering the gate structure 20; a first Contact (CT) plug 40 located within the dielectric layer, the first contact plug 40 being electrically connected to the gate layer 22, drain region 32 or source region 31; a second contact plug 41 in the dielectric layer, the second contact plug 41 being connected to the silicide blocking layer 33 on the drift region 12.

Taking an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOS) as an example, when the device is in operation, current flows from the drain region 32 into the channel under the gate structure 20, positive charges are accumulated in the drift region 12 under the second contact plug 41, negative charges are accumulated at the bottom of the silicide blocking layer 33 under the action of an electric field between the drain region 32 and the gate structure 20, the negative charges in the silicide blocking layer 33 are coupled with the positive charges in the drift region 12, breakdown is likely to occur at the silicide blocking layer 33, and the breakdown voltage of the N-type lateral double-diffused metal oxide semiconductor field effect transistor is small.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent to each other are formed in the substrate, and the drift region is provided with a drain region; forming a grid structure on the substrate at the junction of the well region and the drift region; forming a drain electrode in the drain region; forming a silicide blocking material layer on the gate structure and the substrate exposed by the gate structure; doping ions in the silicide blocking material layer, wherein the doping ions are doped at the bottom of the silicide blocking material layer; and after doping ions, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the gate structure.

In the semiconductor structure of the embodiment of the invention, a substrate is provided with a well region and a drift region which are adjacent to each other; the grid structure is positioned on the substrate at the junction of the well region and the drift region; the drain electrode is positioned in the drift region at one side of the gate structure; and the silicide blocking layer is positioned on the drift region between the gate structure and the drain region, doped ions are arranged in the silicide blocking layer, and the doped ions are positioned at the bottom of the silicide blocking layer.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.

Fig. 2 to 12 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention, and the method for forming a semiconductor structure according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Referring to fig. 2, a substrate 100 is provided, and a well region 101 and a drift region 102 are formed adjacent to each other in the substrate 100, and the drift region 102 has a drain region (not shown in the drawing) therein.

The substrate 100 is used to provide a process platform for the subsequent formation of LDMOS. In this embodiment, taking the LDMOS as a planar transistor as an example, the substrate 100 is correspondingly a planar substrate. In other embodiments, when the LDMOS is a fin field effect transistor, the base correspondingly includes a substrate and a discrete fin located on the substrate.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, or other materials, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

The drift region 102 is doped with first type ions, the well region 101 is doped with second type ions, the conductivity types of the first type ions and the second type ions are different, the well region 101 and the drift region 102 are in contact, and the well region 101 serves as a lateral diffusion region to form a channel with a concentration gradient.

Specifically, in this embodiment, when the semiconductor structure is used to form the NLDMOS, the drift region 102 has N-type ions, where the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions, and the well region 101 has P-type ions, where the P-type ions include one or more of boron ions, gallium ions, and indium ions.

In other embodiments, when the semiconductor structure is used to form a PLDMOS, the drift region has P-type ions therein, where the P-type ions include one or more of boron ions, gallium ions, and indium ions, and the well region 101 has N-type ions therein, where the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

The step of forming the well region 101 and the drift region 102 includes: forming a first implantation mask layer (not shown) which covers the substrate 100 to be formed with the drift region and exposes the substrate 100 to be formed with the well region; doping second type ions into the substrate exposed by the first implantation mask layer to form a well region 101; after forming the well region 101, forming the substrate 100 which covers the well region 101 and exposes the drift region to be formed; and doping the substrate 100 exposed by the second implantation mask layer with first type ions to form the drift region 102.

In the embodiment of the present invention, the second type ions are doped into the substrate 100 exposed by the first implantation mask layer by using an ion implantation method, so as to form the well region 101. The ion implantation has the characteristics of simple operation, low process cost and the like.

In the embodiment of the present invention, the first type ions are doped into the substrate 100 exposed by the second implantation mask layer by using an ion implantation method, so as to form the drift region 102. The ion implantation has the characteristics of simple operation, low process cost and the like.

In this embodiment, the first implantation mask layer and the second implantation mask layer are used as implantation masks for forming the well region 101 and the drift region 102, respectively.

In this embodiment, the drift region 102 has a drain region therein, and the drain region provides for the formation of a drain in a subsequent process. Accordingly, the well region 101 has a source region therein, which is prepared for the subsequent formation of a source.

Referring to fig. 3, a gate structure 103 is formed on the substrate 100 at the interface of the well region 101 and the doped region 102.

The gate structure 103 is used to control the opening and closing of the channel during operation of the semiconductor structure.

The gate structure 103 includes a gate dielectric layer 1031 on the surface of the substrate 100 at the junction between the well region 101 and the doped region 102, and a gate layer 1032 on the gate dielectric layer 1031.

In this embodiment, the gate structure 103 is a polysilicon gate structure, so the material of the gate dielectric layer 1031 is silicon oxide, and the material of the gate layer 1032 is polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and correspondingly, the gate dielectric layer is a high-K gate dielectric layer, and the gate layer is a metal electrode layer.

The method for forming the gate structure 103 includes: forming a gate dielectric material layer (not shown in the figure) on the drift region 102 and the well region 101; forming a gate material layer on the gate dielectric material layer; forming a mask layer 108 on the gate material layer; and etching the gate material layer and the gate dielectric material layer by taking the mask layer 108 as a mask, wherein the remaining gate material layer is used as a gate layer 1032, and the remaining gate dielectric material layer is used as a gate dielectric layer 1031.

The mask layer 108 material includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the mask layer 108 is made of silicon nitride.

It should be noted that, in the subsequent process, the mask layer 108 protects the top of the gate structure 103 from damage.

In this embodiment, the method for forming a semiconductor structure further includes: a sidewall 110 is formed on the sidewall of the gate structure 103.

In the process of forming the semiconductor structure, the sidewall 110 protects the sidewall of the gate structure 103, and the sidewall 110 is further used to define a formation region of the lightly doped region.

In this embodiment, the materials of the side wall 110 include: one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon.

Referring to fig. 4, the method for forming the semiconductor structure further includes: after the gate structure 103 is formed, ions are doped in the well region 101 and the drift region 102 exposed by the gate structure 103, so as to form a lightly doped region 104.

As the semiconductor structure is smaller, the channel length under the gate structure 103 is reduced, and the lightly doped region 104 can effectively mitigate the short channel effect. In addition, in NLDMOS, the lightly doped region 104 can also reduce the peak electric field near the drain, thereby suppressing the hot electron effect and significantly improving the hot carrier lifetime of the device and circuit.

In this embodiment, ions are doped in the well region 101 and the drift region 102 exposed by the gate structure 103 by using an ion implantation method, so as to form a lightly doped region 104. The ion implantation process has the characteristics of simple operation and low process cost.

In this embodiment, the semiconductor structure is used to form an NLDMOS, and N-type ions are doped in the well region 101 and the drift region 102 exposed by the gate structure 103, so as to form a lightly doped region 104. In other embodiments, the semiconductor structure is used to form a PLDMOS, and P-type ions are doped in the well region and the drift region exposed by the gate structure, respectively.

Referring to fig. 5 to 9, the silicide blocking layer 107 (as shown in fig. 9) is formed on the drift region 102 between the drain region and the gate structure 103.

The silicide blocking layer 107 is used to prevent the growth of a silicide (Salicide) layer, thereby preventing the silicide layer from being formed on the drift region 102 between the gate structure 103 and the drain region, avoiding the silicide layer from adversely affecting the formation of a depletion region in the drift region 102, and further ensuring the voltage-withstanding performance of the NLDMOS.

Specifically, the step of forming the silicide blocking layer 107 includes:

as shown in fig. 6, a silicide blocking material layer 106 is formed on the gate structure 103 and the substrate 100 where the gate structure 103 is exposed.

The layer of silicide blocking material 106 provides for the subsequent formation of a silicide blocking layer.

In this embodiment, the material of the silicide blocking material layer 106 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The dielectric constant of the low-K dielectric material is smaller, the low-K dielectric material has excellent insulating property, and correspondingly, the silicide blocking layer formed later also has excellent insulating property, a conductive structure is usually formed on the silicide blocking layer later, when the semiconductor structure works, a large amount of charges can be accumulated at the bottom of the conductive structure, and the material of the silicide blocking layer is the low-K dielectric material, so that charges at the bottom of the conductive structure are not easy to pass through the silicide blocking layer and enter the drift region 102, and NLDMOS has higher breakdown voltage.

Specifically, the materials of the silicide blocking material layer 106 include: siCN, siCO, siON or SiBCN. In this embodiment, the material of the silicide blocking material layer 106 includes SiCO.

In this embodiment, the silicide blocking material layer 106 is formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD). The chemical vapor deposition process is a method for generating a film by using one or more gas phase compounds or simple substances containing film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the silicide blocking material layer 106, so that the film purity of the silicide blocking material layer 106 is higher. In other embodiments, the silicide blocking material layer may also be formed using an atomic layer deposition process (Atomic layer deposition, ALD).

In the step of forming the silicide blocking material layer 106, the silicide blocking material layer 106 is preferably not too thick or too thin. If the silicide blocking material layer 106 is too thick, it takes too much process time to form the silicide blocking material layer 106, and material waste is easily caused, and if the silicide blocking material layer 106 is too thick, the silicide blocking material layer 106 is easy to have too much charge when the semiconductor structure works, and the coupling effect between the too much charge in the silicide blocking layer and carriers in the drift region 102 is serious when the semiconductor structure works, breakdown is easily caused at the silicide blocking layer on the drift region 102, resulting in poor electrical performance of the semiconductor structure. Subsequently, a conductive structure is formed on the silicide blocking layer, and when the semiconductor structure works, charges are accumulated at the bottom of the conductive structure, if the silicide blocking material layer 106 is too thin, the silicide blocking layer 106 cannot well block charges at the bottom of the conductive structure from entering the drift region 102, and accordingly breakdown easily occurs at the silicide blocking layer on the drift region 102, so that the electrical performance of the semiconductor structure is poor. In this embodiment, in the step of forming the silicide blocking material layer 106, the thickness of the silicide blocking material layer 106 is 30 nm to 80 nm.

As shown in fig. 7, ions are doped in the silicide block material layer 106, and the doped ions are doped at the bottom of the silicide block material layer 106.

The silicide blocking material layer 106 is doped with ions, the doped ions are doped at the bottom of the silicide blocking material layer 106, the doped ions are combined with dangling bonds at the bottom surface of the silicide blocking material layer 106 to form saturated bonds, accordingly, charges at the interface at the bottom of the silicide blocking material layer 106 can be reduced, the silicide blocking material layer is etched subsequently to form a silicide blocking layer, when the semiconductor structure works, the coupling effect of carriers in the drift region 102 and charges at the bottom of the silicide blocking layer is small, charges in the corresponding silicide blocking layer are not easy to enter the drift region 102, breakdown voltage of the semiconductor structure is high, and electrical performance of the semiconductor structure is improved; and the ions doped at the bottom of the silicide blocking material layer 106 have their own electric fields, and when the corresponding semiconductor structure works, the ions at the bottom of the silicide blocking layer can interfere with the original electric field line distribution in the silicide blocking layer, so that the electric field lines in the silicide blocking layer are not easy to couple into the drift region 102, and the charges in the silicide blocking layer are not easy to enter into the drift region 102 below the silicide blocking layer, so that the breakdown voltage of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is further improved.

In this embodiment, in the step of doping ions in the silicide blocking material layer 106, the doped ions include C, N or F.

In this embodiment, an ion implantation process is used to dope ions into the silicide blocking material layer 106, so that the doped ions are located at the bottom of the silicide blocking material layer 106. The ion implantation has the characteristics of simple operation and process cost. In other embodiments, a plasma implantation process may be used to dope ions into the silicide blocking material layer, such that the dopant ions are located at the bottom of the silicide blocking material layer.

It should be noted that, in the process of doping ions in the silicide blocking material layer 106 by using the ion implantation process, the implantation energy of the doped ions should not be too large or too small. If the implantation energy of the dopant ions is too large, the dopant ions may easily pass through the silicide blocking material layer 106 and enter the drift region 102, and during the operation of the semiconductor structure, the dopant ions located in the drift region 102 may easily cause scattering of carriers, resulting in poor electrical performance of the semiconductor structure. If the implantation energy of the doped ions is too small, the doped ions are easily doped at the top of the silicide blocking material layer 106 and are not easily combined with dangling bonds at the bottom surface of the silicide blocking material layer 106 to form saturated bonds, so that when the semiconductor structure works, the coupling effect of carriers in the drift region 102 and charges at the bottom of the silicide blocking layer is large, and the charges in the silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is low. In this embodiment, the implantation energy of the doped ions is 1Kev to 5Kev during the process of doping ions in the silicide blocking material layer 106 by using an ion implantation process.

It should also be noted that in the step of doping ions in the silicide blocking material layer 106, the doping amount should not be too large or too small. If the doping amount is too large, too much process time is correspondingly required for doping, which is not beneficial to improving the formation efficiency of the semiconductor structure, and is easy to cause resource waste, and the doping amount is too large, doping ions easily pass through the silicide blocking material layer 106 and enter the drift region 102, and when the semiconductor structure works, the doping ions in the drift region 102 are easy to cause scattering of carriers, and the current performance of the corresponding semiconductor structure is poor. If the doping amount is too small, a large number of dangling bonds remain at the bottom of the silicide blocking material layer 106, and a large number of dangling bonds remain at the bottom of the corresponding subsequently formed silicide blocking layer, so that when the semiconductor structure works, the coupling effect of the carriers in the drift region 102 and the charges at the bottom of the silicide blocking layer is strong, and the charges in the corresponding silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is small; in addition, the doped ions at the bottom of the silicide blocking material layer 106 have a local electric field, and when the semiconductor structure is in operation, the capability of the doped ions at the bottom of the silicide blocking layer to interfere with the original electric field line distribution in the silicide blocking layer is weak, so that the electric field lines in the silicide blocking layer are easy to couple into the drift region 102, and accordingly, charges in the silicide blocking layer are easy to enter into the drift region 102, so that the breakdown voltage of the semiconductor structure is small. In this embodiment, in the step of doping ions in the silicide blocking material layer 106, the doping amount is 3E14 atoms per square centimeter to 2E15 atoms per square centimeter.

In addition, in the step of doping ions in the silicide blocking material layer 106, the angle of incidence of the doping ions is less than not too large with respect to the normal to the surface of the substrate 100. If the included angle between the incident angle of the doped ions and the normal line of the surface of the substrate 100 is too large, a shadow effect (shadow effect) is likely to occur, so that the doped ions are unlikely to enter the silicide blocking material layer 106 at the included angle between the gate structure 103 and the drift region 102, the silicide blocking material layer 106 is patterned subsequently, and the silicide blocking material layer 106 at the included angle between the gate structure 103 and the drift region 102 is usually reserved, so that the bottom surface of the silicide blocking layer at the included angle between the drift region 102 and the gate structure 103 is likely to have a large number of dangling bonds, that is, the bottom surface of the silicide blocking layer is likely to have a large number of charges, and when the semiconductor structure works, the coupling effect between the carriers in the drift region 102 and the charges at the bottom of the silicide blocking layer is relatively strong, and the charges in the silicide blocking layer are likely to enter the drift region 102, so that the breakdown voltage of the semiconductor structure is relatively small; and the lack of doped ions in the silicide blocking layer at the included angle between the drift region 102 and the gate structure 103, which interfere with the distribution of the electric field lines in the silicide blocking layer, results in that the electric field lines in the silicide blocking layer are easy to couple into the drift region 102, and correspondingly, charges in the silicide blocking layer are easy to enter the drift region 102, resulting in a smaller breakdown voltage of the semiconductor structure. In this embodiment, the angle of incidence of the dopant ions is less than 5 ° from the normal to the surface of the substrate 100.

As shown in fig. 9, after doping ions, the silicide blocking material layer 106 is patterned, and the silicide blocking layer 107 is formed on the drift region 102 between the drain region and the gate structure 103.

In this embodiment, the silicide blocking material layer 106 is patterned by a dry etching process, so as to form the silicide blocking layer 107. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the shape of the silicide blocking layer 107 to meet the process requirements, and is also favorable for improving the removal efficiency of the silicide blocking material layer 106.

It should be noted that after patterning the silicide blocking material layer 106, the silicide blocking material layer 106 on the gate structure 103 and a portion of the well region 101 near the gate structure 103 remains, and correspondingly, the silicide blocking material layer on the gate structure 103 and a portion of the well region 101 near the gate structure 103 also serves as the silicide blocking layer 107.

The silicide blocking layer 107 exposes the drain and source regions, providing for the subsequent doping of source and drain ions in the drain and source regions to form the source and drain.

Referring to fig. 6 to 9 in combination with fig. 5, the method for forming a semiconductor structure further includes: after forming the gate structure 103, a first barrier material layer 105 is formed on the gate structure 103 and the substrate 100 where the gate structure 103 is exposed (as shown in fig. 5) before forming the silicide blocking material layer 106.

The first barrier material layer 105 provides for the subsequent formation of a first barrier layer.

In this embodiment, in the step of forming the silicide blocking material layer 106, the silicide blocking material layer 106 is formed on the first blocking material layer 105, and the doped ions doped in the silicide blocking material layer 106 can also form a saturation bond with a dangling bond on the top surface of the first blocking material layer 105.

In the step of doping ions in the silicide blocking material layer 106, the first blocking material layer 105 blocks the doping ions, so that the doping ions are not easy to enter the drift region 102, and carriers in the drift region 102 are not easy to scatter when the semiconductor structure works, which is beneficial to improving the current performance of the semiconductor structure.

Specifically, the materials of the first blocking material layer 105 include a blocking host material and doping ions doped in the blocking host material, and the blocking host material includes: siN, siON, siBCN and SiCN, the dopant ions comprising one or more of C, N, F and B. In this embodiment, the blocking host material comprises SiN, the dopant ions comprise one or more of C, N, F and B, the SiN having a relatively high degree of densification and being capable of blocking charge from passing through the first blocking layer into the drift region 102 during operation of the semiconductor structure. The C, N, B or F can block the lattice gap in the first barrier layer such that electrons in the silicide blocking material layer 106 do not readily diffuse through the first barrier layer into the drift region 102. In addition, C, N, B or F, having an own electric field, can interfere with the original electric field line distribution in the subsequently formed first barrier layer, so that the electric field lines in the first barrier layer are not easy to couple into the drift region 102, and thus the breakdown voltage of the semiconductor structure is higher.

The first barrier material layer 105 is preferably neither too thick nor too thin. If the first blocking material layer 105 is too thick, it takes too much process time to form the first blocking material layer 105, which may result in a low efficiency of forming the semiconductor structure and may easily result in an excessively large volume of the semiconductor structure. If the first blocking material layer 105 is too thin, during the process of doping ions in the silicide blocking material layer 106, the first blocking material layer 105 cannot block the doping ions from entering the drift region 102, and the doping ions entering the drift region 102 easily cause scattering of carriers, resulting in poor current performance of the semiconductor structure. In this embodiment, in the step of forming the first barrier material layer 105, the thickness of the first barrier material layer 105 is 30 nm to 80 nm.

In this embodiment, the first barrier material layer 105 is formed by a chemical vapor deposition process. The chemical vapor deposition process is a method for generating a film by using one or more gas phase compounds or simple substances containing film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the first barrier material layer 105, so that the film purity of the first barrier material layer 105 is higher. In other embodiments, the first barrier material layer may also be formed using an atomic layer deposition process.

Correspondingly, the method for forming the semiconductor structure further comprises the following steps: after patterning the silicide blocking material layer 106, the first blocking material layer 105 is also patterned to form a first blocking layer 110 (as shown in fig. 9).

Referring to fig. 8 and 9, the method for forming the semiconductor structure further includes: after doping ions, before patterning the silicide blocking material layer 106, a second blocking material layer 111 is formed on the silicide blocking material layer 106; the second barrier material layer 111 is patterned to form a second barrier layer 112.

A conductive structure is formed on the silicide blocking layer, specifically the conductive structure is formed on the second blocking layer 112, and when the semiconductor structure works, charges are accumulated at the bottom of the conductive structure, the second blocking layer 112 is used for blocking charges accumulated at the bottom of the conductive structure from passing through the second blocking layer 112 to reach the silicide blocking layer 107, so that charges capable of reaching the drift region 102 are correspondingly reduced, and the breakdown voltage of the semiconductor structure is higher.

In this embodiment, the second barrier material layer 111 is formed by a chemical vapor deposition process. The chemical vapor deposition process is a method for generating a film by using one or more gas phase compounds or simple substances containing film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the second barrier material layer 111, so that the film purity of the second barrier material layer 111 is higher. In other embodiments, the second barrier material layer may also be formed using an atomic layer deposition process.

Specifically, the materials of the second blocking material layer 111 include: siCN, siCO, siON, siBCN or SiN. In this embodiment, the materials of the second barrier material layer 111 include: siCN has higher density, can block charges and can capture charges.

Referring to fig. 10, a drain electrode 113 is formed at the drain region.

In the step of forming the drain 113 in the drain region, a source 114 is also formed in the source region.

The source 114 and drain 113 are used to stress the channel during operation of the semiconductor structure, increasing the mobility of carriers in the channel.

In this embodiment, the doped ion conductivity type in the drain 113 and the source 114 is the same as the doped ion conductivity type in the drift region 102, and is the first type ion.

Specifically, the step of forming the drain electrode 113 and the source electrode 114 includes: the second barrier layer 112, the silicide barrier layer 107 and the first barrier layer 110 are used as doping masks, source and drain ions are doped in the drain region to form a drain 113, and source and drain ions are doped in the source region to form a source 114.

In this embodiment, the semiconductor structure is used to form an NLDMOS, and when the semiconductor structure works, carriers in a channel are electrons, source and drain ions are N-type ions, and specifically, the N-type ions include P, as or Sb. In other embodiments, the semiconductor structure is used to form a PLDMOS, and when the semiconductor structure works, carriers In a channel are holes, source and drain ions are P-type ions, and specifically, the P-type ions include B, ga or In.

Referring to fig. 11 and 12, the method for forming the semiconductor structure further includes: forming a dielectric layer 115 on the second barrier layer 112, the drain electrode 113 and the source electrode 114; etching the dielectric layer 115 over the drift region 102 to form a conductive via (not shown) exposing the second barrier layer 112; a conductive structure 116 is formed in the conductive via.

The conductive structure 116 and the drift region 102 are electrically isolated by the second barrier layer 112, the silicide barrier layer 107 and the first barrier layer 110, so that the conductive structure 116 is in a floating state, the depletion region is widened under the action of an applied built-in electric field after the LDMOS works, the potential drop distance is increased, and the voltage withstanding performance of the LDMOS is improved.

In this embodiment, the material of the conductive structure 116 is W. In other embodiments, the material of the conductive structure may also be a conductive material such as Al, cu, ag, or Au.

In this embodiment, the material of the dielectric layer 115 includes silicon oxide. Silicon oxide is a dielectric material that is common in processing and has low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost of forming the dielectric layer 115.

In the step of forming the conductive via hole in the dielectric layer 115, a contact hole exposing the source 114, the drain 113 and the gate structure 103 is also formed; in the step of forming the conductive structure 116 in the conductive via, a contact plug 117 is also formed in the contact hole.

The contact plug 117 enables electrical connection within the device and also serves to enable electrical connection from device to device.

In this embodiment, the material of the contact plug 117 is the same as the material of the conductive structure 116.

In this embodiment, the silicide blocking layer 107 is formed first, and the drain 113 is formed after the silicide blocking layer 107 is formed.

In other embodiments, the drain electrode may be formed first; after forming the drain, a silicide blocking layer is formed.

In other embodiments, the source electrode is formed in the step of forming the drain electrode.

Specifically, the step of forming the drain electrode and the source electrode includes: forming a shielding layer (not shown) exposing the source region and the drain region; and forming a drain electrode in the drain region and a source electrode in the source region by taking the shielding layer as a doping mask.

The shielding layer is used as a doping mask for forming the source electrode and the drain electrode, the drift region and the well region covered by the shielding layer are protected from being doped easily in the process of doping to form the source electrode and the drain electrode, source and drain ions are not easy to enter the drift region and the well region, and carriers in the drift region are not easy to scatter when the semiconductor structure works, so that the current performance of the semiconductor structure is improved.

The shielding layer is a material which can play a role of a mask and is easy to remove, so that damage to other film structures is reduced when the shielding layer is removed later.

In this embodiment, the material of the shielding layer is an organic material, for example: BARC material, ODL material, SOC material, photoresist, DARC material, DUO material, or APF material.

The method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after forming the source electrode and the drain electrode.

The step of forming a silicide blocking layer includes: after removing the shielding layer, forming a silicide blocking material layer on the gate structure and the substrate exposed by the gate structure; doping ions in the silicide blocking material layer, wherein the doping ions are doped at the bottom of the silicide blocking material layer; and after doping ions, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the gate structure.

The method for forming the semiconductor structure further comprises the following steps: forming a first barrier material layer on the gate structure and the substrate exposed by the gate structure before forming the silicide barrier material layer after forming the source electrode and the drain electrode; in the step of forming the silicide blocking material layer, the silicide blocking material layer is formed on the first blocking material layer; and after patterning the silicide blocking material layer, patterning the first blocking material layer to form a first blocking layer.

The method for forming the semiconductor structure further comprises the following steps: after doping ions, forming a second barrier material layer on the silicide barrier material layer before patterning the silicide barrier material layer; and patterning the second barrier material layer to form a second barrier layer.

Fig. 13 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. The following describes a semiconductor structure provided by an embodiment of the present invention in detail with reference to the accompanying drawings.

Referring to fig. 13, the semiconductor structure of the present embodiment includes: a substrate 300, wherein the substrate 300 is provided with a well region 301 and a drift region 302 which are adjacent to each other; a gate structure 303 located on the substrate 300 at the junction of the well region 301 and the drift region 302; a drain 313 located in the drift region 302 on one side of the gate structure 303; a silicide blocking layer 307 is located on the drift region 302 between the gate structure 303 and the drain 313 region, the silicide blocking layer 307 has doped ions therein, and the doped ions are located at the bottom of the silicide blocking layer 307.

The doped ions are located at the bottom of the silicide blocking layer 307, and the doped ions are combined with dangling bonds on the bottom surface of the silicide blocking layer 307 to form saturated bonds, so that the charges on the bottom surface of the silicide blocking layer 307 can be correspondingly reduced; and the doped ions at the bottom of the silicide blocking layer 307 have an electric field, which can interfere with the original electric field line distribution in the silicide blocking layer 307, so that the electric field lines in the silicide blocking layer 307 are not easy to couple into the drift region 302 below the silicide blocking layer 307, and the charges in the silicide blocking layer 307 are not easy to enter into the drift region 302 below the silicide blocking layer 307, which is beneficial to improving the breakdown voltage of the semiconductor structure.

In this embodiment, taking the LDMOS as a planar transistor as an example, the substrate 300 is a planar substrate correspondingly. In other embodiments, when the LDMOS is a fin field effect transistor, the base correspondingly includes a substrate and a discrete fin located on the substrate.

In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, or other materials, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

The drift region 302 is doped with first type ions, the well region 301 is doped with second type ions, the conductivity types of the first type ions and the second type ions are different, the well region 301 and the drift region 302 are in contact, and the well region 301 serves as a lateral diffusion region to form a channel with a concentration gradient.

Specifically, in this embodiment, when the semiconductor structure is an NLDMOS, the drift region 302 has N-type ions, where the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions, and the well region 301 has P-type ions, where the P-type ions include one or more of boron ions, gallium ions, and indium ions.

In other embodiments, when the semiconductor structure is a PLDMOS, the drift region has P-type ions therein, the P-type ions include one or more of boron ions, gallium ions, and indium ions, and the well region has N-type ions therein, the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

The gate structure 303 is used to control the opening and closing of the channel during operation of the semiconductor structure.

The gate structure 303 includes a gate dielectric layer 3031 on the surface of the substrate 300 at the interface between the well region 301 and the doped region 302, and a gate layer 3032 on the gate dielectric layer 3031.

In this embodiment, the gate structure 303 is a polysilicon gate structure, so the material of the gate dielectric layer 3031 is silicon oxide, and the material of the gate layer 3032 is polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and correspondingly, the gate dielectric layer is a high-K gate dielectric layer, and the gate layer is a metal electrode layer.

The semiconductor structure further includes: a mask layer 308 is located on top of the gate structure 303. The mask layer 308 is used to protect the top of the gate structure 303 from damage.

The mask layer 308 material includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the mask layer 308 is made of silicon nitride.

In this embodiment, the semiconductor structure further includes: and a sidewall 310, located on the sidewall of the gate structure 303.

In this embodiment, the materials of the side wall 310 include: one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon.

The semiconductor structure further includes: and a source 314 located in the well region 301.

The source 314 and drain 313 are used to stress the channel during operation of the semiconductor structure, increasing the mobility of carriers in the channel.

In this embodiment, the doped ion conductivity type in the drain 313 and the source 314 is the same as the doped ion conductivity type in the drift region 302, and is the first type ion.

In this embodiment, the semiconductor structure is used for NLDMOS, and when the semiconductor structure works, carriers in a channel are electrons, source and drain ions are N-type ions, and specifically, the N-type ions include P, as or Sb. In other embodiments, the semiconductor structure is used for PLDMOS, and when the semiconductor structure works, carriers In a channel are holes, source and drain ions are P-type ions, and specifically, the P-type ions include B, ga or In.

The silicide blocking layer 307 is used to prevent the growth of a silicide (Salicide) layer, thereby preventing the silicide layer from being formed on the drift region 302 between the gate structure 303 and the drain 313, avoiding the silicide layer from adversely affecting the formation of a depletion region in the drift region 302, and further ensuring the voltage-withstanding performance of the NLDMOS.

In this embodiment, the silicide blocking layer 307 is made of a low-k dielectric material. The dielectric constant of the low-K dielectric material is smaller, and the insulating property of the low-K dielectric material is excellent.

Specifically, the materials of the silicide blocking layer 307 include: siCN, siCO, siON or SiBCN. In this embodiment, the material of the silicide blocking layer 307 includes SiCO.

In this embodiment, the dopant ions in the silicide blocking layer 307 include C, N or F.

The doping concentration of the doping ions in the silicide blocking layer 307 should not be too large or too small. If the doping concentration is too high, too much process time is correspondingly required, which is not beneficial to improving the formation efficiency of the semiconductor structure, and is easy to cause resource waste, and the doping concentration of the doping ions is too high, the doping ions easily pass through the silicide blocking layer 307 and enter the drift region 302, and when the semiconductor structure works, the doping ions in the drift region 302 are easy to cause scattering of carriers, and the current performance of the corresponding semiconductor structure is poor. If the doping concentration is too small, the number of saturated bonds formed by the doping ions and the dangling bonds is small, a large number of dangling bonds still remain on the bottom surface of the silicide blocking layer 307, and when the semiconductor structure works, the coupling effect of the carriers in the drift region 302 and the charges at the bottom of the silicide blocking layer 307 is strong, and the charges in the silicide blocking layer 307 easily enter the drift region 302, so that the breakdown voltage of the semiconductor structure is small; in addition, the doped ions at the bottom of the silicide blocking layer 307 have a local electric field, and when the semiconductor structure works, the capability of the doped ions at the bottom of the silicide blocking layer 307 to interfere with the original electric field line distribution in the silicide blocking layer 307 is weak, so that the electric field lines in the silicide blocking layer 307 are easy to couple into the drift region 302, and accordingly, charges in the silicide blocking layer 307 are easy to enter into the drift region 302, so that the breakdown voltage of the semiconductor structure is small. In this embodiment, in the step of doping ions in the silicide blocking layer 307, the doping concentration is 3E19 atoms per cubic centimeter to 2E20 atoms per cubic centimeter.

The silicide blocking layer 307 is preferably not too thick or too thin. If the silicide blocking layer 307 is too thick, it takes too much process time to form the silicide blocking layer 307, and material waste is easily caused, and if the silicide blocking layer 307 is too thick, too much charge is easily present in the silicide blocking layer 307 when the semiconductor structure works, the coupling effect between the charge in the silicide blocking layer 307 and the carriers in the drift region 302 is serious, breakdown easily occurs at the silicide blocking layer 307 on the drift region 302, and the electrical performance of the semiconductor structure is poor. When the semiconductor structure is in operation, charges are accumulated at the bottom of the conductive structure 316, if the silicide blocking layer 307 is too thin, the silicide blocking layer 307 cannot well block charges at the bottom of the conductive structure from entering the drift region 302, and breakdown easily occurs at the silicide blocking layer 307 on the drift region 302, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the silicide blocking layer 307 is 30 nm to 80 nm.

The semiconductor structure further includes: a first barrier layer 310 between the silicide block layer 307 and the substrate 300, and between the silicide block layer 307 and the gate structure 303.

The first blocking layer 310 makes the doped ions in the silicide blocking layer 307 not easy to enter the drift region 302, and makes the carriers in the drift region 302 not easy to scatter when the semiconductor structure works, which is beneficial to improving the current performance of the semiconductor structure.

Specifically, the materials of the first blocking layer 310 include a blocking host material and doped ions doped in the blocking host material, and the blocking host material includes: siN, siON, siBCN and SiCN, the dopant ions comprising one or more of C, N, F and B. In this embodiment, the blocking host material comprises SiN, the dopant ions comprise one or more of C, N, F and B, and SiN has a relatively high degree of densification that is capable of blocking charge from entering the drift region 302 during operation of the semiconductor structure. The C, N, B or F can block the lattice gap in the first barrier layer 310 such that electrons in the silicide blocking layer 307 do not readily diffuse through the first barrier layer 310 into the drift region 302. In addition, C, N, B or F, having an electric field thereof, can interfere with the original electric field line distribution in the first barrier layer 310, so that the electric field lines in the first barrier layer 310 are not easy to couple into the drift region 302, and thus the breakdown voltage of the semiconductor structure is higher.

In this embodiment, the first barrier layer 310 is preferably not too thick or too thin. If the first barrier layer 310 is too thick, it takes too much process time to form the first barrier layer 310, which may result in a low efficiency of forming the semiconductor structure and may easily result in an excessively large volume of the semiconductor structure. If the first blocking layer 310 is too thin, the doped ions in the silicide blocking layer 307 may easily pass through the first blocking layer 310 and enter the drift region 302, and the doped ions entering the drift region 302 may easily cause scattering of carriers, resulting in poor current performance of the semiconductor structure. In this embodiment, the thickness of the first blocking layer 310 is 30 nm to 80 nm.

The semiconductor structure further includes: a second barrier layer 312 is located on the silicide block layer 307.

Specifically, the materials of the second barrier layer 312 include: siCN, siCO, siON, siBCN or SiN. In this embodiment, the materials of the second barrier layer 312 include: siCN has higher density, can block charges and can capture charges.

The semiconductor structure further includes: a dielectric layer 315 is disposed on the second barrier layer 312, the drain electrode 313 and the source electrode 314.

The dielectric layer 315 serves to electrically isolate adjacent devices

In this embodiment, the material of the dielectric layer 315 includes silicon oxide. Silicon oxide is a dielectric material that is common in processing and has low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost of forming the dielectric layer 315.

The semiconductor structure further includes: a conductive structure 316 extends through the dielectric layer 315 and contacts the second barrier layer 312 over the drift region 302.

The conductive structure 316 and the drift region 302 are electrically isolated from each other by the second barrier layer 312, the silicide barrier layer 307 and the first barrier layer 310, so that the conductive structure 316 is in a floating state, the depletion region is widened under the action of an applied built-in electric field after the LDMOS is operated, the potential drop distance is increased, and the voltage withstanding performance of the LDMOS is improved.

In this embodiment, the material of the conductive structure 316 is W. In other embodiments, the material of the conductive structure may also be a conductive material such as Al, cu, ag, or Au.

It should be noted that, the conductive structure 316 is formed on the second blocking layer 112, and negative charges are accumulated at the bottom of the conductive structure 316 when the semiconductor structure is in operation, and the second blocking layer 112 can block charges accumulated at the bottom of the conductive structure 316 from passing through the second blocking layer 112 to reach the silicide blocking layer 107, so that charges capable of reaching the drift region 102 are correspondingly reduced, and the breakdown voltage of the semiconductor structure is higher.

It should be noted that the semiconductor structure further includes: a contact plug 317, the contact plug 317 extending through the dielectric layer 315 and electrically connecting with the source 314, drain 315 or the gate structure 303.

The contact plugs 317 are formed of the same material as the conductive structures 316.

The semiconductor structure further includes: lightly doped region 304 is located in drift region 302 between drain 313 and gate structure 303, and in well region 301 between source 314 and gate structure 303.

As the semiconductor structure is smaller, the channel length under the gate structure 303 is reduced, and the lightly doped region 304 can effectively mitigate the short channel effect. In addition, in NLDMOS, lightly doped region 304 also reduces the peak electric field near the drain, thereby suppressing the hot electron effect and significantly improving the hot carrier lifetime of the device and circuit.

In this embodiment, the semiconductor structure is used for NLDMOS, and the lightly doped region 304 is formed by doping N-type ions in the well region 301 and the drift region 302 exposed by the gate structure 303. In other embodiments, the semiconductor structure is used for PLDMOS, and P-type ions are doped in the well region and the drift region exposed by the gate structure, respectively.

The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a well region and a drift region which are adjacent to each other are formed in the substrate, and the drift region is provided with a drain region;

forming a grid structure on the substrate at the junction of the well region and the drift region;

forming a drain electrode in the drain region;

forming a silicide blocking material layer on the gate structure and the substrate exposed by the gate structure;

doping ions in the silicide blocking material layer, wherein the doping ions are doped at the bottom of the silicide blocking material layer;

Patterning the silicide blocking material layer after doping ions, and forming a silicide blocking layer on the drift region between the drain region and the gate structure;

the method for forming the semiconductor structure further comprises the following steps: forming a first barrier material layer on the gate structure and the substrate exposed by the gate structure before forming the silicide barrier material layer after forming the gate structure;

in the step of forming the silicide blocking material layer, the silicide blocking material layer is formed on the first blocking material layer;

and after patterning the silicide blocking material layer, patterning the first blocking material layer to form a first blocking layer.

2. The method of forming a semiconductor structure of claim 1, further comprising: after doping ions, forming a second barrier material layer on the silicide barrier material layer before patterning the silicide barrier material layer; and patterning the second barrier material layer to form a second barrier layer.

3. The method of forming a semiconductor structure of any one of claims 1 to 2, wherein in the step of doping ions in the silicide block material layer, the doped ions comprise C, N or F.

4. The method of forming a semiconductor structure according to any one of claims 1 to 2, wherein ions are doped in the silicide blocking material layer using an ion implantation process or a plasma implantation process.

5. The method for forming a semiconductor structure according to any one of claims 1 to 2, wherein ions are doped in the silicide blocking material layer by ion implantation, and process parameters of the doped ions include: the doping amount is 3E14 atoms per square centimeter to 2E15 atoms per square centimeter, the included angle between the incidence direction of the doping ions and the normal line of the substrate surface is smaller than 5 degrees, and the implantation energy of the doping ions is 1Kev to 5Kev.

6. The method of forming a semiconductor structure of any one of claims 1 to 2, wherein in the step of forming the silicide block material layer, the thickness of the silicide block material layer is 30 nm to 80 nm.

7. The method of forming a semiconductor structure of any of claims 1-2, wherein the material of the silicide blocking material layer is a low-k dielectric material.

8. The method of forming a semiconductor structure of any of claims 7, wherein the material of the silicide blocking material layer comprises: siCN, siCO, siON or SiBCN.

9. The method of forming a semiconductor structure according to any one of claims 1 to 2, wherein the silicide blocking material layer is formed using a chemical vapor deposition process or an atomic layer deposition process.

10. The method of forming a semiconductor structure of any one of claims 1 to 2, wherein the step of forming the drain and the silicide block layer comprises: forming the drain electrode; forming the silicide blocking layer after forming the drain electrode;

alternatively, forming the silicide blocking layer; and forming the drain electrode after forming the silicide blocking layer.

11. The method of forming a semiconductor structure of claim 1 or 2, wherein the first barrier material layer comprises a barrier host material and dopant ions doped in the barrier host material, the barrier host material comprising: siN, siON, siBCN and SiCN, the dopant ions comprising one or more of C, N, F and B.

12. A semiconductor structure, comprising:

a substrate, wherein the substrate is internally provided with a well region and a drift region which are adjacent;

the grid structure is positioned on the substrate at the junction of the well region and the drift region;

The drain electrode is positioned in the drift region at one side of the gate structure;

a silicide blocking layer positioned on the drift region between the gate structure and the drain, wherein the silicide blocking layer is provided with doped ions, and the doped ions are positioned at the bottom of the silicide blocking layer;

the semiconductor structure further includes: a first barrier layer between the silicide blocking layer and the substrate, and between the silicide blocking layer and the gate structure.

13. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises: and the second barrier layer is positioned on the silicide barrier layer.

14. The semiconductor structure of any of claims 12-13, wherein the silicide blocking layer has doped ions comprising C, N or F.

15. The semiconductor structure of any of claims 12-13, wherein a doping concentration of dopant ions at a bottom of the silicide block layer is from 3E19 atoms per cubic centimeter to 2E20 atoms per cubic centimeter.

16. The semiconductor structure of any one of claims 12 to 13, wherein the silicide blocking layer has a thickness of 30 nm to 80 nm.

17. The semiconductor structure of any one of claims 12 to 13, wherein the material of the silicide blocking layer comprises: siCN, siCO, siON with doped ions or SiBCN.

18. The semiconductor structure of any one of claims 12 to 13, wherein the first barrier layer comprises a barrier host material and dopant ions doped in the barrier host material, the barrier host material comprising: siN, siON, siBCN and SiCN, the dopant ions comprising one or more of C, N, F and B.