CN113675087A

CN113675087A - Semiconductor structure and forming method thereof

Info

Publication number: CN113675087A
Application number: CN202010406717.1A
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-05-14
Filing date: 2020-05-14
Publication date: 2021-11-19
Anticipated expiration: 2040-05-14
Also published as: CN113675087B

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate, and a drain region is formed in the drift region; forming a gate structure on the substrate at the junction of the well region and the drift region; forming a silicide blocking material layer on the grid structure and the substrate exposed from the grid structure; doping ions in the silicide blocking material layer, wherein the doped ions are doped at the bottom of the silicide blocking material layer; and patterning the silicide blocking material layer to form a silicide blocking layer on the drift region between the drain region and the gate structure. The doped ions are combined with the dangling bonds at the bottom of the silicide blocking material layer to form saturated bonds, so that charges on an interface at the bottom of the silicide blocking material layer can be reduced, the ions doped at the bottom of the silicide blocking material layer have own electric field and can interfere with the original electric field line distribution in the silicide blocking layer, and therefore the charges in the silicide blocking layer are not easy to enter a drift region, and the breakdown voltage of the semiconductor structure is high.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In the development of power integrated circuits, a single chip process developed for integrating a power switch and a control circuit together, especially a lateral double diffusion MOS (LDMOS) process currently used for manufacturing a monolithic integrated circuit, is a mainstream trend. The LDMOS process performs planar diffusion (planar diffusion) on the surface of the semiconductor substrate to form a main current path in the lateral direction, and thus the control circuit and the LDMOS can be integrated on a single power IC because the LDMOS is fabricated by a typical IC process.

LDMOS devices are field effect transistor devices (FETs) that are similar to FET devices of a conventional Field Effect Transistor (FET) device, each including a pair of source/drain regions formed in a semiconductor substrate separated by a channel region and a gate electrode formed in turn over the channel region, however, unlike the conventional FET devices in which the pair of source/drain regions are formed symmetrically to the gate electrode, the drain region is further from the gate electrode than the source region, and the drain region is simultaneously formed in a doped well (of the same polarity as the drain region) that separates the channel region from the drain region.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate, and a drain region is arranged in the drift region; forming a gate structure on the substrate at the junction of the well region and the drift region; forming a drain electrode in the drain region; forming a silicide blocking material layer on the grid structure and the substrate exposed by the grid structure; doping ions in the silicide blocking material layer, wherein the doped ions are doped at the bottom of the silicide blocking material layer; and after ions are doped, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the grid structure.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: the drift region is arranged in the substrate and is adjacent to the well region; the grid structure is positioned on the substrate at the junction of the well region and the drift region; the drain electrode is positioned in the drift region on one side of the grid structure; and the silicide blocking layer is positioned on the drift region between the grid structure and the drain electrode, doped ions are arranged in the silicide blocking layer, and the doped ions are positioned at the bottom of the silicide blocking layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure of the embodiment of the invention, a substrate is internally provided with a well region and a drift region which are adjacent, and a gate structure is formed on the substrate at the junction of the well region and the drift region; forming a silicide blocking material layer on the grid structure and the substrate exposed by the grid structure; ions are doped in the silicide blocking material layer and doped at the bottom of the silicide blocking material layer, the doped ions and dangling bonds on the bottom surface of the silicide blocking material layer are combined to form saturated bonds, accordingly, the charges on the bottom surface of the silicide blocking material layer can be reduced, when the semiconductor structure works, the coupling effect of carriers in the drift region and the charges on the bottom of the silicide blocking layer is small, the charges in the corresponding silicide blocking layer are not easy to enter the drift region, the breakdown voltage of the semiconductor structure is high, and the electrical performance of the semiconductor structure is improved; the ions doped at the bottom of the silicide blocking material layer have an electric field of the ions, and can interfere the original electric field line distribution in the silicide blocking layer, so that the electric field lines in the silicide blocking layer are not easily coupled to the drift region below the silicide blocking layer, and the charges in the silicide blocking layer are not easily entered into the drift region below the silicide blocking layer, so that the breakdown voltage of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is further improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIGS. 2 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

FIG. 13 is a schematic structural diagram illustrating a method of forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As can be seen from the background art, the semiconductor structure formed at present still has a problem of poor electrical performance. The reason for the poor performance of the semiconductor structure is analyzed in combination with a method for forming the semiconductor structure.

Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.

The semiconductor structure shows a design of a high-voltage LDMOS, the semiconductor structure includes: a substrate 10, wherein a well region 11 and a drift region 12 which are adjacent to each other are formed in the substrate 10; the gate structure 20 is positioned on the substrate 10 at the boundary of the well region 11 and the drift region 12, and the gate structure 20 comprises a gate oxide layer 21 and a gate layer 22 positioned on the gate oxide layer 21; a source region 31 located in the well region 11 at one side of the gate structure 20; a drain region 32 located in the drift region 12 at the other side of the gate structure 20; a silicide blocking layer 33 located on the substrate 10 between the gate structure 20 and the drain region 32, wherein the silicide blocking layer 33 further extends to the sidewall and a part of the top of the gate structure 20 on the side close to the drain region 32; a dielectric layer (not shown) on the substrate 10 exposed by the gate structure 20, the dielectric layer further covering the gate structure 20; a first contact hole plug (CT) 40 located within the dielectric layer, the first contact hole plug 40 being electrically connected to the gate layer 22, the drain region 32, or the source region 31; a second contact hole plug 41 located within the dielectric layer, the second contact hole plug 41 being connected to the silicide block layer 33 on the drift region 12.

Taking an N-type laterally double diffused metal oxide semiconductor field effect transistor (NLDMOS) as an example, when the device is in operation, a current flows from the drain region 32 to the channel under the gate structure 20, positive charges are accumulated in the drift region 12 under the second contact hole plug 41, and under the action of an electric field between the drain region 32 and the gate structure 20, negative charges are accumulated at the bottom of the silicide blocking layer 33, the negative charges in the silicide blocking layer 33 are coupled with the positive charges in the drift region 12, and breakdown is likely to occur at the silicide blocking layer 33, which results in a smaller breakdown voltage of the N-type laterally double diffused metal oxide semiconductor field effect transistor.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate, and a drain region is arranged in the drift region; forming a gate structure on the substrate at the junction of the well region and the drift region; forming a drain electrode in the drain region; forming a silicide blocking material layer on the grid structure and the substrate exposed by the grid structure; doping ions in the silicide blocking material layer, wherein the doped ions are doped at the bottom of the silicide blocking material layer; and after ions are doped, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the grid structure.

In the semiconductor structure of the embodiment of the invention, a substrate is provided with a well region and a drift region which are adjacent in the substrate; the grid structure is positioned on the substrate at the junction of the well region and the drift region; the drain electrode is positioned in the drift region on one side of the grid structure; and the silicide blocking layer is positioned on the drift region between the grid structure and the drain region, doped ions are arranged in the silicide blocking layer, and the doped ions are positioned at the bottom of the silicide blocking layer.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention, and the method for forming a semiconductor structure according to the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2, a substrate 100 is provided, a well region 101 and a drift region 102 are formed adjacent to each other in the substrate 100, and the drift region 102 has a drain region (not shown).

The substrate 100 is used to provide a process platform for the subsequent formation of the LDMOS. In this embodiment, taking the LDMOS as a planar transistor as an example, the substrate 100 is correspondingly a planar substrate. In other embodiments, when the LDMOS is a finfet, the substrate comprises a substrate and a discrete fin on the substrate.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium oxide substrate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The drift region 102 is doped with first type ions, the well region 101 is doped with second type ions, the conductivity types of the first type ions and the second type ions are different, the well region 101 is in contact with the drift region 102, and the well region 101 serves as a lateral diffusion region to form a channel with a concentration gradient.

Specifically, in this embodiment, when the semiconductor structure is used to form an NLDMOS, the drift region 102 has N-type ions therein, where the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions, and the well region 101 has P-type ions therein, where the P-type ions include one or more of boron ions, gallium ions, and indium ions.

In other embodiments, when the semiconductor structure is used to form a PLDMOS, the drift region has P-type ions therein, the P-type ions include one or more of boron ions, gallium ions, and indium ions, and the well region 101 has N-type ions therein, the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

The step of forming the well region 101 and the drift region 102 includes: forming a first implantation mask layer (not shown in the figure), wherein the first implantation mask layer covers the substrate 100 on which the drift region is to be formed and exposes the substrate 100 on which the well region is to be formed; doping the substrate exposed by the first injection mask layer with second type ions to form a well region 101; after forming the well region 101, forming the substrate 100 covering the well region 101 and exposing a drift region to be formed; doping the substrate 100 exposed by the second implantation mask layer with first type ions to form the drift region 102.

In the embodiment of the invention, the substrate 100 exposed by the first implantation mask layer is doped with the second type ions by an ion implantation method to form the well region 101. The ion implantation has the characteristics of simple operation, low process cost and the like.

In the embodiment of the present invention, the substrate 100 exposed by the second implantation mask layer is doped with first type ions by an ion implantation method to form the drift region 102. The ion implantation has the characteristics of simple operation, low process cost and the like.

In this embodiment, the first implantation mask layer and the second implantation mask layer are respectively used as implantation masks for forming the well region 101 and the drift region 102.

In this embodiment, the drift region 102 has a drain region therein, and the drain region is prepared for forming a drain in a subsequent process. Correspondingly, the well region 101 has a source region therein, which is ready for the subsequent formation of a source.

Referring to fig. 3, a gate structure 103 is formed on the substrate 100 at the boundary between the well region 101 and the doped region 102.

The gate structure 103 is used to control the opening and closing of the channel during operation of the semiconductor structure.

The gate structure 103 includes a gate dielectric layer 1031 on the surface of the substrate 100 at the interface between the well region 101 and the doped region 102, and a gate layer 1032 on the gate dielectric layer 1031.

In this embodiment, the gate structure 103 is a polysilicon gate structure, so that the gate dielectric layer 1031 is made of silicon oxide, and the gate layer 1032 is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and accordingly, the gate dielectric layer is a high-K gate dielectric layer, and the gate layer is a metal electrode layer.

The forming method of the gate structure 103 comprises the following steps: a gate dielectric material layer (not shown in the figure) is formed on the drift region 102 and the well region 101; forming a gate material layer on the gate dielectric material layer; forming a mask layer 108 on the gate material layer; and etching the gate material layer and the gate dielectric material layer by taking the mask layer 108 as a mask, wherein the rest gate material layer is taken as a gate electrode layer 1032, and the rest gate dielectric material layer is taken as a gate dielectric layer 1031.

The material of the mask layer 108 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron nitride silicon carbide. In this embodiment, the mask layer 108 is made of silicon nitride.

It should be noted that, in the subsequent process, the mask layer 108 protects the top of the gate structure 103 from being damaged.

In this embodiment, the method for forming the semiconductor structure further includes: and forming a side wall 110 on the side wall of the gate structure 103.

In the forming process of the semiconductor structure, the side wall 110 protects the side wall of the gate structure 103, and the side wall 110 is further used for defining a forming region of a lightly doped region.

In this embodiment, the material of the sidewall 110 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.

Referring to fig. 4, the method for forming the semiconductor structure further includes: after the gate structure 103 is formed, ions are doped in the well region 101 and the drift region 102 exposed by the gate structure 103 to form a lightly doped region 104.

As the size of the semiconductor structure is smaller and smaller, the length of the channel below the gate structure 103 is continuously reduced during the operation of the semiconductor structure, and the lightly doped region 104 can effectively reduce the short channel effect. In addition, in the NLDMOS, the lightly doped region 104 can also reduce the peak electric field near the drain end, thereby suppressing the hot electron effect and significantly improving the hot carrier lifetime of the device and the circuit.

In this embodiment, ions are doped in the well region 101 and the drift region 102 exposed by the gate structure 103 by ion implantation to form a lightly doped region 104. The ion implantation process has the characteristics of simple operation and low process cost.

In this embodiment, the semiconductor structure is used to form an NLDMOS, and N-type ions are doped into the well region 101 and the drift region 102 exposed by the gate structure 103, so as to form a lightly doped region 104. In other embodiments, the semiconductor structure is used to form a PLDMOS, and P-type ions are doped in the exposed well region and drift region of the gate structure.

Referring to fig. 5 to 9, the silicide blocking layer 107 is formed on the drift region 102 between the drain region and the gate structure 103 (as shown in fig. 9).

The silicide blocking layer 107 is used for preventing a silicide (Salicide) layer from growing, so that the silicide layer is prevented from being formed on the drift region 102 between the gate structure 103 and the drain region, the silicide layer is prevented from generating adverse effects on the formation of a depletion region in the drift region 102, and the voltage resistance of the NLDMOS is further ensured.

Specifically, the step of forming the silicide blocking layer 107 includes:

as shown in fig. 6, a silicide blocking material layer 106 is formed on the gate structure 103 and the substrate 100 exposed by the gate structure 103.

The layer of silicide blocking material 106 provides for the subsequent formation of a silicide blocking layer.

In this embodiment, the silicide blocking material layer 106 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9). The low-K dielectric material has a small dielectric constant, the low-K dielectric material has excellent insulating property, correspondingly, a silicide blocking layer formed subsequently also has excellent insulating property, a conductive structure is usually formed on the silicide blocking layer subsequently, when the semiconductor structure works, a large amount of charges are collected at the bottom of the conductive structure, and the silicide blocking layer is made of the low-K dielectric material, so that the charges at the bottom of the conductive structure are not easy to penetrate through the silicide blocking layer to enter the drift region 102, and the NLDMOS has high breakdown voltage.

Specifically, the material of the silicide blocking material layer 106 includes: SiCN, SiCO, SiON, or SiBCN. In this embodiment, the material of the silicide blocking material layer 106 includes SiCO.

In this embodiment, the silicide blocking material layer 106 is formed by a Chemical Vapor Deposition (CVD) process. The chemical vapor deposition process is a method for generating a film by utilizing one or more gas-phase compounds or simple substances containing film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the silicide blocking material layer 106, so that the film purity of the silicide blocking material layer 106 is higher. In other embodiments, the silicide blocking material layer may also be formed by an Atomic Layer Deposition (ALD) process.

It should be noted that in the step of forming the silicide blocking material layer 106, the silicide blocking material layer 106 is not too thick nor too thin. If the silicide blocking material layer 106 is too thick, an excessive process time is required to form the silicide blocking material layer 106, and material waste is easily caused, and if the silicide blocking material layer 106 is too thick, the corresponding silicide blocking layer is too thick, when the semiconductor structure works, excessive charges are easily present in the silicide blocking material layer 106, and accordingly, when the semiconductor structure works, the coupling effect between the excessive charges in the silicide blocking layer and carriers in the drift region 102 is severe, and breakdown is easily caused at the silicide blocking layer on the drift region 102, so that the electrical performance of the semiconductor structure is poor. And forming a conductive structure on the silicide blocking layer, wherein when the semiconductor structure works, charges are accumulated at the bottom of the conductive structure, if the silicide blocking material layer 106 is too thin, the silicide blocking layer 106 cannot well block the charges at the bottom of the conductive structure from entering the drift region 102, and the silicide blocking layer on the drift region 102 is correspondingly easy to break down, so that the electrical property of the semiconductor structure is poor. In this embodiment, in the step of forming the silicide blocking material layer 106, the thickness of the silicide blocking material layer 106 is 30 nm to 80 nm.

As shown in fig. 7, ions are doped in the silicide block material layer 106, and the doped ions are doped at the bottom of the silicide block material layer 106.

Doping ions in the silicide blocking material layer 106, wherein the doping ions are doped at the bottom of the silicide blocking material layer 106, the doping ions are combined with a dangling bond on the bottom surface of the silicide blocking material layer 106 to form a saturated bond, accordingly, charges on the bottom interface of the silicide blocking material layer 106 can be reduced, the silicide blocking material layer is etched subsequently to form a silicide blocking layer, when the semiconductor structure works, the coupling effect of carriers in the drift region 102 and the charges on the bottom of the silicide blocking layer is small, the charges in the corresponding silicide blocking layer are not easy to enter the drift region 102, the breakdown voltage of the semiconductor structure is high, and the electrical performance of the semiconductor structure is improved; the ions doped at the bottom of the silicide blocking material layer 106 have their own electric field, and when the corresponding semiconductor structure works, the ions at the bottom of the silicide blocking material layer can interfere with the original electric field line distribution in the silicide blocking layer, so that the electric field lines in the silicide blocking layer are not easily coupled to the drift region 102, and the charges in the silicide blocking layer are not easily introduced into the drift region 102 below the silicide blocking layer, so that the breakdown voltage of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is further improved.

In this embodiment, in the step of doping ions in the silicide blocking material layer 106, the doped ions include C, N or F.

In this embodiment, an ion implantation process is adopted to dope ions in the silicide blocking material layer 106, so that the doped ions are located at the bottom of the silicide blocking material layer 106. The ion implantation has the characteristics of simple operation and low process cost. In other embodiments, a plasma implantation process may be further used to dope ions in the silicide blocking material layer, so that the doped ions are located at the bottom of the silicide blocking material layer.

It should be noted that, in the process of doping ions in the silicide blocking material layer 106 by using an ion implantation process, the implantation energy of the doped ions should not be too large or too small. If the implantation energy of the dopant ions is too large, the dopant ions easily penetrate through the silicide blocking material layer 106 and enter the drift region 102, and when the semiconductor structure works, the dopant ions in the drift region 102 easily cause scattering of carriers, which results in poor electrical performance of the semiconductor structure. If the injection energy of the doped ions is too small, the doped ions are easily doped at the top of the silicide blocking material layer 106 and are not easily combined with a dangling bond at the bottom surface of the silicide blocking material layer 106 to form a saturated bond, when the semiconductor structure works, the coupling effect of a carrier in the drift region 102 and charges at the bottom of the silicide blocking layer is large, the charges in the silicide blocking layer easily enter the drift region 102, and the breakdown voltage of the semiconductor structure is low. In this embodiment, in the process of doping ions in the silicide blocking material layer 106 by using an ion implantation process, the implantation energy of the doped ions is 1Kev to 5 Kev.

It should be noted that, in the step of doping ions in the silicide blocking material layer 106, the doping amount should not be too large, and should not be too small. If the amount of the dopant is too large, too much process time is required to dope correspondingly, which is not favorable for improving the formation efficiency of the semiconductor structure and is likely to cause resource waste, and the dopant is too large, so that the dopant easily penetrates through the silicide blocking material layer 106 and enters the drift region 102, and when the semiconductor structure works, the dopant in the drift region 102 is likely to cause scattering of carriers, and the current performance of the corresponding semiconductor structure is not good. If the dopant amount is too small, a large number of dangling bonds still exist at the bottom of the silicide blocking material layer 106, and a large number of dangling bonds exist at the bottom surface of a corresponding subsequently formed silicide blocking layer, so that when the semiconductor structure works, the coupling effect of the current carriers in the drift region 102 and the charges at the bottom of the silicide blocking layer is strong, and the charges in the corresponding silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is small; in addition, the doped ions at the bottom of the silicide blocking material layer 106 have a local electric field, and when the semiconductor structure operates, the doped ions at the bottom of the silicide blocking layer have a weak ability to interfere with the original distribution of the electric field lines in the silicide blocking layer, so that the electric field lines in the silicide blocking layer are easily coupled to the drift region 102, and accordingly, charges in the silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is small. In this embodiment, in the step of doping ions in the silicide blocking material layer 106, the doping amount is 3E14 atoms per square centimeter to 2E15 atoms per square centimeter.

In addition, in the step of doping ions in the silicide blocking material layer 106, an included angle between an incident angle of the doped ions and a normal of the surface of the substrate 100 is not too large. If the included angle between the incident angle of the doped ions and the normal line of the substrate 100 is too large, a shadowing effect (shadow effect) is likely to occur, so that the doped ions are not likely to enter the silicide blocking material layer 106 at the corner between the gate structure 103 and the drift region 102, subsequent patterning of the layer of silicide blocking material 106, the formation of a silicide blocking layer, typically the silicide blocking material layer 106 at the corner between the gate structure 103 and the drift region 102 is preserved, therefore, the bottom surface of the silicide block layer at the corner between the drift region 102 and the gate structure 103 is prone to have a large number of dangling bonds, i.e. the bottom surface of the silicide block layer is prone to have a large number of charges, when the semiconductor structure works, the coupling effect of the current carriers in the drift region 102 and the bottom charges of the silicide blocking layer is strong, and the charges in the silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is small; and the silicide blocking layer at the corner between the drift region 102 and the gate structure 103 lacks doped ions which interfere with the original electric field line distribution in the silicide blocking layer, so that the electric field lines in the silicide blocking layer are easily coupled into the drift region 102, and correspondingly, charges in the silicide blocking layer easily enter the drift region 102, so that the breakdown voltage of the semiconductor structure is smaller. In this embodiment, the angle between the incident angle of the doped ions and the normal of the surface of the substrate 100 is less than 5 °.

As shown in fig. 9, after doping ions, the silicide blocking material layer 106 is patterned, and the silicide blocking layer 107 is formed on the drift region 102 between the drain region and the gate structure 103.

In this embodiment, the silicide blocking material layer 106 is patterned by a dry etching process to form the silicide blocking layer 107. The dry etching process has anisotropic etching characteristics and better etching profile controllability, is favorable for enabling the appearance of the silicide blocking layer 107 to meet the process requirements, and is also favorable for improving the removal efficiency of the silicide blocking material layer 106.

It should be noted that after the silicide blocking material layer 106 is patterned, the silicide blocking material layer 106 on the gate structure 103 and a portion of the well region 101 close to the gate structure 103 is retained, and correspondingly, the silicide blocking material layer on the gate structure 103 and a portion of the well region 101 close to the gate structure 103 also serves as a silicide blocking layer 107.

It should be further noted that the silicide blocking layer 107 exposes the drain region and the source region, and provides for doping source and drain ions in the drain region and the source region, and forming a source electrode and a drain electrode.

Referring to fig. 6 to 9 in conjunction with fig. 5, the method for forming the semiconductor structure further includes: after the gate structure 103 is formed and before the silicide blocking material layer 106 is formed, a first blocking material layer 105 is formed on the gate structure 103 and the substrate 100 exposed by the gate structure 103 (as shown in fig. 5).

The first barrier material layer 105 provides for the subsequent formation of a first barrier layer.

In this embodiment, in the step of forming the silicide blocking material layer 106, the silicide blocking material layer 106 is formed on the first blocking material layer 105, and the doped ions doped in the silicide blocking material layer 106 can also form a saturation bond with the dangling bond on the top surface of the first blocking material layer 105.

In the step of doping ions in the silicide blocking material layer 106, the first blocking material layer 105 blocks the doping ions, so that the doping ions are not easy to enter the drift region 102, and when the semiconductor structure works, carriers in the drift region 102 are not easy to scatter, which is beneficial to improving the current performance of the semiconductor structure.

Specifically, the material of the first barrier material layer 105 includes a barrier host material and dopant ions doped in the barrier host material, and the barrier host material includes: SiN, SiON, SiBCN, and SiCN, and the dopant ions include one or more of C, N, F and B. In this embodiment, the blocking host material comprises SiN, the dopant ions comprise one or more of C, N, F and B, and the SiN has a higher density and is capable of blocking charges from passing through the first blocking layer into the drift region 102 when the semiconductor structure is in operation. The C, N, B or F can block the lattice gap in the first barrier layer so that electrons in the silicide blocking material layer 106 do not readily diffuse through the first barrier layer into the drift region 102. In addition, C, N, B or F, which has its own electric field, can interfere with the original distribution of electric field lines in the subsequently formed first blocking layer, so that the electric field lines in the first blocking layer are not easily coupled into the drift region 102, and the breakdown voltage of the semiconductor structure is high.

The first barrier material layer 105 should not be too thick nor too thin. If the first barrier material layer 105 is too thick, too much process time is spent to form the first barrier material layer 105, which may result in inefficient formation of the semiconductor structure and easily leads to an excessive volume of the semiconductor structure. If the first blocking material layer 105 is too thin, in the process of doping ions in the silicide blocking material layer 106, the first blocking material layer 105 cannot block the doping ions from entering the drift region 102, and the doping ions entering the drift region 102 are prone to cause scattering of carriers, resulting in poor current performance of the semiconductor structure. In this embodiment, in the step of forming the first barrier material layer 105, the thickness of the first barrier material layer 105 is 30 nm to 80 nm.

In this embodiment, the first barrier material layer 105 is formed by a chemical vapor deposition process. The chemical vapor deposition process is a method for generating a thin film by using one or more gas-phase compounds or simple substances containing thin film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the first barrier material layer 105, so that the thin film purity of the first barrier material layer 105 is high. In other embodiments, the first barrier material layer may be formed by an atomic layer deposition process.

Correspondingly, the forming method of the semiconductor structure further comprises the following steps: after patterning the silicide blocking material layer 106, the first blocking material layer 105 is also patterned to form a first blocking layer 110 (as shown in fig. 9).

Referring to fig. 8 and 9, the method of forming the semiconductor structure further includes: after doping ions, before patterning the silicide blocking material layer 106, forming a second blocking material layer 111 on the silicide blocking material layer 106; and patterning the second barrier material layer 111 to form a second barrier layer 112.

And subsequently, a conductive structure is formed on the silicide blocking layer, specifically, the conductive structure is formed on the second blocking layer 112, when the semiconductor structure works, charges are accumulated at the bottom of the conductive structure, and the second blocking layer 112 is used for blocking the charges accumulated at the bottom of the conductive structure from passing through the second blocking layer 112 to reach the silicide blocking layer 107, so that the charges capable of reaching the drift region 102 are correspondingly reduced, and the breakdown voltage of the semiconductor structure is higher.

In this embodiment, in the present embodiment, a chemical vapor deposition process is used to form the second barrier material layer 111. The chemical vapor deposition process is a method for generating a film by using one or more gas-phase compounds or simple substances containing film elements to perform chemical reaction, has good step coverage, and can control the deposition thickness of the second barrier material layer 111, so that the film purity of the second barrier material layer 111 is higher. In other embodiments, the second barrier material layer may be formed by an atomic layer deposition process.

Specifically, the material of the second barrier material layer 111 includes: SiCN, SiCO, SiON, SiBCN, or SiN. In this embodiment, the material of the second barrier material layer 111 includes: SiCN has higher density, can block charges and can trap the charges.

Referring to fig. 10, a drain electrode 113 is formed at the drain region.

In the step of forming the drain electrode 113 in the drain region, a source electrode 114 is also formed in the source region.

The source 114 and drain 113 serve to provide stress to the channel and enhance carrier mobility in the channel during operation of the semiconductor structure.

In this embodiment, the conductivity types of the doped ions in the drain 113 and the source 114 are the same as the conductivity type of the doped ions in the drift region 102, and are both the first type ions.

Specifically, the step of forming the drain electrode 113 and the source electrode 114 includes: and doping source and drain ions in the drain region to form a drain 113 and doping source and drain ions in the source region to form a source 114 by taking the second barrier layer 112, the silicide barrier layer 107 and the first barrier layer 110 as doping masks.

In this embodiment, the semiconductor structure is used to form an NLDMOS, and when the semiconductor structure operates, carriers in a channel are electrons, and source-drain ions are N-type ions, specifically, the N-type ions include P, As or Sb. In other embodiments, the semiconductor structure is used for forming a PLDMOS, and when the semiconductor structure operates, carriers In a channel are holes, and source and drain ions are P-type ions, specifically, the P-type ions include B, Ga or In.

Referring to fig. 11 and 12, the method of forming the semiconductor structure further includes: forming a dielectric layer 115 on the second barrier layer 112, the drain electrode 113, and the source electrode 114; etching the dielectric layer 115 above the drift region 102 to form a conductive via (not shown) exposing the second barrier layer 112; conductive structures 116 are formed in the conductive vias.

The conductive structure 116 and the drift region 102 are electrically isolated by the second blocking layer 112, the silicide blocking layer 107 and the first blocking layer 110, so that the conductive structure 116 is in a floating state, a depletion region after the LDMOS operates is widened under the action of an applied built-in electric field, the step-down distance is increased, and the voltage resistance of the LDMOS is improved.

In this embodiment, the conductive structure 116 is made of W. In other embodiments, the material of the conductive structure may also be a conductive material such as Al, Cu, Ag, or Au.

In this embodiment, the material of the dielectric layer 115 includes silicon oxide. Silicon oxide is a dielectric material with a common process and low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost for forming the dielectric layer 115.

In the step of forming the conductive via in the dielectric layer 115, a contact hole exposing the source 114, the drain 113 and the gate structure 103 is further formed; in the step of forming the conductive structure 116 in the conductive via hole, a contact plug 117 is also formed in the contact hole.

The contact plug 117 realizes electrical connection within the device and also functions to realize electrical connection from device to device.

In this embodiment, the material of the contact plug 117 is the same as that of the conductive structure 116.

In this embodiment, the silicide blocking layer 107 is formed first, and the drain 113 is formed after the silicide blocking layer 107 is formed.

In other embodiments, the drain may be formed first; and forming a silicide barrier layer after forming the drain electrode.

In other embodiments, the source is formed in the step of forming the drain.

Specifically, the step of forming the drain and the source includes: forming a barrier layer (not shown in the figure) exposing the source region and the drain region; and forming a drain electrode in the drain region and a source electrode in the source region by using the shielding layer as a doping mask.

The shielding layer is used as a doping mask for forming a source electrode and a drain electrode, in the process of forming the source electrode and the drain electrode by doping, the drift region and the well region covered by the shielding layer are protected from being doped easily, source and drain ions do not enter the drift region and the well region easily, when the semiconductor structure works, current carriers in the drift region are not scattered easily, and the current performance of the semiconductor structure is improved.

The shielding layer is made of a material which can play a role of a mask and is easy to remove, so that damage to other film layer structures is reduced when the shielding layer is removed subsequently.

In this embodiment, the material of the shielding layer is an organic material, for example: BARC material, ODL material, SOC material, photoresist, DARC material, DUO material, or APF material.

The method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after the source electrode and the drain electrode are formed.

The step of forming the silicide blocking layer comprises: after removing the shielding layer, forming a silicide blocking material layer on the grid structure and the substrate exposed by the grid structure; doping ions in the silicide blocking material layer, wherein the doped ions are doped at the bottom of the silicide blocking material layer; and after ions are doped, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the grid structure.

The method for forming the semiconductor structure further comprises the following steps: after the source electrode and the drain electrode are formed and before the silicide blocking material layer is formed, a first blocking material layer is formed on the grid electrode structure and the substrate exposed out of the grid electrode structure; in the step of forming the silicide blocking material layer, the silicide blocking material layer is formed on the first blocking material layer; and after the silicide blocking material layer is patterned, the first blocking material layer is also patterned to form a first blocking layer.

The method for forming the semiconductor structure further comprises the following steps: after doping ions, before patterning the silicide blocking material layer, forming a second blocking material layer on the silicide blocking material layer; and patterning the second barrier material layer to form a second barrier layer.

FIG. 13 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure provided by the embodiment of the invention will be described in detail with reference to the accompanying drawings.

Referring to fig. 13, the semiconductor structure of the present embodiment includes: a substrate 300, wherein the substrate 300 has a well region 301 and a drift region 302 which are adjacent to each other; a gate structure 303 located on the substrate 300 at the boundary of the well region 301 and the drift region 302; a drain 313 in the drift region 302 on one side of the gate structure 303; a silicide blocking layer 307 located on the drift region 302 between the gate structure 303 and the drain 313 region, wherein the silicide blocking layer 307 has doped ions therein, and the doped ions are located at the bottom of the silicide blocking layer 307.

The doped ions are located at the bottom of the silicide blocking layer 307, the doped ions and the dangling bonds at the bottom of the silicide blocking layer 307 are combined to form saturated bonds, accordingly, charges at the bottom of the silicide blocking layer 307 can be reduced, when the semiconductor structure works, the coupling effect of carriers in the drift region 302 and the charges at the bottom of the silicide blocking layer 307 is small, and the charges in the corresponding silicide blocking layer 307 cannot enter the drift region 302 easily, so that the breakdown voltage of the semiconductor structure is high, and the electrical performance of the semiconductor structure is improved; the doped ions at the bottom of the silicide blocking layer 307 have their own electric field, which can interfere with the original electric field line distribution in the silicide blocking layer 307, so that the electric field lines in the silicide blocking layer 307 are not easily coupled to the drift region 302 below the silicide blocking layer 307, and the charges in the silicide blocking layer 307 are not easily introduced into the drift region 302 below the silicide blocking layer 307, which is beneficial to improving the breakdown voltage of the semiconductor structure.

In this embodiment, taking the LDMOS as a planar transistor as an example, the substrate 300 is correspondingly a planar substrate. In other embodiments, when the LDMOS is a finfet, the substrate comprises a substrate and a discrete fin on the substrate.

In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate may also be a substrate made of other materials such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium oxide substrate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The drift region 302 is doped with first type ions, the well region 301 is doped with second type ions, the conductivity types of the first type ions and the second type ions are different, the well region 301 is in contact with the drift region 302, and the well region 301 serves as a lateral diffusion region to form a channel with a concentration gradient.

Specifically, in this embodiment, when the semiconductor structure is an NLDMOS, the drift region 302 has N-type ions therein, where the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions, and the well region 301 has P-type ions therein, where the P-type ions include one or more of boron ions, gallium ions, and indium ions.

In other embodiments, when the semiconductor structure is a PLDMOS, the drift region has P-type ions therein, the P-type ions include one or more of boron ions, gallium ions and indium ions, and the well region has N-type ions therein, the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

The gate structure 303 is used to control the opening and closing of the channel during operation of the semiconductor structure.

The gate structure 303 includes a gate dielectric layer 3031 located on the surface of the substrate 300 at the interface between the well region 301 and the doped region 302, and a gate layer 3032 located on the gate dielectric layer 3031.

In this embodiment, the gate structure 303 is a polysilicon gate structure, so that the gate dielectric layer 3031 is made of silicon oxide, and the gate layer 3032 is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and accordingly, the gate dielectric layer is a high-K gate dielectric layer, and the gate layer is a metal electrode layer.

The semiconductor structure further includes: a mask layer 308 is located on top of the gate structure 303. The mask layer 308 is used to protect the top of the gate structure 303 from damage.

The material of the mask layer 308 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon nitride, and boron nitride silicon carbide. In this embodiment, the mask layer 308 is made of silicon nitride.

In this embodiment, the semiconductor structure further includes: and a sidewall spacer 310 on a sidewall of the gate structure 303.

In this embodiment, the material of the sidewall 310 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.

The semiconductor structure further includes: and a source 314 located in the well region 301.

The source 314 and drain 313 serve to provide stress to the channel and enhance carrier mobility in the channel during operation of the semiconductor structure.

In this embodiment, the conductivity types of the doped ions in the drain 313 and the source 314 are the same as the conductivity types of the doped ions in the drift region 302, and are both the first type ions.

In this embodiment, the semiconductor structure is an NLDMOS, and when the semiconductor structure operates, carriers in a channel are electrons, and source-drain ions are N-type ions, specifically, the N-type ions include P, As or Sb. In other embodiments, the semiconductor structure is a PLDMOS, and when the semiconductor structure operates, carriers In a channel are holes, and source and drain ions are P-type ions, specifically, the P-type ions include B, Ga or In.

The silicide blocking layer 307 is used to prevent the growth of a silicide (Salicide) layer, so as to prevent the silicide layer from being formed on the drift region 302 between the gate structure 303 and the drain 313, avoid the adverse effect of the silicide layer on the formation of a depletion region in the drift region 302, and further ensure the voltage resistance of the NLDMOS.

In this embodiment, the silicide blocking layer 307 is made of a low-k dielectric material. The low-K dielectric material has a small dielectric constant and excellent insulating property.

Specifically, the material of the silicide blocking layer 307 includes: SiCN, SiCO, SiON, or SiBCN. In this embodiment, the material of the silicide blocking layer 307 includes SiCO.

In this embodiment, the silicide block layer 307 has dopant ions comprising C, N or F.

It should be noted that the doping concentration of the dopant ions in the silicide blocking layer 307 is not too large or too small. If the doping concentration is too large, too much process time is required correspondingly, which is not beneficial to improving the forming efficiency of the semiconductor structure and is easy to cause resource waste, and the doping concentration of the doping ions is too large, the doping ions are easy to pass through the silicide blocking layer 307 and enter the drift region 302, when the semiconductor structure works, the doping ions in the drift region 302 are easy to cause scattering of carriers, and the current performance of the corresponding semiconductor structure is not good. If the doping concentration is too small, the number of saturated bonds formed by doping ions and dangling bonds is small, a large number of dangling bonds still exist on the bottom surface of the silicide blocking layer 307, when the semiconductor structure works, the coupling effect of carriers in the drift region 302 and charges at the bottom of the silicide blocking layer 307 is strong, and the charges in the silicide blocking layer 307 easily enter the drift region 302, so that the breakdown voltage of the semiconductor structure is small; in addition, the doped ions at the bottom of the silicide blocking layer 307 have a local electric field, and when the semiconductor structure operates, the doped ions at the bottom of the silicide blocking layer 307 have a weak ability to interfere with the original distribution of the electric field lines in the silicide blocking layer 307, so that the electric field lines in the silicide blocking layer 307 are easily coupled to the drift region 302, and accordingly, the charges in the silicide blocking layer 307 easily enter the drift region 302, so that the breakdown voltage of the semiconductor structure is small. In this embodiment, in the step of doping ions in the silicide blocking layer 307, the doping concentration is 3E19 atoms per cubic centimeter to 2E20 atoms per cubic centimeter.

Note that the silicide block layer 307 is not too thick or too thin. If the silicide blocking layer 307 is too thick, it takes too much process time to form the silicide blocking layer 307, and material is easily wasted, and if the silicide blocking layer 307 is too thick, when the semiconductor structure works, too much charge is easily present in the silicide blocking layer 307, the coupling effect between the charge in the silicide blocking layer 307 and the carriers in the drift region 302 is severe, and breakdown is easily generated at the silicide blocking layer 307 on the drift region 302, which results in poor electrical performance of the semiconductor structure. When the semiconductor structure works, charges are accumulated at the bottom of the conductive structure 316, and if the silicide blocking layer 307 is too thin, the silicide blocking layer 307 cannot well block the charges at the bottom of the conductive structure from entering the drift region 302, and breakdown is likely to occur at the silicide blocking layer 307 on the drift region 302, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the thickness of the silicide blocking layer 307 is 30 nm to 80 nm.

The semiconductor structure further includes: a first blocking layer 310 is disposed between the silicide blocking layer 307 and the substrate 300, and between the silicide blocking layer 307 and the gate structure 303.

The first blocking layer 310 makes the doped ions in the silicide blocking layer 307 not easily enter the drift region 302, and makes the carriers in the drift region 302 not easily scatter when the semiconductor structure works, which is beneficial to improving the current performance of the semiconductor structure.

Specifically, the material of the first blocking layer 310 includes a blocking host material and dopant ions doped in the blocking host material, and the blocking host material includes: SiN, SiON, SiBCN, and SiCN, and the dopant ions include one or more of C, N, F and B. In this embodiment, the blocking host material comprises SiN, the dopant ions comprise one or more of C, N, F and B, and the SiN has a relatively high density and is capable of blocking charges from entering the drift region 302 during operation of the semiconductor structure. The C, N, B or F can block the lattice gap in the first barrier layer 310, so that electrons in the silicide-block layer 307 do not readily diffuse through the first barrier layer 310 into the drift region 302. In addition, C, N, B or F, which has its own electric field, can disturb the original distribution of electric field lines in the first blocking layer 310, so that the electric field lines in the first blocking layer 310 are not easily coupled into the drift region 302, and the breakdown voltage of the semiconductor structure is high.

In this embodiment, the first barrier layer 310 should not be too thick or too thin. If the first barrier layer 310 is too thick, it takes too much process time to form the first barrier layer 310, which results in inefficient formation of the semiconductor structure and easily results in an excessively large volume of the semiconductor structure. If the first blocking layer 310 is too thin, the doped ions in the silicide blocking layer 307 easily penetrate through the first blocking layer 310 into the drift region 302, and the doped ions entering the drift region 302 easily cause scattering of carriers, resulting in poor current performance of the semiconductor structure. In this embodiment, the thickness of the first barrier layer 310 is 30 nm to 80 nm.

The semiconductor structure further includes: a second barrier layer 312 on the silicide block layer 307.

Specifically, the material of the second barrier layer 312 includes: SiCN, SiCO, SiON, SiBCN, or SiN. In this embodiment, the material of the second barrier layer 312 includes: SiCN has higher density, can block charges and can trap the charges.

The semiconductor structure further includes: a dielectric layer 315 is disposed on the second barrier layer 312, the drain 313 and the source 314.

The dielectric layer 315 is used to electrically isolate adjacent devices

In this embodiment, the material of the dielectric layer 315 includes silicon oxide. The silicon oxide is a dielectric material with a common process and a low cost, and has high process compatibility, thereby being beneficial to reducing the process difficulty and the process cost for forming the dielectric layer 315.

The semiconductor structure further includes: a conductive structure 316 extending through the dielectric layer 315 in contact with the second barrier layer 312 over the drift region 302.

The conductive structure 316 and the drift region 302 are electrically isolated by the second blocking layer 312, the silicide blocking layer 307 and the first blocking layer 310, so that the conductive structure 316 is in a floating state, the depletion region after the LDMOS operates is widened under the action of an applied built-in electric field, the step-down distance is increased, and the voltage resistance of the LDMOS is improved.

In this embodiment, the material of the conductive structure 316 is W. In other embodiments, the material of the conductive structure may also be a conductive material such as Al, Cu, Ag, or Au.

It should be noted that, the conductive structure 316 is formed on the second blocking layer 112, when the semiconductor structure operates, negative charges accumulate at the bottom of the conductive structure 316, and the second blocking layer 112 can block the charges accumulated at the bottom of the conductive structure 316 from passing through the second blocking layer 112 to reach the silicide blocking layer 107, so that the charges that can reach the drift region 102 are correspondingly reduced, and the breakdown voltage of the semiconductor structure is higher.

In addition, the semiconductor structure further includes: a contact hole plug 317, the contact hole plug 317 penetrating the dielectric layer 315 and electrically connected with the source 314, the drain 315, or the gate structure 303.

The material of the contact hole plug 317 is the same as that of the conductive structure 316.

The semiconductor structure further includes: and a lightly doped region 304 located in the drift region 302 between the drain 313 and the gate structure 303, and in the well region 301 between the source 314 and the gate structure 303.

As the size of the semiconductor structure is smaller and smaller, the length of the channel below the gate structure 303 is continuously reduced during the operation of the semiconductor structure, and the lightly doped region 304 can effectively reduce the short channel effect. In addition, in the NLDMOS, the lightly doped region 304 can also reduce the peak electric field near the drain end, thereby suppressing the hot electron effect and significantly improving the hot carrier lifetime of the device and the circuit.

In this embodiment, the semiconductor structure is an NLDMOS, and N-type ions are doped into the well region 301 and the drift region 302 exposed by the gate structure 303 to form the lightly doped region 304. In other embodiments, the semiconductor structure is a PLDMOS, and P-type ions are doped in the exposed well region and drift region of the gate structure.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate, and a drain region is arranged in the drift region;

forming a gate structure on the substrate at the junction of the well region and the drift region;

forming a drain electrode in the drain region;

forming a silicide blocking material layer on the grid structure and the substrate exposed by the grid structure;

doping ions in the silicide blocking material layer, wherein the doped ions are doped at the bottom of the silicide blocking material layer;

and after ions are doped, patterning the silicide blocking material layer, and forming the silicide blocking layer on the drift region between the drain region and the grid structure.

2. The method of forming a semiconductor structure of claim 1, further comprising: after the grid structure is formed and before the silicide blocking material layer is formed, a first blocking material layer is formed on the grid structure and the substrate exposed out of the grid structure;

in the step of forming the silicide blocking material layer, the silicide blocking material layer is formed on the first blocking material layer;

and after the silicide blocking material layer is patterned, the first blocking material layer is also patterned to form a first blocking layer.

3. The method of forming a semiconductor structure of claim 2, further comprising: after doping ions, before patterning the silicide blocking material layer, forming a second blocking material layer on the silicide blocking material layer; and patterning the second barrier material layer to form a second barrier layer.

4. The method as claimed in any of claims 1 to 3, wherein in the step of doping ions in the silicide-block material layer, the doped ions comprise C, N or F.

5. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein ions are doped in the silicide-block material layer using an ion implantation process or a plasma implantation process.

6. The method as claimed in any one of claims 1 to 3, wherein the silicide blocking material layer is doped with ions by ion implantation, and the process parameters of the doped ions include: the dosage of the doping agent is 3E14 atoms per square centimeter to 2E15 atoms per square centimeter, the included angle between the incidence direction of the doping ions and the normal line of the substrate surface is less than 5 degrees, and the implantation energy of the doping ions is 1Kev to 5 Kev.

7. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein in the step of forming the silicide blocking material layer, the silicide blocking material layer has a thickness of 30 nm to 80 nm.

8. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein the material of the silicide blocking material layer is a low-k dielectric material.

9. The method of forming a semiconductor structure of any of claim 8, wherein the material of the layer of silicide blocking material comprises: SiCN, SiCO, SiON, or SiBCN.

10. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein the silicide-blocking material layer is formed using a chemical vapor deposition process or an atomic layer deposition process.

11. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein the step of forming the drain and the silicide block layer comprises: forming the drain electrode; forming the silicide blocking layer after forming the drain electrode;

or, forming the silicide blocking layer; and forming the drain electrode after forming the silicide barrier layer.

12. The method of forming a semiconductor structure of claim 2 or 3, wherein the first barrier material layer comprises a barrier host material and dopant ions doped in the barrier host material, the barrier host material comprising: SiN, SiON, SiBCN, and SiCN, and the dopant ions include one or more of C, N, F and B.

13. A semiconductor structure, comprising:

the drift region is arranged in the substrate and is adjacent to the well region;

the grid structure is positioned on the substrate at the junction of the well region and the drift region;

the drain electrode is positioned in the drift region on one side of the grid structure;

and the silicide blocking layer is positioned on the drift region between the grid structure and the drain electrode, doped ions are arranged in the silicide blocking layer, and the doped ions are positioned at the bottom of the silicide blocking layer.

14. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the first blocking layer is positioned between the silicide blocking layer and the substrate and between the silicide blocking layer and the grid structure.

15. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: and the second barrier layer is positioned on the silicide barrier layer.

16. The semiconductor structure of any of claims 13 to 15, wherein said silicide block layer has doped ions comprising C, N or F.

17. The semiconductor structure of any one of claims 13 to 15, wherein a doping concentration of dopant ions at a bottom of the silicide block layer is from 3E19 atoms per cubic centimeter to 2E20 atoms per cubic centimeter.

18. The semiconductor structure of any of claims 13 to 15, wherein the silicide block layer has a thickness of 30 nm to 80 nm.

19. The semiconductor structure of any of claims 13 to 15, wherein the material of the silicide block layer comprises: SiCN, SiCO, SiON or SiBCN with doped ions.

20. The semiconductor structure of claim 14 or 15, wherein the first barrier layer comprises a blocking host material and dopant ions doped in the blocking host material, the blocking host material comprising: SiN, SiON, SiBCN, and SiCN, and the dopant ions include one or more of C, N, F and B.