CN114823904A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114823904A
CN114823904A CN202110128776.1A CN202110128776A CN114823904A CN 114823904 A CN114823904 A CN 114823904A CN 202110128776 A CN202110128776 A CN 202110128776A CN 114823904 A CN114823904 A CN 114823904A
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region
deep well
well region
forming
semiconductor structure
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陈宗高
蒲贤勇
张海波
杨林宏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Priority to CN202110128776.1A priority Critical patent/CN114823904A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate having a deep well region therein, the deep well region having a first conductivity type; a drift region and a body region located adjacent within the deep well region, the body region having a second conductivity type, the drift region having a first conductivity type, and the first and second conductivity types being opposite; a source region located within the body region, and the source region having a first conductivity type; the drain region is positioned in the deep well region, has a first conductivity type, and the top of the drain region is lower than the bottom of the source region; and the gate structure is positioned on the surface of part of the body region and the surface of part of the drift region. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
An LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device that forms a lateral current path on the surface of a Semiconductor substrate through planar diffusion (planar diffusion), and is commonly used in radio frequency power circuits. In contrast to conventional MOS transistors, a lightly doped region, referred to as a drift region, is typically provided between the source and drain regions of an LDMOS transistor. Therefore, when the LDMOS transistor is connected to a high voltage between the source region and the drain region, the drift region can withstand a higher voltage drop due to the relatively low impurity concentration and the high resistance state of the drift region, so that the LDMOS transistor can have a higher breakdown voltage.
The LDMOS transistor is compatible with a Complementary Metal Oxide Semiconductor (CMOS) process, so that the LDMOS transistor is widely used in a power device. For an LDMOS transistor used as a power integrated circuit, the on-resistance (Rdson) and the Breakdown Voltage (BV) are two important metrics for measuring the device performance.
However, the performance of the existing LDMOS transistor is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of a lateral double-diffusion metal oxide semiconductor.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate having a deep well region therein, the deep well region having a first conductivity type; a drift region and a body region located adjacent within the deep well region, the body region having a second conductivity type, the drift region having a first conductivity type, and the first and second conductivity types being opposite; a source region located within the body region, and the source region having a first conductivity type; the drain region is positioned in the deep well region, has a first conductivity type, and the top of the drain region is lower than the bottom of the source region; and the gate structure is positioned on the surface of part of the body region and the surface of part of the drift region.
Optionally, the drift region includes opposite first and second sides; the body region is adjacent to the first side of the drift region, and the drain region is located in the deep well region of the side wall of the second side of the drift region.
Optionally, the substrate further comprises: a shallow well region located within a portion of the deep well region, the shallow well region having a second conductivity type; the body region and the drift region are located in the shallow well region, and the shallow well region is communicated with the deep well region located on the second side wall of the drift region.
Optionally, the top of the drain region is lower than the bottom of the drift region.
Optionally, the method further includes: and the first plug is positioned in the deep well region, is electrically connected with the drain region, and has a first isolation layer between the side wall of the first plug and the deep well region.
Optionally, the material of the first plug includes: doped polysilicon or metal, the metal comprises one or more of copper, tungsten, aluminum, titanium and nickel.
Optionally, the method further includes: and the second isolation layer is positioned in the deep well region and the drift region, the deep well region is exposed out of the surface of the second isolation layer, and the bottom of the second isolation layer is connected with the top of the first isolation layer.
Optionally, the method further includes: the first plug penetrates through the conducting area, and the conducting area is provided with a first conduction type.
Optionally, the bottom of the conducting region is higher than the top of the drain region.
Optionally, the deep well region has a first doping concentration, the conduction region has a second doping concentration, and the second doping concentration is greater than the first doping concentration.
Optionally, the method further includes: and the second plug is positioned on the surface of the substrate and electrically connected with the source region.
Optionally, the method further includes: the barrier layer is positioned on the surface of the drift region and the surface of the side wall of one side of the grid structure, and one side of the grid structure is positioned on the drift region; and a third plug located on the barrier layer, wherein the barrier layer is located between the gate structure and the third plug.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a deep well region in the substrate, the deep well region having a first conductivity type; forming a drift region and a body region adjacent to each other in the deep well region, wherein the body region has a second conductivity type, the drift region has a first conductivity type, and the first conductivity type and the second conductivity type are opposite; forming a source region in the body region, wherein the source region has a first conductive type; forming a drain region in the deep well region, wherein the drain region has a first conductivity type, and the top of the drain region is lower than the bottom of the source region; and forming a gate structure on part of the surface of the body region and part of the surface of the drift region.
Optionally, the top of the drain region is lower than the bottom of the drift region.
Optionally, the method further includes: forming a shallow well region in a portion of the deep well region, the shallow well region having a second conductivity type; the body region and the drift region are located in the shallow well region, and the shallow well region is communicated with the deep well region located on the second side wall of the drift region.
Optionally, the method further includes: and forming a first plug electrically connected with the drain region in the deep well region, wherein a first isolation layer is arranged between the side wall of the first plug and the deep well region.
Optionally, the method further includes: before the first plug is formed, a second isolation layer is formed in the deep well region and the drift region, the deep well region is exposed out of the surface of the second isolation layer, and the bottom of the second isolation layer is connected with the top of the first isolation layer.
Optionally, the method for forming the first isolation layer and the second isolation layer includes: forming a first opening in the deep well region and the drift region; forming an initial isolation layer in the first opening; forming a second opening exposing the surface of the drain region in the initial isolation layer and the deep well region, wherein the bottom of the second opening is lower than the bottom of the initial isolation layer; and filling an insulating material in the second opening, wherein the insulating material in the second opening lower than the bottom of the first opening forms a first isolation layer, and the initial isolation layer in the first opening and part of the insulating material in the second opening form a second isolation layer.
Optionally, the method further includes: and forming a second plug on the surface of the substrate, wherein the second plug is electrically connected with the source region.
Optionally, the method further includes: the barrier layer is arranged on the surface of the drift region and the surface of the side wall of one side of the grid structure, and one side of the grid structure is positioned on the drift region; and forming a third plug on the barrier layer, wherein the barrier layer is positioned between the gate structure and the third plug.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, the deep well region is internally provided with the adjacent body region and the drift region, the grid structure is positioned on the surface of the body region and the surface of the drift region, and the drain region is positioned in the deep well region, and the top of the drain region is lower than the bottom of the source region, namely, the size of the drain region in the direction vertical to the surface of the substrate is larger, so that the distance between the deep drain region and the grid structure is larger, the increase of the distance between the drain region and the grid structure is beneficial to improving the breakdown voltage, and the high voltage resistance of the formed semiconductor structure is improved.
Furthermore, a shallow well region is arranged in the deep well region, the conduction type of the shallow well region is opposite to that of the deep well region, the shallow well region is communicated with the deep well region on the second side wall of the drift region, so that a depletion region can be formed in the contact region of the shallow well region and the deep well region, the depletion region is favorable for improving the breakdown voltage of a device, and the high voltage resistance of the formed semiconductor structure is further improved.
Furthermore, the top of the drain region is lower than the bottom of the drift region, that is, the size of the drain region in the direction vertical to the surface of the substrate is larger, and the depth of the drain region is deeper, so that the breakdown voltage of the formed semiconductor structure is kept unchanged when the distance between the drain region and the gate structure in the horizontal direction is reduced, and therefore, the breakdown voltage can be not reduced, and simultaneously, more devices are formed in a unit area, and the integration level is improved.
Further, the semiconductor structure further comprises: the barrier layer is positioned on the surface of the drift region and the surface of the side wall of one side of the grid structure, and one side of the grid structure is positioned on the drift region; a third plug located on the barrier layer, the barrier layer located between the gate structure and the third plug. When the semiconductor device works, the corner of the junction of the grid structure and the drift region have higher electric fields, and the third plug positioned on the surface of the barrier layer can redistribute the higher electric fields near the grid structure and the drift region, so that the electric fields are reduced, and the pressure resistance of the formed semiconductor structure is improved.
Furthermore, a conducting area is arranged in the deep well area, the conducting type of the conducting area is the same as that of the deep well area, the second doping concentration of the conducting area is greater than the first doping concentration of the deep well area, when the device works, when current flows from the drain area to the source area through the deep well area, the conducting resistance of the conducting area in the deep well area is smaller, and therefore the conducting current is favorably improved, and the performance of the formed semiconductor structure is improved.
According to the forming method of the semiconductor structure, the deep well region is formed in the substrate, the drain region is formed in the deep well region, the top of the drain region is lower than the bottom of the source region, namely the size of the drain region in the direction vertical to the surface of the substrate is larger, so that the distance between the deep drain region and the grid structure is larger, the distance between the drain region and the grid structure is increased, the breakdown voltage is favorably improved, and the high-voltage resistance of the formed semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment;
fig. 2 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the performance of the conventional lateral double diffused mos is to be improved.
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
First, the reason for the poor performance of the conventional semiconductor structure will be described in detail with reference to the accompanying drawings, and fig. 1 is a schematic structural diagram of the semiconductor structure in an embodiment.
Referring to fig. 1, the semiconductor structure includes: a substrate 100, wherein the substrate 100 has a drift region 120 and a body region 110 therein, and the conductivity type of the drift region 120 is opposite to the conductivity type of the body region 110; a gate structure 150 on the substrate 100, wherein a portion of the gate structure 150 is located on the drift region 120, and a portion of the gate structure 150 is located on the body region 110; a barrier layer 160 located adjacent to a portion of the surface of the drift region 120 of the gate structure 150, and the barrier layer 160 is located on the top surface and sidewall surface of the gate structure 150; a drain region 140 in the drift region 120 on one side of the barrier layer 160 and the gate structure 150, and a source region 130 in the body region 110 on one side of the gate structure 150.
In the above structure, the barrier layer 160 functions to increase the distance between the drain region 140 and the gate structure 110, thereby improving the breakdown voltage of the device.
However, when the device is turned on, the distance between the drain region and the channel is still short, that is, the distance between the drain region and the gate structure is short in the direction parallel to the surface of the substrate, so that the breakdown voltage of the formed device is still low.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: the deep well region is positioned in the substrate and has a second conduction type, and the side wall of the deep well region is contacted with the side wall of the drift region; a source region located within the body region, and the source region having a first conductivity type; the device comprises a grid structure, the distance between the drain region and the grid structure is increased, so that the breakdown voltage is improved, and the high voltage resistance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided.
The material of the substrate 200 includes silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the substrate 200 is silicon.
With continued reference to fig. 2, a deep well region 210 is formed in the substrate 200, wherein the deep well region 210 has a first conductivity type.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the deep well region 210 is an N-type.
In the present embodiment, the deep well region 210 is formed by doping N-type ions into the substrate 200 through an ion implantation process.
It should be noted that the substrate 200 exposes the surface of the deep well region 210.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the conductivity type of the deep well region is P-type.
The N-type ions are one or more of phosphorus ions, arsenic ions and antimony ions; the P-type ions are one or more of boron ions, indium ions and gallium ions.
In other embodiments, the method for forming the substrate and the deep well region includes: providing an initial substrate; forming an initial first deep well region in the initial substrate; and forming an initial second deep well region on the surface of the initial substrate by adopting an epitaxial growth process, wherein the initial substrate and the initial second deep well region form a substrate, and the initial first deep well region and the initial second deep well region form a deep well region.
Referring to fig. 3, a shallow well region 220 is formed in the deep well region 210, wherein the shallow well region 220 has a second conductivity type.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the shallow well region 220 is a P-type.
In the present embodiment, the shallow well region 220 is formed by doping P-type ions into the substrate 200 through an ion implantation process.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the conductivity type of the shallow well region is N-type.
Specifically, the implantation energy of the ion implantation process for forming the shallow well region 220 is less than the implantation energy of the ion implantation process for forming the deep well region 210, so that the depth of the shallow well region 220 is less than the depth of the deep well region 210.
In other embodiments, the shallow well region may not be formed.
Referring to fig. 4, adjacent drift regions 230 and body regions 240 are formed in the deep well region 210, the body regions 240 have a second conductivity type, the drift regions 230 have a first conductivity type, and the first conductivity type and the second conductivity type are opposite.
Specifically, in the present embodiment, the drift region 230 and the body region 240 are formed in the shallow well region 220.
The drift region 220 is used for separating a drain region and a channel region formed subsequently, so that a current channel of the semiconductor structure is prolonged, and breakdown voltage is improved.
The body region 230 serves to separate a source region and a channel region, which are formed later.
The method for forming the drift region 230 includes: a first mask layer (not shown) is formed on the surface of the substrate 200, and the first mask layer is used for defining the position and the size of the drift region 220; with the first mask layer as a mask, an ion implantation process is performed on the substrate 200 to form the drift region 230 in the shallow well region 220.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the drift region 230 is formed by doping N-type ions into the substrate 200 through an ion implantation process.
Specifically, the implantation energy of the ion implantation process for forming the drift region 230 is less than the implantation energy of the ion implantation process for forming the shallow well region 220, so that the depth of the drift region 230 is less than the depth of the shallow well region 220.
The method for forming the body region 240 includes: forming a second mask layer (not shown) on the surface of the substrate 200, wherein the second mask layer is used for defining the position and size of the body region 240; with the second mask layer as a mask, an ion implantation process is performed on the substrate 200 to form the body region 240 in the shallow well region 220.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the body region 240 is formed by doping P-type ions into the substrate 200 through an ion implantation process.
Specifically, the implantation energy of the ion implantation process for forming the body region 240 is less than the implantation energy of the ion implantation process for forming the shallow well region 220, so that the depth of the body region 240 is less than the depth of the shallow well region 220.
In particular, the drift region 230 includes opposing first and second sides 231, 232; the body region 240 is adjacent to the first side 231 of the drift region 230.
By forming the shallow well region 220 in the deep well region 210, the conductivity type of the shallow well region 220 is opposite to that of the deep well region 210, and the shallow well region 220 is communicated with the deep well region 210 located on the second side wall of the drift region 230, so that a depletion region a can be formed in a region where the shallow well region 220 and the deep well region 210 are in contact, and the depletion region a is beneficial to improving the breakdown voltage of a device, thereby further improving the high voltage resistance of the formed semiconductor structure.
Referring to fig. 5, a gate structure 250 is formed on a portion of the surface of the body region 240 and a portion of the surface of the drift region 230.
The forming method of the gate structure 250 comprises the following steps: forming a gate structure material layer (not shown) on the substrate 200; forming a patterned layer (not shown) on the gate structure material layer, the patterned layer covering a portion of the gate structure material layer on the drift region 230 and on a portion of the body region 240; and etching the gate structure material layer by using the patterning layer as a mask until the surface of the substrate 200 is exposed, so as to form the gate structure 250.
The gate structure 250 includes: a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the gate structure 250 further includes: and a protective layer (not shown) on the top surface of the gate layer, wherein the protective layer is used for protecting the top surface of the gate layer, reducing the influence of the gate layer on the subsequent process, and facilitating the improvement of the performance of the formed semiconductor structure.
With reference to fig. 5, a sidewall spacer (not shown) is formed on the sidewall of the gate structure 250.
The side walls are used for protecting the side wall surfaces of the gate structures 250 from being influenced by subsequent processes, so that the appearance is maintained, and the stability of electrical properties is improved; on the other hand, for locating the positions of subsequently formed source and drain regions.
The forming method of the side wall comprises the following steps: forming a sidewall material layer (not shown) on the surface of the substrate 200 and the top surface and sidewall surface of the gate structure 250; and etching back the side wall material layer until the surface of the substrate 200 and the top surface of the gate layer are exposed to form the side wall.
The material of the side wall comprises a dielectric material, and the dielectric material comprises one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the material of the sidewall spacer includes silicon nitride.
Referring to fig. 6, a source region 260 is formed in the body 240 region, and the source region 260 has a first conductivity type.
The forming method of the source region 260 includes: and performing ion implantation on the body region 240 by using the side walls and the gate structure 250 as a mask to form the source region 260.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the source region 260 is an N-type.
Note that the substrate 200 exposes the top surface of the source region 260.
In the present embodiment, the semiconductor structure to be formed is a P-type LDMOS, and the conductivity type of the source region 260 is P-type.
Referring to fig. 7, a drain region 270 is formed in the deep well region 210, the drain region 270 has a first conductivity type, and a top of the drain region 270 is lower than a bottom of the source region 260.
In this embodiment, the top of the drain region 270 is lower than the bottom of the drift region 230.
The drift region 230 includes opposing first and second sides 231, 232; the body region 240 is adjacent to the first side 231 of the drift region 230 and the drain region 270 is located in the deep well region 210 on the sidewall of the second side 232 of the drift region 230.
The method for forming the drain region 270 includes: forming a third mask layer (not shown) on the substrate 200, wherein the third mask layer exposes the surface of the deep well region 210 on the sidewall of the second side 232 of the drift region 230; and performing ion implantation on the deep well region 210 by using the third mask layer as a mask to form the drain region 270.
By forming the deep well region 210 in the substrate 200 and forming the drain region 270 in the deep well region 210, the top of the drain region 270 is lower than the bottom of the source region 260, that is, the size of the drain region 270 in the direction perpendicular to the surface of the substrate 200 is larger, so that the distance between the deep drain region 270 and the gate structure 250 formed on the drift region 230 is larger, and the increase in the distance between the drain region 270 and the gate structure 250 is beneficial to improving the breakdown voltage, so that the high voltage resistance of the formed semiconductor structure is improved.
In this embodiment, after the source region 260 is formed, the drain region 270 is formed. In other embodiments, the drain region may also be formed before the source region is formed.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the drain region 270 is N-type.
Referring to fig. 8, a conductive region 280 is formed in the deep well region 210, and the conductive region 280 has a first conductivity type.
In this embodiment, the bottom of the conductive region 280 is higher than the top of the drain region 270.
In this embodiment, the conduction region 280 has a second doping concentration, the deep well region 270 has a first doping concentration, and the second doping concentration is greater than the first doping concentration.
The forming method of the conducting region 280 includes: forming a fourth mask layer (not shown) on the substrate 200, wherein the fourth mask layer exposes the surface of the deep well region 210 on the sidewall of the second side 232 of the drift region 230; and performing ion implantation on the deep well region 210 by using the fourth mask layer as a mask to form the conduction region 280.
By forming the conducting region 280 in the deep well region 210, the conducting region 280 and the deep well region 210 have the same conductivity type, and the conducting region 280 has the second doping concentration greater than the first doping concentration of the deep well region 210, when the device operates, and when current flows from the drain region 270 to the source region 260 through the deep well region 210, the conducting resistance of the conducting region 280 located in the deep well region 210 is small, thereby facilitating improvement of conducting current and improving the performance of the formed semiconductor structure.
In this embodiment, the bottom of the conducting region 280 is higher than the top of the drain region 270.
In other embodiments, the bottom of the conducting region may also be flush or lower than the top of the drain region.
In other embodiments, the conductive region may not be formed.
Next, a first isolation layer is formed in the deep well region 210; forming a second isolation layer in the deep well region 210 and the drift region 230, wherein the deep well region 210 exposes a surface of the second isolation layer, and a bottom of the second isolation layer is connected to a top of the first isolation layer, and please refer to fig. 9 to fig. 10 in the forming process of forming the first isolation layer and the second isolation layer.
Referring to fig. 9, a first opening (not shown) is formed in the deep well region 210 and the drift region 230; an initial isolation layer 291 is formed within the first opening.
In the present embodiment, after the conductive region 280 is formed, the first opening is formed in the deep well region 210, the drift region 230 and the conductive region 280.
In this embodiment, the initial isolation layer 291 is also on the surface of the substrate 200.
Referring to fig. 10, a second opening (not shown) exposing the surface of the drain region 270 is formed in the initial isolation layer 291 and the deep well region 210, and the bottom of the second opening is lower than the bottom of the initial isolation layer 291; the second opening is filled with an insulating material, the insulating material in the second opening below the bottom of the first opening forms a first isolation layer 2921, the initial isolation layer 291 in the first opening and a portion of the insulating material in the second opening forms a second isolation layer 2922.
The first isolation layer 2921 functions to electrically isolate the sidewall of the first plug, which is formed later, from the deep well region 210, thereby applying a voltage to the drain region 270 through the first plug.
The second isolation layer 2922 functions to increase the distance between the drain region 280 and the gate structure 250, so that the path of the operating current of the semiconductor structure is increased, thereby increasing the breakdown voltage of the semiconductor structure.
The insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and combinations of one or more of silicon oxycarbonitride.
In this embodiment, the material of the first isolation layer 2921 is silicon oxide, and the material of the second isolation layer 2922 is silicon oxide.
In other embodiments, the first isolation layer may be formed first, and then the second isolation layer may be formed.
In other embodiments, the first isolation layer and the second isolation layer may be formed by a conventional method in the art, and are not limited herein.
Referring to fig. 11, a first plug 310 electrically connected to the drain region 270 is formed in the deep well region 210, and the first isolation layer 2921 is disposed between a sidewall of the first plug 310 and the deep well region 210.
The first isolation layer 2921 is arranged between the side wall of the first plug 310 and the deep well region 210, so that the first isolation layer 2921 can form an isolation effect between the first plug 310 and the deep well region 210.
Specifically, in the present embodiment, the deep well region 210 has a conduction region 280, and the first plug 310 further penetrates through the conduction region 280.
Specifically, the first plug 310 also penetrates the second isolation layer 2922.
Referring to fig. 12, a second plug 320 is formed on the surface of the substrate 200, and the second plug 320 is electrically connected to the source region 260.
The source region 260 is electrically connected to peripheral circuits through the second plug 320.
With reference to fig. 12, a blocking layer 331 is formed on the surface of the drift region 230 and the surface of a sidewall of the gate structure 250, and one side of the gate structure 250 is located on the drift region 230; a third plug 330 is formed over the blocking layer and the blocking layer 331 is between the gate structure 250 and the third plug 330.
In other embodiments, the barrier layer and the third plug on the barrier layer may not be formed.
A barrier layer 331 passing through the surface of the drift region 230 and the surface of one side wall of the gate structure 250, and one side of the gate structure 250 being located on the drift region 230; a third plug 330 is formed on the blocking layer 331, and the blocking layer 331 is located between the gate structure 250 and the third plug 330. When the semiconductor device works, the corner of the gate structure 250 and the drift region 230 have higher electric fields, and the third plug 330 located on the surface of the barrier layer 331 enables the higher electric fields near the gate structure 250 and the drift region 230 to be redistributed by the third plug 330, so that the electric field is reduced, and the pressure resistance of the formed semiconductor structure is improved.
In this embodiment, the method for forming a semiconductor structure further includes: a fourth plug 340 is formed on the surface of the substrate 200, and the fourth plug 340 is electrically connected to the first plug 310.
The drain region 270 is electrically connected to a peripheral circuit through the first and fourth plugs 310 and 340.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 12, which includes: a substrate 200, the substrate 200 having a deep well region 210 therein, the deep well region 210 having a first conductivity type; a drift region 230 and a body region 240 adjacent to each other within the deep well region 210, the body region 240 having a second conductivity type, the drift region 230 having a first conductivity type, and the first and second conductivity types being opposite; a source region 260 located within the body region 240, and the source region 260 having a first conductivity type; a drain region 270 located within the deep well region 210, the drain region 270 having a first conductivity type, and a top of the drain region 270 being lower than a bottom of the source region 260; a gate structure 250 located at a surface of a portion of the body region 240 and a surface of a portion of the drift region 230.
The deep well region 210 has an adjacent body region 240 and a drift region 230 therein, the gate structure 250 is located on the surface of the body region 240 and the surface of the drift region 230, since the drain region 270 is located in the deep well region 210, and the top of the drain region 270 is lower than the bottom of the source region 260, that is, the size of the drain region 270 along the direction perpendicular to the surface of the substrate 200 is larger, so that the distance between the deep drain region 270 and the gate structure 250 is larger, and the distance between the drain region 270 and the gate structure 250 is increased, which is beneficial to improving the breakdown voltage, so that the high voltage resistance of the formed semiconductor structure is improved.
The following detailed description is made with reference to the accompanying drawings.
Specifically, the drift region 230 includes a first side 231 (shown in fig. 4) and a second side 232 (shown in fig. 4) that are opposite; the body region 240 is adjacent to the first side 231 of the drift region 230 and the drain region 270 is located in the deep well region 210 on the sidewall of the second side 231 of the drift region 230.
In this embodiment, the substrate 200 further includes: a shallow well region 220 located within a portion of the deep well region 210, the shallow well region 220 having a second conductivity type; the body region 240 and the drift region 230 are located in the shallow well region 220, and the shallow well region 220 communicates with the deep well region 210 located on the sidewall of the second side 232 of the drift region 230.
Since the deep well region 210 has the shallow well region 220 therein, the conductivity type of the shallow well region 220 is opposite to that of the deep well region 210, and the shallow well region 220 is communicated with the deep well region 210 located on the side wall of the second side 232 of the drift region 230, a depletion region a (shown in fig. 4) can be formed in the contact region between the shallow well region 210 and the deep well region 220, and the depletion region a is favorable for improving the breakdown voltage of the device, so as to further improve the high voltage resistance of the formed semiconductor structure.
In this embodiment, the top of the drain region 270 is lower than the bottom of the drift region 230.
The top of the drain region 270 is lower than the bottom of the drift region 230, that is, the size of the drain region 270 in the direction perpendicular to the surface of the substrate 200 is larger, and the depth of the drain region 270 is deeper, so that the breakdown voltage of the formed semiconductor structure is kept unchanged when the distance between the drain region 270 and the gate structure 250 in the horizontal direction is reduced, and therefore, a larger number of devices can be formed in a unit area while the breakdown voltage is not reduced, which is favorable for improving the integration level.
In this embodiment, the semiconductor structure further includes: the first plug 310 is located in the deep well region 210, the first plug 310 is electrically connected to the drain region 270, and a first isolation layer 2921 is located between the sidewall of the first plug 270 and the deep well region 210.
The material of the first plug 310 includes: doped polysilicon or metal, the metal comprises one or more of copper, tungsten, aluminum, titanium and nickel.
In this embodiment, the material of the first plug 310 is polysilicon. In other embodiments, the material of the first plug is tungsten.
In this embodiment, the semiconductor structure further includes: and a second isolation layer 2922 disposed in the deep well region 210 and the drift region 230, wherein the surface of the second isolation layer 2922 is exposed from the deep well region 210, and the bottom of the second isolation layer 2922 is connected to the top of the first isolation layer 2921.
Specifically, the first plug 310 also penetrates the second isolation layer 2922.
In this embodiment, the semiconductor structure further includes: a conductive region 280 located in the deep well region 210, wherein the first plug 310 penetrates the conductive region 280, and the conductive region 280 has a first conductivity type.
Specifically, the bottom of the conductive region 280 is higher than the top of the drain region 270.
In the present embodiment, the deep well region 210 has a first doping concentration, the conduction region 280 has a second doping concentration, and the second doping concentration is greater than the first doping concentration.
The deep well region 210 is provided with a conduction region 280, the conduction type of the conduction region 280 is the same as that of the deep well region 210, and the conduction region 280 has a second doping concentration greater than the first doping concentration of the deep well region 210, when the device works and current flows from the drain region 270 to the source region 260 through the deep well region 210, the conduction resistance of the conduction region 280 located in the deep well region 210 is small, so that the conduction current is improved, and the performance of the formed semiconductor structure is improved.
In this embodiment, the semiconductor structure further includes: a second plug 320 located on the surface of the substrate 200, wherein the second plug 320 is electrically connected to the source region 260.
In this embodiment, the semiconductor structure further includes: a barrier layer 331 located on the surface of the drift region 230 and on a sidewall surface of one side of the gate structure 250, and one side of the gate structure 250 is located on the drift region 230; a third plug 330 on the blocking layer 331, and the blocking layer 331 is between the gate structure 250 and the third plug 330.
The semiconductor structure further includes: a barrier layer 331 located on the surface of the drift region 230 and a sidewall surface of one side of the gate structure 250, and a third plug 330 located on the barrier layer 331. When the semiconductor device works, the corner of the gate structure 250 and the drift region 230 have higher electric fields, and the third plug 330 located on the surface of the barrier layer 331 enables the higher electric fields near the gate structure 250 and the drift region 230 to be redistributed by the third plug 330, so that the electric field is reduced, and the pressure resistance of the formed semiconductor structure is improved.
In this embodiment, the semiconductor structure further includes: a fourth plug 340 on the surface of the substrate 200, wherein the fourth plug 340 is electrically connected to the first plug 310.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
a substrate having a deep well region therein, the deep well region having a first conductivity type;
a drift region and a body region located adjacent within the deep well region, the body region having a second conductivity type, the drift region having a first conductivity type, and the first and second conductivity types being opposite;
a source region located within the body region, and the source region having a first conductivity type;
the drain region is positioned in the deep well region, has a first conductivity type, and the top of the drain region is lower than the bottom of the source region;
and the gate structure is positioned on the surface of part of the body region and the surface of part of the drift region.
2. The semiconductor structure of claim 1, wherein the drift region includes opposing first and second sides; the body region is adjacent to the first side of the drift region, and the drain region is located in the deep well region of the side wall of the second side of the drift region.
3. The semiconductor structure of claim 2, wherein the substrate further comprises: a shallow well region located within a portion of the deep well region, the shallow well region having a second conductivity type; the body region and the drift region are located in the shallow well region, and the shallow well region is communicated with the deep well region located on the second side wall of the drift region.
4. The semiconductor structure of claim 1, wherein a top of the drain region is lower than a bottom of the drift region.
5. The semiconductor structure of claim 1, further comprising: and the first plug is positioned in the deep well region, is electrically connected with the drain region, and has a first isolation layer between the side wall of the first plug and the deep well region.
6. The semiconductor structure of claim 5, in which a material of the first plug comprises: doped polysilicon or metal, the metal comprises one or more of copper, tungsten, aluminum, titanium and nickel.
7. The semiconductor structure of claim 5, further comprising: and the second isolation layer is positioned in the deep well region and the drift region, the deep well region is exposed out of the surface of the second isolation layer, and the bottom of the second isolation layer is connected with the top of the first isolation layer.
8. The semiconductor structure of claim 5, further comprising: the first plug penetrates through the conducting area, and the conducting area is provided with a first conduction type.
9. The semiconductor structure of claim 8, wherein a bottom of the conduction region is higher than a top of the drain region.
10. The semiconductor structure of claim 8, wherein the deep well region has a first doping concentration, the pass-through region has a second doping concentration, and the second doping concentration is greater than the first doping concentration.
11. The semiconductor structure of claim 1, further comprising: and the second plug is positioned on the surface of the substrate and electrically connected with the source region.
12. The semiconductor structure of claim 1, further comprising: the barrier layer is positioned on the surface of the drift region and the surface of the side wall of one side of the grid structure, and one side of the grid structure is positioned on the drift region; and a third plug located on the barrier layer, wherein the barrier layer is located between the gate structure and the third plug.
13. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a deep well region in the substrate, the deep well region having a first conductivity type;
forming a drift region and a body region adjacent to each other in the deep well region, wherein the body region has a second conductivity type, the drift region has a first conductivity type, and the first conductivity type and the second conductivity type are opposite;
forming a source region in the body region, wherein the source region has a first conductive type;
forming a drain region in the deep well region, wherein the drain region has a first conductivity type, and the top of the drain region is lower than the bottom of the source region;
and forming a gate structure on part of the surface of the body region and part of the surface of the drift region.
14. The method of forming a semiconductor structure of claim 13, wherein a top of the drain region is lower than a bottom of the drift region.
15. The method of forming a semiconductor structure of claim 13, further comprising: forming a shallow well region in a portion of the deep well region, the shallow well region having a second conductivity type; the body region and the drift region are located in the shallow well region, and the shallow well region is communicated with the deep well region located on the second side wall of the drift region.
16. The method of forming a semiconductor structure of claim 13, further comprising: and forming a first plug electrically connected with the drain region in the deep well region, wherein a first isolation layer is arranged between the side wall of the first plug and the deep well region.
17. The method of forming a semiconductor structure of claim 16, further comprising: before the first plug is formed, a second isolation layer is formed in the deep well region and the drift region, the deep well region is exposed out of the surface of the second isolation layer, and the bottom of the second isolation layer is connected with the top of the first isolation layer.
18. The method of forming a semiconductor structure of claim 17, wherein the method of forming the first and second spacers comprises: forming a first opening in the deep well region and the drift region; forming an initial isolation layer in the first opening; forming a second opening exposing the surface of the drain region in the initial isolation layer and the deep well region, wherein the bottom of the second opening is lower than the bottom of the initial isolation layer; and filling an insulating material in the second opening, wherein the insulating material in the second opening lower than the bottom of the first opening forms a first isolation layer, and the initial isolation layer in the first opening and part of the insulating material in the second opening form a second isolation layer.
19. The method of forming a semiconductor structure of claim 13, further comprising: and forming a second plug on the surface of the substrate, wherein the second plug is electrically connected with the source region.
20. The method of forming a semiconductor structure of claim 13, further comprising: the barrier layer is arranged on the surface of the drift region and the surface of the side wall of one side of the grid structure, and one side of the grid structure is positioned on the drift region; and forming a third plug on the barrier layer, wherein the barrier layer is positioned between the gate structure and the third plug.
CN202110128776.1A 2021-01-29 2021-01-29 Semiconductor structure and forming method thereof Pending CN114823904A (en)

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