CN113674688B - Drive chip, display module, display panel and test method of display panel - Google Patents
Drive chip, display module, display panel and test method of display panel Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The disclosure provides a driving chip, a display module, a display panel and a test method of the display panel, and belongs to the technical field of display. The driving chip includes: the device comprises a first test pin, a driving unit and a data selection unit; the driving unit is configured to drive the display panel to display; the input end of the data selection unit is connected with the first test pin, the output end of the data selection unit is connected with the driving unit of the driving chip, the data selection unit is configured to receive a plurality of test signals and control signals input from the first test pin and select a target test signal in the plurality of test signals according to the control signals, and the driving unit drives the display panel to perform testing according to the selected target test signal. The test pins can be reduced, the size of the driving chip is reduced, and the product cost is reduced.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a driving chip, a display module, a display panel and a test method of the display panel.
Background
With the continuous development of the flexible AMOLED technology, on one hand, due to the great process difficulty of the flexible AMOLED technology, and on the other hand, due to the higher and higher requirements of users on image quality, in order to manufacture a product with market competitiveness, many gain and compensation functions must be added on the basis of realizing display, and good display effects under different application scenarios are realized by using the functions.
At present, no matter the effect gain or the image quality compensation is completed by a unit module in a drive IC by using a logic design, a plurality of test points are usually reserved on the FPC for facilitating debugging in the initial stage of the design, the size of the test points also needs to meet certain requirements, and the same number of test pins are correspondingly required to be arranged on the IC, so that enough space is reserved on the IC and the FPC for placing the test points, the size of the IC is increased, and the design difficulty is greatly increased for the limited FPC with respect to the wiring space; especially, as the number of main board functional modules of terminals such as mobile phones and the like is increased, the available space reserved for the FPC is smaller and smaller.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The purpose of the present disclosure is to provide a driving chip, a display module, a display panel and a test method for the display panel, which can reduce test pins, and are beneficial to reducing the size of the driving chip and reducing the product cost.
According to an aspect of the present disclosure, there is provided a driving chip including:
a first test pin;
a driving unit configured to drive the display panel to display;
the data selection unit is configured to receive a plurality of test signals and control signals input from the first test pin, select a target test signal from the plurality of test signals according to the control signal, and drive the display panel to perform a test according to the selected target test signal.
In an exemplary embodiment of the present disclosure, an input terminal of the data selection unit is connected to one of the first test pins.
In an exemplary embodiment of the present disclosure, the data selecting unit includes:
a first test signal input terminal, a second test signal input terminal, a first strobe input terminal, a second strobe input terminal and an additional control input terminal;
a first not gate having an input connected to the additional control input;
the first input end of the AND gate is connected with the output end of the first NOT gate, and the output end of the AND gate is the input end of the data selection unit;
the input end of the second NOT gate is connected with the first gating input end;
the input end of the first low-level effective switch is connected with the output end of the second NOT gate;
a third not gate, an input end of which is connected with the second gating input end;
the input end of the second low-level effective switch is connected with the output end of the third NOT gate;
the input end of the fourth NOT gate is connected with the first test signal input end;
the input end of the fifth NOT gate is connected with the second test signal input end;
the first transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
the second transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fifth NOT gate, the first control end is connected with the output end of the first low-level effective switch, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate;
a third low level active switch having an input connected to the output of the first transmission gate and the output of the second transmission gate;
and the fifth transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the third low-level effective switch, the first control end is connected with the output end of the third NOT gate, the second control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, and the output end is connected with the second input end of the AND gate.
In an exemplary embodiment of the present disclosure, the data selecting unit further includes:
a third test signal input;
the input end of the sixth NOT gate is connected with the third test signal input end;
a third transmission gate, including an input terminal, a first control terminal, a second control terminal and an output terminal, wherein the input terminal is connected to the output terminal of the sixth not gate, the first control terminal is connected to the output terminal of the second not gate, and the second control terminal is an active low-level control terminal and is connected to the output terminal of the first active low-level switch;
the input end of the fourth low-level effective switch is connected with the output end of the third transmission gate;
and the sixth transmission gate comprises an input end, a first control end, a second control end and an output end, wherein the input end is connected with the output end of the fourth low-level effective switch, the first control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, the second control end is connected with the output end of the third NOT gate, and the output end is connected with the second input end of the AND gate.
In an exemplary embodiment of the present disclosure, the data selecting unit further includes:
a fourth test signal input;
the input end of the seventh NOT gate is connected with the fourth test signal input end;
a fourth transmission gate, including input, first control end, second control end and output, the input with the output of seventh not gate is connected, first control end is connected with the output of the effective switch of first low level, the second control end be the effective control end of low level and with the output of second not gate is connected, the output with the input of the effective switch of fourth low level is connected.
According to another aspect of the present disclosure, there is provided a display module, including:
a display panel;
in the above driving chip, the driving chip is connected to the display panel.
In an exemplary embodiment of the present disclosure, the display module further includes:
the circuit board is provided with at least one second test pin, the second test pins are electrically connected with the first test pins in a one-to-one correspondence mode, and signals are input to the first test pins through the second test pins.
In an exemplary embodiment of the present disclosure, the driving chip is disposed on the display panel; or,
the display module further comprises a chip on film, the chip on film is connected with the display panel, and the driving chip is arranged on the chip on film.
According to still another aspect of the present disclosure, a display device is provided, which includes the above display module.
According to still another aspect of the present disclosure, there is provided a test method of a display panel, the test method including:
providing a display panel and a driving chip; the driving chip comprises a first testing pin, a driving unit and a data selection unit, wherein the driving unit is configured to drive the display panel to display; the input end of the data selection unit is connected with the first test pin, and the output end of the data selection unit is connected with the driving unit of the driving chip;
the data selection unit selects a target test signal in the plurality of test signals according to the control signal, and the driving unit drives the display panel to test according to the selected target test signal.
The driving chip provided by the disclosure can manually switch the test signals by using the same test point in a user-defined mode, so that the signal test points which do not need to be measured simultaneously can be combined into the same test point, and the self-remaining test pins are reduced, thereby greatly reducing the design difficulty, improving the design efficiency, being beneficial to reducing the size of the driving chip and reducing the product cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic view of a display module according to an embodiment of the disclosure;
fig. 2 is a schematic logic circuit diagram of a data selection unit according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a data selecting unit according to an embodiment of the disclosure;
fig. 4 is a logic truth table of a data selection unit according to an embodiment of the disclosure;
fig. 5 is a flowchart of a method for testing a display panel according to an embodiment of the disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be understood that if the illustrated device is turned upside down, elements described as "upper" will be those that are "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a", "an", "the", "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
An embodiment of the present disclosure provides the driver chip, which includes: the device comprises a first test pin, a driving unit and a data selection unit; the driving unit is configured to drive the display panel to display; the input end of the data selection unit is connected with the first test pin, the output end of the data selection unit is connected with the driving unit of the driving chip, the data selection unit is configured to receive a plurality of test signals and control signals input from the first test pin and select a target test signal in the plurality of test signals according to the control signals, and the driving unit drives the display panel to perform testing according to the selected target test signal. The test pins can be reduced, the size of the driving chip is reduced, and the product cost is reduced.
This drive chip (IC) that openly provides can utilize same test point through self-defined mode, and the manual switching that carries out test signal just so can merge the signal measurement station that does not need simultaneous measurement into same, has reduced self-remaining test PIN (PIN) to can reduce substantially the design degree of difficulty, improve design efficiency, be favorable to drive chip size (IC size) to reduce moreover, reduce product cost.
In an embodiment of the present disclosure, the input terminal of the data selection unit is connected to a first test pin, i.e. the input of the test signal can be realized through a test pin, which greatly reduces the number of self-contained test pins. Of course, a plurality of first test pins can be arranged, the input end of the data selection unit is connected with the plurality of first test pins, signal test points which do not need to be measured simultaneously can be combined into one signal test point, and signals which do not need to be measured simultaneously are input into the data selection unit through one test pin to be selected and then tested.
In one embodiment of the present disclosure, two test signals are simultaneously input, and one test signal is selected to be tested; specifically, the data selection unit includes:
the device comprises a first test signal input end, a second test signal input end, a first gating input end, a second gating input end and an additional control input end;
a first not gate, the input end of which is connected with the additional control input end;
the first input end of the AND gate is connected with the output end of the first NOT gate, and the output end of the AND gate is the input end of the data selection unit;
the input end of the second NOT gate is connected with the first gating input end;
the input end of the first low-level effective switch is connected with the output end of the second NOT gate;
the input end of the third NOT gate is connected with the second gating input end;
the input end of the second low-level effective switch is connected with the output end of the third NOT gate;
the input end of the fourth NOT gate is connected with the first test signal input end;
the input end of the fifth NOT gate is connected with the second test signal input end;
the first transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
the second transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fifth NOT gate, the first control end is connected with the output end of the first low-level effective switch, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate;
the input end of the third low-level effective switch is connected with the output end of the first transmission gate and the output end of the second transmission gate;
and the fifth transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the third low-level effective switch, the first control end is connected with the output end of the third NOT gate, the second control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, and the output end is connected with the second input end of the AND gate.
In another embodiment of the disclosure, three test signals are simultaneously input, and one test signal is selected to be tested; the data selection unit includes:
a first test signal input terminal, a second test signal input terminal, a third test signal input terminal, a first gating input terminal, a second gating input terminal and an additional control input terminal;
a first not gate, the input terminal of which is connected with the additional control input terminal;
the first input end of the AND gate is connected with the output end of the first NOT gate, and the output end of the AND gate is the input end of the data selection unit;
the input end of the second NOT gate is connected with the first gating input end;
the input end of the first low-level effective switch is connected with the output end of the second NOT gate;
the input end of the third NOT gate is connected with the second gating input end;
the input end of the second low-level effective switch is connected with the output end of the third NOT gate;
the input end of the fourth NOT gate is connected with the first test signal input end;
the input end of the fifth NOT gate is connected with the second test signal input end;
the first transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
the second transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fifth NOT gate, the first control end is connected with the output end of the first low-level effective switch, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate;
the input end of the third low-level effective switch is connected with the output end of the first transmission gate and the output end of the second transmission gate;
the fifth transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the third low-level effective switch, the first control end is connected with the output end of the third NOT gate, the second control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, and the output end is connected with the second input end of the AND gate;
the input end of the sixth NOT gate is connected with the third test signal input end;
the third transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the sixth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
the input end of the fourth low-level effective switch is connected with the output end of the third transmission gate;
and the sixth transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth low-level effective switch, the first control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, the second control end is connected with the output end of the third NOT gate, and the output end is connected with the second input end of the AND gate.
In another embodiment of the present disclosure, as shown in fig. 2 to 4, four kinds of test signals are simultaneously input, and one of the test signals is selected for testing; the data selection unit includes:
first test signal input terminal D 00 A second test signal input terminal D 01 A third test signal input terminal D 10 A fourth test signal input terminal D 11 A first gate input terminal A 0 A second gate input terminal A 1 And an additional control input S';
a first not gate c1, the input of which is connected to the additional control input S';
the first input end of the AND gate d0 is connected with the output end of the first NOT gate c1, and the output end is the input end of the driving unit;
a second NOT gate c2 having an input terminal connected to the first gate input terminal A 0 Connecting;
the input end of the first low-level effective switch b1 is connected with the output end of the second NOT gate c 2;
a third NOT gate c3 with input terminal connected to the second gating input terminal A 1 Connecting;
the input end of the second low-level effective switch b2 is connected with the output end of the third NOT gate c 3;
a fourth NOT gate c4 having an input terminal connected to the first test signal input terminal D 00 Connecting;
the first transmission gate TG1 comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate c4, the first control end is connected with the output end of the second NOT gate c2, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch b 1;
a fifth not gate c5 having an input terminal connected to the second test signal input terminal D 01 Connecting;
the second transmission gate TG2 comprises an input end, a first control end, a second control end and an output end, wherein the input end is connected with the output end of the fifth NOT gate c5, the first control end is connected with the output end of the first low-level effective switch b1, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate c 2;
the input end of the third low-level effective switch b3 is connected with the output end of the first transmission gate TG1 and the output end of the second transmission gate TG 2;
a fifth transmission gate TG5, including an input end, a first control end, a second control end and an output end, where the input end is connected to the output end of the third low-level effective switch b3, the first control end is connected to the output end of the third not gate c3, the second control end is a low-level effective control end and is connected to the output end of the second low-level effective switch b2, and the output end is connected to the second input end of the and gate d 0;
a sixth not gate c6 having an input terminal connected to the third test signal input terminal D 10 Connecting;
a third transmission gate TG3, including an input terminal, a first control terminal, a second control terminal and an output terminal, wherein the input terminal is connected to the output terminal of the sixth not gate c6, the first control terminal is connected to the output terminal of the second not gate c2, and the second control terminal is an active low-level control terminal and is connected to the output terminal of the first active low-level switch b 1;
a seventh NOT gate c7 having an input terminal connected to the fourth test signal input terminal D 11 Connecting;
a fourth transmission gate TG4, including an input terminal, a first control terminal, a second control terminal and an output terminal, wherein the input terminal is connected to the output terminal of the seventh not gate c7, the first control terminal is connected to the output terminal of the first low level active switch b1, and the second control terminal is a low level active control terminal and is connected to the output terminal of the second not gate c 2;
an input end of the fourth low-level effective switch b4 is connected with an output end of the third transmission gate TG3 and an output end of the fourth transmission gate TG 4;
and the sixth transmission gate TG6 comprises an input end, a first control end, a second control end and an output end, wherein the input end is connected with the output end of the fourth low-level effective switch b4, the first control end is a low-level effective control end and is connected with the output end of the second low-level effective switch b2, the second control end is connected with the output end of the third NOT gate c3, and the output end is connected with the second input end of the AND gate d 0.
The selection of four test signals can be realized through one test pin, the whole realization process is a digital signal, the truth table of the data selection unit is shown in fig. 4, and the calculation formula of the test signal Y finally selected according to the truth table is as follows:
wherein,
which is represented as a high level 1, and,
which is represented as a low level of 0,
represented as high level 1.
In addition, the inventor finds that, in order to solve the problem that the available space of the FPC indicated in the background art is smaller and smaller, the FPC is designed by using a multi-layer board, but the overall thickness of the FPC is increased, and even then, the increase of the thickness is more and more limited, so how to save the routing space of the FPC as much as possible under the existing design scheme becomes a difficult problem to be solved in the industry. Generally, in order to verify the theoretical consistency with the actual, other signals than the Timing related signal do not need to be measured simultaneously.
To solve the above technical problem, an embodiment of the present disclosure provides a display module, as shown in fig. 1, the display module includes: the display panel 10 is connected to the driving chip (IC) 30, the driving chip 30 is connected to the display panel 10, and the driving chip (IC) 30 is provided with a data selection unit 310.
In an embodiment of the disclosure, as shown in fig. 1, the display module further includes: the circuit board (FPC) 20 is provided with at least one second test pin 50, the second test pins 50 are electrically connected with the first test pins 40 in a one-to-one correspondence mode, and signals are input to the first test pins 40 through the second test pins 40. The same test point is used for switching test signals manually in a self-defined mode, so that signal test points which do not need to be measured simultaneously can be combined into the same test point, self-reserved test PINs (PIN) on a circuit board are reduced, and the space of an FPC is saved to a great extent, and wiring is facilitated.
In one embodiment of the present disclosure, the driving chip (IC) is disposed on the display Panel (PLN), the display panel 10 includes a non-display area in which a display area surrounds the display area, the non-display area includes a bonding area, and the driving chip 30 may be disposed on the display panel through the bonding area.
In another embodiment of the present disclosure, the display module further includes a Chip On Film (COF) connected to the display Panel (PLN), and the driving chip (IC) is disposed on the COF. The circuit board can be connected with the chip on film.
In an embodiment of the present disclosure, as shown in fig. 1, the circuit board 20 is provided with a through hole for fingerprint identification, the circuit board 20 is connected with a connector, and is fastened to a main board of the display device, and the circuit board 20 and the display panel 10 can be attached to each other through a conductive adhesive.
The embodiment of the present disclosure further provides a display device, which includes the above display module. The details and advantages of the display device are discussed in the above related to the manufacturing method, and are not repeated herein.
An embodiment of the present disclosure also provides a test method of a display panel, as shown in fig. 5, the test method includes:
step S100, providing a display panel and a driving chip; the driving chip comprises a first testing pin, a driving unit and a data selection unit, wherein the driving unit is configured to drive the display panel to display; the input end of the data selection unit is connected with the first test pin, and the output end of the data selection unit is connected with the driving unit of the driving chip;
step S200, a plurality of test signals and control signals are input to the data selection unit through the first test pin, the data selection unit selects a target test signal in the plurality of test signals according to the control signals, and the driving unit drives the display panel to test according to the selected target test signal.
According to the test method of the display panel, the same test point can be used for switching the test signals manually in a user-defined mode, so that signal test points which do not need to be measured simultaneously can be combined into the same test point, self-retained test PINs (PIN) are reduced, the design difficulty can be greatly reduced, the design efficiency is improved, the reduction of the size of a drive chip (IC size) is facilitated, and the product cost is reduced.
In an embodiment of the present disclosure, a circuit board (FPC) may be further provided in step S100, the circuit board is provided with at least one second test pin, the second test pin is electrically connected to the first test pin in a one-to-one correspondence, and the second test pin inputs a signal to the first test pin. The switching of the test signals is manually carried out by using the same test point in a self-defined mode, so that the signal test points which do not need to be measured simultaneously can be combined into the same test point, the number of self-contained test PINs (PIN) on a circuit board is reduced, and the space of the FPC is saved to a great extent so as to facilitate wiring.
The display panel, the driving chip and the circuit board provided in the test method may be the display panel, the driving chip and the circuit board in the above embodiments, and for specific details, reference is made to the above discussion about the display panel, the driving chip and the circuit board, and details are not repeated here.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (9)
1. A driving chip for display driving, comprising:
a first test pin;
a driving unit configured to drive the display panel to display;
the data selection unit is configured to receive a plurality of test signals and control signals input from the first test pin, select a target test signal from the plurality of test signals according to the control signal, and drive the display panel to test according to the selected target test signal;
wherein the data selection unit includes:
a first test signal input terminal, a second test signal input terminal, a first strobe input terminal, a second strobe input terminal and an additional control input terminal;
a first not gate having an input connected to the additional control input;
the first input end of the AND gate is connected with the output end of the first NOT gate, and the output end of the AND gate is the input end of the data selection unit;
the input end of the second NOT gate is connected with the first gating input end;
the input end of the first low-level effective switch is connected with the output end of the second NOT gate;
a third not gate, an input end of which is connected with the second gating input end;
the input end of the second low-level effective switch is connected with the output end of the third NOT gate;
the input end of the fourth NOT gate is connected with the first test signal input end;
the input end of the fifth NOT gate is connected with the second test signal input end;
the first transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
the second transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fifth NOT gate, the first control end is connected with the output end of the first low-level effective switch, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate;
a third low level active switch having an input connected to the output of the first transmission gate and the output of the second transmission gate;
and the fifth transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the third low-level effective switch, the first control end is connected with the output end of the third NOT gate, the second control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, and the output end is connected with the second input end of the AND gate.
2. The driver chip of claim 1, wherein the input terminal of the data selection unit is connected to the first test pin.
3. The driver chip of claim 1, wherein the data selection unit further comprises:
a third test signal input;
the input end of the sixth NOT gate is connected with the third test signal input end;
the third transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the sixth not gate, the first control end is connected with the output end of the second not gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch;
a fourth low level active switch, an input end of which is connected with an output end of the third transmission gate;
and the sixth transmission gate comprises an input end, a first control end, a second control end and an output end, wherein the input end is connected with the output end of the fourth low-level effective switch, the first control end is a low-level effective control end and is connected with the output end of the second low-level effective switch, the second control end is connected with the output end of the third NOT gate, and the output end is connected with the second input end of the AND gate.
4. The driver chip of claim 3, wherein the data selection unit further comprises:
a fourth test signal input;
the input end of the seventh NOT gate is connected with the fourth test signal input end;
a fourth transmission gate, including input, first control end, second control end and output, the input with the output of seventh not gate is connected, first control end is connected with the output of the effective switch of first low level, the second control end be the effective control end of low level and with the output of second not gate is connected, the output with the input of the effective switch of fourth low level is connected.
5. A display module, comprising:
a display panel;
the driver chip of any of claims 1-4, connected to the display panel.
6. The display module assembly of claim 5, wherein the display module assembly further comprises:
the circuit board is provided with at least one second test pin, the second test pins are electrically connected with the first test pins in a one-to-one correspondence manner, and signals are input to the first test pins through the second test pins.
7. The display module of claim 5, wherein the driving chip is disposed on the display panel; or,
the display module further comprises a chip on film, the chip on film is connected with the display panel, and the driving chip is arranged on the chip on film.
8. A display device, characterized in that the display device comprises the display module according to any one of claims 5-7.
9. A method for testing a display panel, comprising:
providing a display panel and a driving chip; the driving chip comprises a first testing pin, a driving unit and a data selection unit, and the driving unit is configured to drive the display panel to display; the input end of the data selection unit is connected with the first test pin, and the output end of the data selection unit is connected with the driving unit of the driving chip; wherein the data selection unit includes: the device comprises a first test signal input end, a second test signal input end, a first gating input end, a second gating input end and an additional control input end; a first not gate having an input connected to the additional control input; the first input end of the AND gate is connected with the output end of the first NOT gate, and the output end of the AND gate is the input end of the data selection unit; the input end of the second NOT gate is connected with the first gating input end; the input end of the first low-level effective switch is connected with the output end of the second NOT gate; a third not gate, an input end of which is connected with the second gating input end; the input end of the second low-level effective switch is connected with the output end of the third NOT gate; the input end of the fourth NOT gate is connected with the first test signal input end; the input end of the fifth NOT gate is connected with the second test signal input end; the first transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fourth NOT gate, the first control end is connected with the output end of the second NOT gate, and the second control end is a low-level effective control end and is connected with the output end of the first low-level effective switch; the second transmission gate comprises an input end, a first control end, a second control end and an output end, the input end is connected with the output end of the fifth NOT gate, the first control end is connected with the output end of the first low-level effective switch, and the second control end is a low-level effective control end and is connected with the output end of the second NOT gate; a third low level active switch having an input connected to the output of the first transmission gate and the output of the second transmission gate; a fifth transmission gate, including an input terminal, a first control terminal, a second control terminal and an output terminal, where the input terminal is connected to the output terminal of the third low-level active switch, the first control terminal is connected to the output terminal of the third not gate, the second control terminal is a low-level active control terminal and is connected to the output terminal of the second low-level active switch, and the output terminal is connected to the second input terminal of the and gate;
the data selection unit selects a target test signal in the plurality of test signals according to the control signal, and the driving unit drives the display panel to test according to the selected target test signal.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140120580A (en) * | 2013-04-03 | 2014-10-14 | 삼성디스플레이 주식회사 | Organic light emitting display device and method of inspecting the same |
| CN106057112A (en) * | 2016-08-09 | 2016-10-26 | 武汉华星光电技术有限公司 | Box forming test circuit and liquid crystal display substrate |
| CN112331118A (en) * | 2020-11-30 | 2021-02-05 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN112349230A (en) * | 2020-12-04 | 2021-02-09 | 厦门天马微电子有限公司 | Display panel, detection method thereof and display device |
| CN213635305U (en) * | 2020-11-05 | 2021-07-06 | 惠科股份有限公司 | Test circuit, display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107038985B (en) * | 2017-06-02 | 2020-04-03 | 京东方科技集团股份有限公司 | Driving module for display panel, display panel and display device |
-
2021
- 2021-08-20 CN CN202110960429.5A patent/CN113674688B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140120580A (en) * | 2013-04-03 | 2014-10-14 | 삼성디스플레이 주식회사 | Organic light emitting display device and method of inspecting the same |
| CN106057112A (en) * | 2016-08-09 | 2016-10-26 | 武汉华星光电技术有限公司 | Box forming test circuit and liquid crystal display substrate |
| CN213635305U (en) * | 2020-11-05 | 2021-07-06 | 惠科股份有限公司 | Test circuit, display panel and display device |
| CN112331118A (en) * | 2020-11-30 | 2021-02-05 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN112349230A (en) * | 2020-12-04 | 2021-02-09 | 厦门天马微电子有限公司 | Display panel, detection method thereof and display device |
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