CN113673192A - Parallel accelerated extraction method for SPEF parasitic parameters of ultra-large scale integrated circuit - Google Patents
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Abstract
A method for parallel accelerated extraction of SPEF parasitic parameters of a very large scale integrated circuit comprises the following steps: starting multithreading, and dividing the file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to the branch structure of the SPEF file; starting multithreading, reading each data block in parallel, establishing and analyzing parasitic parameter data required by a timing diagram; and starting multithreading, and merging the coupling capacitors of each data block in parallel. The parallel acceleration extraction method of the SPEF parasitic parameters of the ultra-large scale integrated circuit achieves very objective high parallelism and good acceleration ratio through fine-grained task division, and improves the response speed of static timing analysis in the optimization process of circuit design.
Description
Technical Field
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to an acceleration method for analyzing SPEF files of a super large scale integrated circuit in parallel in static time sequence analysis.
Background
In different stages of integrated circuit design, timing sequence inspection is required to be performed on the design to ensure that the designed circuit can meet the predetermined timing sequence requirement. Static Timing Analysis (STA) does not depend on excitation, and can quickly and accurately measure the circuit timing to measure the performance of the circuit.
Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the whole circuit, constructs a timing diagram, calculates the delay propagation of signals on the paths, and finds out the error violating the timing constraint.
Static timing analysis requires numerous library files, including Liberty, SPEF, SDC, etc., in calculating the propagation delay of a signal. SPEF (standard parasitic exchange format) is a standard medium file for transferring parasitic parameters of interconnection lines between EDA tools in an integrated circuit design flow. The SPEF can describe various interconnection line parasitic models, and further establishes functions of signal skew, delay calculation language, name mapping and the like. An integrated circuit designer extracts SPEF parameters of a current circuit design network through a specific parasitic parameter extraction tool, and uses the parameters to participate in calculation and evaluation of power consumption and static time sequence analysis, and the usability and the optimization direction of the current design are comprehensively evaluated; in fact, a chip designer needs to adjust the circuit design for many times or optimize for many times to meet the relevant requirements of time sequence and power consumption, and in the process, the parasitic parameters of the interconnection line need to be extracted for many times and static time sequence analysis needs to be performed for many times, so that the time consumption is huge.
In the last decades, hardware computing units have been developed rapidly, available computing resources have become more and more abundant, and most of the technologies still remain in single-process (thread) reading, which is far less than the available computing resources, resulting in a large amount of computing resources being left unused and the efficiency of the whole static timing analysis being low.
At present, available computing resources of hardware are more and more abundant, most of technologies can still stay in single-process (thread) reading and are far smaller than the available computing resources, and therefore the vacancy of a large number of computing resources and the efficiency of the whole static time sequence analysis are caused. Little research has been done on the direction to achieve computational optimization by multiprocessing (threads).
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a parallel acceleration extraction method for SPEF parasitic parameters of a very large scale integrated circuit, which achieves very objective high parallelism and good acceleration ratio through fine-grained task division, and improves the response speed of static time sequence analysis in the circuit design optimization process.
In order to achieve the above object, the present invention provides a method for parallel accelerated extraction of SPEF parasitic parameters of a very large scale integrated circuit, comprising the steps of:
starting multithreading, and dividing the file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to the branch structure of the SPEF file;
starting multithreading, reading each data block in parallel, establishing and analyzing parasitic parameter data required by a timing diagram;
and starting multithreading, and merging the coupling capacitors of each data block in parallel.
Further, the division of the data block should satisfy the following condition:
the number of the data blocks is integral multiple of the process number set by a user or the core number of the CPU;
the nets in each data block are kept complete and close in number;
the number of interconnect lines between data blocks is minimal.
Further, the step of enabling multithreading, dividing the file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to the branch structure of the SPEF file, further includes,
according to the specific format of the SPEF file, roughly cutting the file to ensure the integrity of statement information and the integrity of main elements;
and starting a multi-process to finely process the information of the pre-partition, and extracting the position information of the header and the position information of the NAME _ MAP.
Further, the method also comprises the following steps of,
carrying out data block coarse positioning on a source file according to the size of a data block, and ensuring that each data block is a complete meaning line statement;
and carrying out fine positioning on the data block obtained by the coarse positioning according to the block information of the SPEF file to obtain a hierarchical data block, wherein the hierarchical principle comprises a basic attribute which depends on the whole situation and a basic attribute which can be highly parallel.
Further, the step of starting multithreading, reading each data block in parallel to establish and analyze the parasitic parameter data required by the timing diagram further comprises,
reading the SPEF file and the basic attribute definition part, and establishing globally readable basic attribute data storage;
reading NAME _ MAP NAME mapping definition part, and establishing mapping corresponding to global read-only integer and network NAME;
and respectively reading the partitioning marks of the wire net according to the data blocks in the sub-process, and finishing the reading and the storage of the parasitic parameter information of the interconnection wire.
Furthermore, the step of reading the partitioning marks of the net respectively according to the data blocks and the sub-processes to complete the reading and storing of the parasitic parameter information of the interconnection line further comprises,
when the net information is analyzed, each net stores a node name and a capacitance size list mapped by the coupling capacitance of the net;
and after the establishment of all the network information and the database of the nodes is finished, searching and updating the mapping of the pre-stored coupling capacitor.
Furthermore, the step of starting multithreading and merging the coupling capacitors of each data block in parallel also comprises the step of independently grouping the established net information to be used as a fine-grained task to carry out multi-process parallelization and complete the serialized storage of the coupling capacitors.
Further, the method also comprises the following steps of,
extracting and merging the same node names and the mapping requirements of the serialized data in different net information according to the net information which is serialized;
and taking the global net information which is stored in a serialized mode as a read-only input parameter, simultaneously recording a net list of the coupling capacitors which need to be updated, establishing parallel fine-grained tasks for combining the coupling capacitors, and performing the mapping of searching node names and a serialized memory by each task and updating the mapping into the net corresponding to the coupling capacitor.
To achieve the above object, the present invention further provides an electronic device comprising a memory and a processor, the memory storing a computer program running on the processor, the processor executing the computer program to perform the steps of the method for parallel accelerated extraction of SPEF parasitic parameters of a very large scale integrated circuit, as described above.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon a computer program which when run performs the steps of the method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integration (vlsi) as described above.
The method for parallel accelerated extraction of SPEF parasitic parameters of the ultra-large scale integrated circuit has the following beneficial effects:
1) by utilizing hierarchical parallelization, rich computing resources are fully utilized, and parallel high-speed analysis of the SPEF file is achieved;
2) by fine-grained task division, the method achieves very objective high parallelism and good speed-up ratio, and improves the response speed of static time sequence analysis in the optimization process of circuit design.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit according to the present invention;
FIG. 2 is a schematic diagram of a portion of the position distribution of a circuit SPEF file after fine positioning in accordance with the present invention;
FIG. 3 is a schematic diagram of the position of a mark after coarse cutting of a circuit SPEF file, and re-fine positioning of the first stage after cutting, in accordance with the present invention;
FIG. 4 is a block diagram of a circuit SPEF file according to the present invention after completion of hierarchical group marking.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1
FIG. 1 is a flow chart of a method for parallel accelerated extraction of a SPEF parasitic parameter of a VLSI according to the present invention, and the method for parallel accelerated extraction of a SPEF parasitic parameter of a VLSI according to the present invention will be described in detail with reference to FIG. 1.
First, in step 101, a SPEF file is read, multithreading (process) is started, and the file is divided into a basic attribute definition part (Header) and a parameter file body part including N data blocks (Partition) in parallel according to a branch structure of the SPEF file.
The SPEF file is read by using a normal single process (or thread) in the past and takes a long time, and a plurality of data blocks in the SPEF file can be relatively independent after being specifically processed, so that hierarchical parallel computing can be performed, a considerable real-time running speed-up ratio can be obtained, and computing load balance is achieved.
In the embodiment of the present invention, in order to ensure the computation load balance among partitions, the following conditions need to be satisfied for Partition of partitions: 1) the number of the partitions is an integral multiple of the process number set by the user as much as possible, and when the number is not set by the user, the number is defaulted to be the core number of the CPU; 2) the quantity of nets in each Partition is as close as possible; 3) interconnection lines among partitions are as few as possible; 4) the Net in each Partition remains intact. N partitions divided under the four conditions described above are optimal. In order to obtain information in the above four conditions, the netlist of the whole circuit needs to be read in advance. It should be noted that the partitions finally divided according to the algorithm are data blocks containing one or more nets in general, and the size and length of the partitions are not the same in general.
In the embodiment of the invention, the data block division is to extract the grading position information of different data blocks according to the optimized block size specified by a user or preset, and the finished result stores the position information about the blocking information. Specifically, a process (or thread) performs a first rough cut on a file according to a specific format of the SPEF file, so as to ensure the integrity of statement information and the integrity of main elements (such as Net, etc.), and then starts multiple processes (or threads) to perform fine processing on pre-chunked information, which mainly includes extracting location information of Header, extracting location information of NAME _ MAP, and the like, and includes the following steps:
1) according to the block size appointed by a user or defaulted by the user, the block size is defined by the user according to circuit characteristics, the size of an SPEF file and the like, and the program combines user input to perform more detailed and accurate grading and block marking; the latter is that the program calculates the size of the hierarchical block needed by the reasonable optimal resource allocation according to the calculation resource and the storage resource of the current machine and by combining the size, the distribution characteristic and the like of the current SPEF file. Therefore, the block blocks of the source file are roughly positioned for the first time, the source file is cut in sequence based on the size of the defined blocks, if the position of the cut point is in the middle section of statement semantics, the part with complete semantics is continuously searched backwards and is used as a new cut point, and the fact that each block is a complete meaning line statement is mainly guaranteed.
2) According to block information (including basic attribute definition parts of files and designs, power line and ground line definitions, NAME _ MAP NAME mapping definitions, PORTS circuit port definitions, net definitions and the like) of the SPEF files, the block obtained by the first coarse positioning is subjected to one-time fine positioning to obtain a hierarchical block, and the hierarchical principle mainly includes basic attributes (including basic attributes of file designs and the like) of global dependence and basic attributes (including net definitions and the like) which can be highly parallel.
In detail, as shown in fig. 2, firstly, a multi-process (thread) search is performed on an ". times.end" keyword according to a coarsely positioned block marker, and a position from a file head address to a position where the first ". times.end" appears is used as an END position of a global dependency module, and then, a more detailed search and serialized storage are performed on the global dependency module; and secondly, for the rest of the SPEF file, sequentially starting multiple processes (threads) according to the searched END position, and serializing the net.
As shown in fig. 3, in detail, in this example, the original SPEF is marked by coarse-and-fine-grained hierarchical block division, and is divided into a Header portion, a NAME _ MAP portion, and a PORTS portion, which are independent first-level; the serialized portion of the D _ NET serves as a second level, and based on the aforementioned reasonable partition size, multi-process (thread) partition marking is completed on the premise of not destroying the integrity of the NET, and a finally formed file hierarchical partition positioning position structure diagram is shown in fig. 4.
At step 102, multiple threads (processes) are initiated and parasitic parameter data required for each Partition to build and analyze the timing graph is read in parallel.
In the embodiment of the invention, the parasitic parameter data comprises capacitance and resistance of Net, Input port and Output pin related to Net, capacitance and resistance of nodes, coupling capacitance between different nodes and the like.
In the embodiment of the invention, the parallel of multiple processes (threads) is carried out according to the obtained hierarchical block marks, each process (or thread) does not need to read complete design data, and is responsible for a Partition according to a cutting point obtained in precise positioning, and only reads a part of data required by the current Partition calculation, and the method comprises the following steps:
1) the SPEF file and the basic property definition part (Header) of the design are read. A globally readable basic attribute data store is created, consisting essentially of DIVIDER, DELIMITER, BUS _ DELIMITER, and the like.
2) And reading the NAME _ MAP NAME mapping definition part (if any), and establishing a mapping of the globally read-only integer and the Net NAME.
3) And respectively reading the blocking marks of the wire net by processes (threads) according to block blocks to finish reading and storing the parasitic parameter information of the interconnection wires. The method mainly comprises the net information in the formats of logic netlists such as D _ NET (distributed nets) and R _ NET (reduced nets), and physical nets such as D _ PNET (distributed physical nets) and R _ PNET (reduced physical nets), wherein the net information comprises the names and the attributes of connected ports, net distributed capacitance, distributed resistance, distributed capacitance and the like.
Preferably, 3) according to block, the partitioning process (thread) reads the partitioning mark of the net, and completes the steps of reading and storing the interconnection line parasitic parameter information, which can be specifically executed as:
first, when net information is analyzed, each net is only responsible for storing node names and capacitance size lists to which the coupling capacitances of the net are mapped.
And secondly, after all the net information is established and the database of the node is established, searching and updating the mapping of the pre-stored coupling capacitor.
In the embodiment of the invention, when the net information is read and analyzed, the coupling capacitance among nets is involved, and the part involves multi-process (thread) data interaction, so that the design principle of the multi-process (thread) is violated. The mapping of the coupling capacitor is divided into two steps to be executed, the original highly-coupled coupling capacitor storage is decoupled smoothly, the acceleration of multiple processes (threads) is completed, and the redundant load of a program is not increased.
In step 103, a plurality of processes (or threads) are started and coupling capacitance is combined for each Partition in parallel.
In the embodiment of the invention, the established net information is independently grouped and is used as a fine-grained task to carry out parallelization of multiple processes (threads), and the serialized storage of the coupling capacitor is completed. Specifically, the established net information is independently grouped, and is used as a fine-grained task to parallelize multiple processes (threads), so as to complete the step of serialized storage of the coupling capacitor, which can be specifically implemented as:
1) according to the net information that has been serialized in step 102, the same node names and the mapping requirements of the serialized data in different net information are extracted and merged, so that the number of the whole tasks is the maximum of the total amount of the coupling capacitance in the net information, and the calculated data is overall controllable and does not change with the size change of the block.
2) And taking the global net information which is stored in a serialized mode as a read-only input parameter, simultaneously recording a net list of the coupling capacitors which need to be updated, establishing parallel fine-grained tasks for combining the coupling capacitors, wherein each task is only responsible for searching the mapping between the node name and the serialized memory and updating the mapping into the net corresponding to the coupling capacitor.
Therefore, all the net information is stored in a serialized mode, and a complete database is established and can be used for static time sequence analysis and query.
The invention provides a parallel accelerated extraction method of SPEF parasitic parameters of a super-large-scale integrated circuit, which is characterized in that a complex and huge circuit parasitic parameter file is partitioned into multiple stages according to the characteristics of the file to realize high concurrency processing of hierarchical parallel, and after the processing of a globally dependent module is finished and synchronization is completed, multi-process (thread) parallel is carried out on a second-stage local independent module; and combining the coupling capacitances between different nets which may exist on the basis of mutually independent serialized storage of each preliminarily completed Net. And each Net is used as the minimum granularity in the merging process, and all coupling capacitance nodes related to the Net are recorded on the Net, so that high parallelism is realized. And finally, establishing and analyzing a parasitic parameter database.
In an embodiment of the present invention, there is further provided an electronic device comprising a memory and a processor, the memory having stored thereon a computer program running on the processor, when executing the computer program, performing the steps of the method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit, as described above.
In an embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which when run performs the steps of the method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for parallel accelerated extraction of SPEF parasitic parameters of a very large scale integrated circuit is characterized by comprising the following steps:
starting multithreading, and dividing the file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to the branch structure of the SPEF file;
starting multithreading, reading each data block in parallel, establishing and analyzing parasitic parameter data required by a timing diagram;
and starting multithreading, and merging the coupling capacitors of each data block in parallel.
2. A method of parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit according to claim 1, characterized in that said division of the data blocks shall satisfy the following condition:
the number of the data blocks is integral multiple of the process number set by a user or the core number of the CPU;
the nets in each data block are kept complete and close in number;
the number of interconnect lines between data blocks is minimal.
3. The method of parallel accelerated extraction of a SPEF parasitic parameter in a very large scale integrated circuit according to claim 1, wherein said step of enabling multithreading to divide the SPEF file into a plurality of data blocks of a basic attribute definition part and a parameter file body part in parallel according to a branching structure of the SPEF file further comprises,
according to the specific format of the SPEF file, roughly cutting the file to ensure the integrity of statement information and the integrity of main elements;
and starting a multi-process to finely process the information of the pre-partition, and extracting the position information of the header and the position information of the NAME _ MAP.
4. A method of parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit according to claim 3, further comprising,
carrying out data block coarse positioning on a source file according to the size of a data block, and ensuring that each data block is a complete meaning line statement;
and carrying out fine positioning on the data block obtained by the coarse positioning according to the block information of the SPEF file to obtain a hierarchical data block, wherein the hierarchical principle comprises a basic attribute which depends on the whole situation and a basic attribute which can be highly parallel.
5. The method of parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit of claim 1, wherein said step of enabling multithreading, reading in parallel each data block, creating and analyzing the parasitic parameter data required by the timing graph, further comprises,
reading the SPEF file and the basic attribute definition part, and establishing globally readable basic attribute data storage;
reading NAME _ MAP NAME mapping definition part, and establishing mapping corresponding to global read-only integer and network NAME;
and respectively reading the partitioning marks of the wire net according to the data blocks in the sub-process, and finishing the reading and the storage of the parasitic parameter information of the interconnection wire.
6. The method of claim 5, wherein the step of reading and storing the interconnection parasitic parameter information is accomplished by reading the net partitioning marks separately in each data block and branch process, and further comprises,
when the net information is analyzed, each net stores a node name and a capacitance size list mapped by the coupling capacitance of the net;
and after the establishment of all the network information and the database of the nodes is finished, searching and updating the mapping of the pre-stored coupling capacitor.
7. The method of claim 1, wherein the step of initiating multithreading to concurrently combine coupling capacitors for each data block further comprises independently grouping the established net information and parallelizing the multiple processes as a fine-grained task to complete sequential storage of the coupling capacitors.
8. The method of parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit of claim 7, further comprising,
extracting and merging the same node names and the mapping requirements of the serialized data in different net information according to the net information which is serialized;
and taking the global net information which is stored in a serialized mode as a read-only input parameter, simultaneously recording a net list of the coupling capacitors which need to be updated, establishing parallel fine-grained tasks for combining the coupling capacitors, and performing the mapping of searching node names and a serialized memory by each task and updating the mapping into the net corresponding to the coupling capacitor.
9. An electronic device comprising a memory and a processor, said memory having stored thereon a computer program for execution on said processor, said processor executing the steps of the method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit of any one of claims 1 to 8 when said computer program is executed.
10. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program is operative to perform the steps of the method for parallel accelerated extraction of a SPEF parasitic parameter of a very large scale integrated circuit according to any one of claims 1 to 8.
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| CN117077598A (en) * | 2023-10-13 | 2023-11-17 | 青岛展诚科技有限公司 | 3D parasitic parameter optimization method based on Mini-batch gradient descent method |
| CN117077598B (en) * | 2023-10-13 | 2024-01-26 | 青岛展诚科技有限公司 | 3D parasitic parameter optimization method based on Mini-batch gradient descent method |
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