CN117077596A - Timing analysis method, device, equipment and medium of integrated circuit chip - Google Patents
Timing analysis method, device, equipment and medium of integrated circuit chip Download PDFInfo
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Abstract
The application provides a time sequence analysis method, a time sequence analysis device, time sequence analysis equipment and a time sequence analysis medium for an integrated circuit chip. The method comprises the following steps: acquiring top layer data of an integrated circuit chip and circuit module data of each of a plurality of circuit modules in the integrated circuit chip; generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip; and carrying out time sequence analysis on each circuit module according to the environment model of each circuit module and the circuit module data, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top layer data, the environment model of each circuit module and the circuit module data to obtain a time sequence analysis result. The method can solve the problem of time sequence analysis errors caused by coupling capacitance in the time sequence analysis method of the integrated circuit chip in the related technology, and realize layering time sequence analysis of the integrated circuit chip so as to improve the efficiency and accuracy of the time sequence analysis.
Description
Technical Field
The present application relates to integrated circuit chip technologies, and in particular, to a method, an apparatus, a device, and a medium for analyzing timing sequences of an integrated circuit chip.
Background
In the physical design of large-scale integrated circuits, in order to improve the design efficiency, a hierarchical design mode is mostly adopted, the design is divided into a plurality of modules, each module is flattened and designed, an independent layout and wiring process is completed, each circuit module is respectively subjected to data modeling and provided for a top layer to carry out assembly design, and finally, full-chip time sequence analysis is carried out, or physical design rule inspection and the like can also be carried out.
In hierarchical design, it is necessary to divide the physical space occupied by each of the circuit module and the top layer, in which the module generally occupies the low-level winding resources for interconnection between devices, and the top layer occupies the high-level winding resources for interconnection of special signals such as high-speed clock lines and power supply networks. Adjacent metal wires exist at the boundary between the modules and the boundary of the top layer, and coupling capacitance exists between the metal wires, but when each module independently performs data modeling, due to the lack of data of other modules and the top layer, the coupling capacitance cannot be modeled, and crosstalk effect caused by the coupling capacitance cannot be ignored, so that errors of time sequence and noise analysis are caused.
The prior art scheme has two directions: firstly, data modeling is performed in a flattened mode, namely, after complete data of a module are assembled on a top layer, parasitic parameters of a full chip are extracted, the method can accurately perform data modeling and analysis, but the method is only suitable for medium-scale chips, and for large-scale chips, the expenditure of time and hardware resources is huge, even the processing limit of an Electronic Design Automation (EDA) tool is exceeded, and design dependence between a decoupling circuit module and the top layer is not facilitated.
Another solution is to reduce signal coupling at the boundary, e.g., increase shielding lines, increase the distance between the lines to reduce coupling capacitance; however, as the process size of the integrated circuit decreases, the model of the parasitic parameter becomes more and more complex, and it is difficult to radically stop the coupling capacitance. In addition, the shielded wire occupies a lot of winding resources, causing congestion of other interconnecting wires.
Disclosure of Invention
The application provides a time sequence analysis method, a device, equipment and a medium of an integrated circuit chip, which are used for solving the problem of time sequence analysis errors caused by coupling capacitance in the time sequence analysis method of the integrated circuit chip in the related technology, and realizing layering time sequence analysis of the integrated circuit chip so as to improve the efficiency and accuracy of the time sequence analysis.
In one aspect, the present application provides a method for timing analysis of an integrated circuit chip, the method comprising:
acquiring top layer data of an integrated circuit chip and circuit module data of each of a plurality of circuit modules in the integrated circuit chip;
generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip;
And carrying out time sequence analysis on each circuit module according to the environment model of each circuit module and circuit module data, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top-layer data, the environment model of each circuit module and the circuit module data to obtain a time sequence analysis result.
In an alternative embodiment, generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip includes:
extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
and generating an environment model corresponding to each circuit module according to the top-layer interconnection lines with coupling capacitors between each circuit module.
In an alternative embodiment, performing a timing analysis on each of the circuit modules according to the environmental model and the circuit module data of each of the circuit modules includes:
extracting parasitic parameters from the environment model and the circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
And according to the environment model corresponding to each circuit module, the module parasitic parameter file and the environment parasitic parameter file perform time sequence analysis on each circuit module to obtain a time sequence analysis result corresponding to each circuit module.
In an alternative embodiment, the full-chip timing analysis of the integrated circuit chip according to the top-level data, the environmental model of each circuit module, and the circuit module data includes:
extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file;
assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file;
and carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
In an optional implementation manner, extracting parasitic parameters of the environmental model and the circuit module data of each circuit module to obtain an environmental parasitic parameter file and a module parasitic parameter file corresponding to each circuit module, where the parasitic parameter file includes:
According to the environment model of each circuit module and the circuit module data, carrying out parasitic parameter extraction in a combined mode to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
wherein the module parasitic parameter file comprises: a parasitic parameter inside the circuit module, the environmental parasitic parameter file comprising: coupling capacitance between the interconnect lines within the environmental model and the interconnect lines within the circuit module.
In another aspect, the present application provides a timing analysis apparatus for an integrated circuit chip, the apparatus comprising:
the device comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring top-layer data of an integrated circuit chip and circuit module data of each of a plurality of circuit modules in the integrated circuit chip;
the generating module is used for generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip;
and the time sequence analysis module is used for carrying out time sequence analysis on each circuit module according to the environment model and the circuit module data of each circuit module, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top layer data, the environment model and the circuit module data of each circuit module to obtain a time sequence analysis result.
In an alternative embodiment, the generating module includes:
the extracting unit is used for extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
and the generating unit is used for generating an environment model corresponding to each circuit module according to the top-layer interconnection line with the coupling capacitance between each circuit module.
In an alternative embodiment, the timing analysis module includes:
the first extraction unit is used for extracting parasitic parameters of the environment model and the circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
and the first time sequence analysis unit is used for performing time sequence analysis on each circuit module according to the environment model corresponding to each circuit module, the module parasitic parameter file and the environment parasitic parameter file to obtain a time sequence analysis result corresponding to each circuit module.
In an alternative embodiment, the timing analysis module further includes:
The second extraction unit is used for extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file;
the assembly unit is used for assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file;
and the second time sequence analysis unit is used for carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
In another aspect, the present application provides an electronic device, including: a processor and a memory connected with the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method as described in any one of the above.
In another aspect, the application provides a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, are adapted to carry out a method as any one of the above.
In another aspect, the application provides a computer program product comprising a computer program which, when executed by a processor, implements any of the methods described above.
The application provides a time sequence analysis method, a device, equipment and a medium of an integrated circuit chip, wherein hierarchical design data of the integrated circuit chip are obtained, the hierarchical design data comprise top layer data, and circuit module data of a plurality of circuit modules respectively; generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip; and carrying out time sequence analysis on each circuit module according to the environment model of each circuit module and the circuit module data, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top layer data, the environment model of each circuit module and the circuit module data to obtain a time sequence analysis result.
The time sequence analysis scheme of the integrated circuit chip can solve the problem of time sequence analysis errors caused by coupling capacitance in the time sequence analysis method of the integrated circuit chip in the related technology, and realize hierarchical time sequence analysis of the integrated circuit chip so as to improve the efficiency and accuracy of the time sequence analysis.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart of a timing analysis method of an integrated circuit chip according to an embodiment of the present application;
FIG. 2 is a flow chart of an alternative timing analysis method of an integrated circuit chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative coupling capacitor provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative integrated circuit chip design according to an embodiment of the present application;
FIG. 5 is an optional parasitic parameter file assembly diagram of various layers according to an embodiment of the present application;
FIG. 6 is a block diagram illustrating a timing analysis device of an integrated circuit chip according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
First, the terms involved in the present application will be explained:
electronic design automation (Electronic Design Automation, EDA for short): the method is a design mode for completing the processes of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule inspection and the like) and the like of the ultra-large scale integrated circuit chip by utilizing computer aided design software.
Standard media file (Standard Parasitic Extraction Format, SPEF): refers to a standard media file for transferring interconnect parasitic parameters (resistance, capacitance, inductance) between EDA tools in an integrated circuit design flow.
Design exchange format (Design Exchange Format, DRF): refers to a file format for describing the physical design information of the circuit.
Currently, in integrated circuit designs, coupling capacitors exist between metal lines, and Signal Integrity (SI) problems may occur when signals are transmitted through the coupling capacitors. These problems are mainly related to the waveform shape and amplitude of the signal, which may lead to signal distortion, noise, crosstalk, etc. In static timing analysis, SI problems must be accurately modeled and analyzed, otherwise, the chip may not reach expected performance or even have functional errors when actually working.
In the physical design of large-scale integrated circuits, in order to improve the design efficiency, a hierarchical design mode is mostly adopted, the design is divided into a plurality of modules, each module is flattened and designed, an independent layout and wiring process is completed, each circuit module is respectively subjected to data modeling and provided for a top layer to carry out assembly design, and finally, full-chip time sequence analysis is carried out, or physical design rule inspection and the like can also be carried out.
In hierarchical design, it is necessary to divide the physical space occupied by each of the circuit module and the top layer, in which the module generally occupies the low-level winding resources for interconnection between devices, and the top layer occupies the high-level winding resources for interconnection of special signals such as high-speed clock lines and power supply networks. Adjacent metal wires exist at the boundary between the modules and the boundary of the top layer, and coupling capacitance exists between the metal wires, but when each module independently performs data modeling, due to the lack of data of other modules and the top layer, the coupling capacitance cannot be modeled, and crosstalk effect caused by the coupling capacitance cannot be ignored, so that errors of time sequence and noise analysis are caused.
The prior art scheme has two directions: firstly, data modeling is performed in a flattened mode, namely, after complete data of a module are assembled on a top layer, parasitic parameters of a full chip are extracted, the method can accurately perform data modeling and analysis, but the method is only suitable for medium-scale chips, and for large-scale chips, the expenditure of time and hardware resources is huge, even the processing limit of an Electronic Design Automation (EDA) tool is exceeded, and design dependence between a decoupling circuit module and the top layer is not facilitated.
Another solution is to reduce signal coupling at the boundary, for example, to increase shielding lines and increase the distance between the lines to reduce coupling capacitance, but as the process size of the integrated circuit decreases, the model of parasitic parameters becomes more and more complex, and it is difficult to radically stop the coupling capacitance. In addition, the shielded wire occupies a lot of winding resources, causing congestion of other interconnecting wires.
The application provides a time sequence analysis method of an integrated circuit chip, which aims to solve the technical problems in the prior art. The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
The application provides a time sequence analysis method of an integrated circuit chip, and fig. 1 is a flow chart of the time sequence analysis method of the integrated circuit chip provided by the embodiment of the application, as shown in fig. 1, the method comprises the following steps:
s101, hierarchical design data of an integrated circuit chip is obtained, wherein the hierarchical design data comprises top layer data and circuit module data of each of a plurality of circuit modules.
S102, generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip.
S103, carrying out time sequence analysis on each circuit module according to the environment model and the circuit module data of each circuit module, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top layer data, the environment model and the circuit module data of each circuit module to obtain a time sequence analysis result.
It should be noted that the environmental model is obtained by modeling the surrounding environment where the circuit module is located, and specifically includes the circuit and the interconnection lines around the circuit module.
Alternatively, a circuit module refers to a hierarchical design of an integrated circuit chip, where the entire integrated circuit chip is split into multiple smaller-scale circuits, which are referred to as circuit modules. The interconnection between the circuit modules is achieved by means of top-level interconnection lines.
In an alternative embodiment, for example, there is an integrated circuit chip whose hierarchical design data includes: the top layer data of the integrated circuit chip and the circuit module data of each of a plurality of circuit modules in the integrated circuit chip, wherein the top layer data specifically can comprise the overall structure, the function and the interface information of the integrated circuit chip and the layout and the attribute information of top layer interconnection lines. The circuit module data specifically includes internal structure, function and interface information of each circuit module, and layout and attribute information of interconnect lines within the circuit module. For example, take the following four circuit modules as an example:
Processor module CPU: is responsible for executing instructions and processing data.
Access module MEM: is responsible for storing and accessing data.
Read-write module IO: is responsible for communication and interaction with external devices.
Power supply module PWR: is responsible for managing and distributing power.
According to the method of the invention, hierarchical design data of an integrated circuit chip is firstly obtained; and then, generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip. For example, assume that the positional information of each circuit module in the integrated circuit chip is as follows:
CPU IO
MEM PWR
according to the embodiment of the application, the top-layer interconnection lines with coupling capacitances between each circuit module can be extracted from the top-layer data, and the environment model corresponding to each circuit module can be generated according to the interconnection lines. For example: environmental model of CPU: and the top-layer interconnection lines between other circuit modules such as IO, MEM, PWR adjacent to or close to the CPU and the coupling capacitance between the interconnection lines and the interconnection lines in the CPU are included. For another example, the environment model of IO: the device comprises top-layer interconnection lines between other circuit modules such as a CPU, a PWR and the like which are adjacent to or close to the IO, and coupling capacitances between the interconnection lines and interconnection lines in the IO. For another example, MEM's environmental model: including the top-level interconnect lines between other circuit modules, such as CPUs, PWRs, etc., adjacent or in close proximity to the MEM, and the coupling capacitances between these interconnect lines and interconnect lines within the MEM. Also for example, environmental model of PWR: including the top level interconnect lines between other circuit blocks adjacent or closely spaced IO, MEM, CPU to the PWR and the coupling capacitance between these interconnect lines and the interconnect lines within the PWR.
In one example, as shown in step 1 of fig. 2, hierarchical design data for an integrated circuit chip includes: top layer Top data of the integrated circuit chip, circuit module data BlockA data of the circuit module A and circuit module data BlockB data of the circuit module B, wherein an environment model of the circuit module A is a BlockA environment model, and an environment model of the circuit module B is a BlockB environment model.
Next, as shown in step 2 of fig. 2, according to the environmental model and the circuit module data of each circuit module, parasitic parameters of the internal interconnect line and the external interconnect line of the circuit module a and the circuit module B are extracted respectively, so as to obtain an environmental parasitic parameter file and a module parasitic parameter file corresponding to each circuit module, for example, a module parasitic parameter file BlockA SPEF and an environmental parasitic parameter file ContextA SPEF corresponding to the circuit module a; for example, a block spurious parameter file BlockB SPEF and an environment spurious parameter file ContextB SPEF corresponding to the circuit block B.
Then, as shown in step 3 of fig. 2, according to these parasitic parameter files, the internal signals and external signals of the circuit module a and the circuit module B are subjected to timing analysis, so as to obtain the timing analysis result corresponding to each circuit module, which includes information such as delay, rise time, fall time, setup time, hold time, clock offset, etc.
Then, as shown in step 4 of fig. 2, parasitic parameter extraction is performed on the Top-level interconnect line according to the Top-level Top data, so as to obtain a Top-level parasitic parameter file Top SPEF. And then, assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file, namely, assembling the full-chip SPEF, and obtaining the full-chip parasitic parameter file. Finally, as shown in step 5 of fig. 2, according to the parasitic parameter file of the whole chip, all signals of the integrated circuit chip are subjected to timing analysis, so as to obtain a timing analysis result corresponding to the integrated circuit chip, where the timing analysis result includes, but is not limited to: maximum operating frequency, minimum operating period, critical path, etc.
By the embodiment of the application, the layering time sequence analysis of the integrated circuit chip can be realized, so that the efficiency and the accuracy of the time sequence analysis are improved.
In the embodiment of the present application, the following multiple optional implementations may be further adopted, so that the foregoing embodiment is explained in detail, so as to facilitate understanding of the solution of the present application:
in an alternative embodiment, generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip includes:
S201, extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
s202, generating an environment model corresponding to each circuit module according to the top-layer interconnection lines with coupling capacitors between the circuit modules.
In the embodiment of the application, each circuit module is provided with a respective environment model, and a top-layer interconnection line of a coupling capacitor between the circuit module and a top-layer data is extracted according to the position of the circuit module in the integrated circuit chip. Specifically, a top-level interconnect line of a coupling capacitor exists between the extraction and module-level interconnect lines, and is stripped from the top-level data. The module-level interconnect lines refer to interconnect lines of the module internal circuits.
The coupling capacitor exists between two parallel connection lines on the same Metal Layer, as shown in fig. 3, wire1 and wire2 are located on the same Metal Layer (Metal Layer N), and the coupling capacitor is C1. And also exist between two parallel sections of connecting lines between different metal layers, as shown in fig. 3, wire1 and wire3 are respectively positioned in the nth layer and the n+2th layer metal layers, and the coupling capacitance is C2. Thus, in extracting the environmental model, consideration needs to be given to both the lateral (same metal layer) and longitudinal (between different metal layers) dimensions.
Taking a schematic design of an integrated circuit chip as shown in fig. 4 as an example, the chip design structure includes: top layer (Top) and 3 circuit modules (BlockA, blockB, blockC). For example, blockA uses M1 to Mn metal layers for the internal interconnect lines and mn+1 layers above BlockA to Mtop for the top level interconnect lines. First, considering the coupling capacitance on the same metal layer, the larger the distance is, the smaller the coupling capacitance value is, so that the top-layer interconnection lines distributed in a certain range outside the BlockA boundary have a significant influence on the interconnection lines inside the BlockA, and the influence of the interconnection lines far away from the area is negligible.
Therefore, a reasonable threshold is set, and the physical boundary of the blockA is expanded outwards for a distance to form an area shown by a dotted line frame. The top level interconnect lines of M1 to Mn in this dotted line area need to remain. Secondly, considering the coupling capacitance between different metal layers, the interconnection line from the Mn+1 layer above the Block A to the Mtop layer can influence the interconnection line in the block A, so that the interconnection line from the Mn+1 layer in the region to the top layer of the Mtop layer needs to be reserved. Specifically, as shown in fig. 4, the wires within the dashed area of BlockA need to remain as the top-level interconnect wires in the environment model. All interconnect lines outside the dashed area of BlockA have negligible impact on BlockA and therefore do not need to remain in the environment model. And adopting a similar method, and then continuously generating respective environment models for the blockB and the blockC respectively.
According to the embodiment of the application, the environment model is extracted, the coupling capacitance information among different layers of designs is reserved, and compared with the process of independently extracting parasitic parameters of each layer in the layering design, the method and the device can effectively avoid errors such as time sequence analysis, noise analysis and the like caused by loss of the coupling capacitance information.
In an alternative embodiment, performing a timing analysis on each of the circuit modules according to the environmental model and the circuit module data of each of the circuit modules includes:
s301, extracting parasitic parameters of an environment model and circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
s302, according to the environment model corresponding to each circuit module, the module parasitic parameter file and the environment parasitic parameter file, performing time sequence analysis on each circuit module to obtain a time sequence analysis result corresponding to each circuit module.
Optionally, the module parasitic parameter file includes parasitic parameters between the metal wires in the module; the environmental parasitic parameter file contains parasitic parameters between the module surrounding metal wiring and the module internal metal wiring.
Optionally, parasitic parameter tools such as StarRC, quantus and the like may be used to extract parasitic parameters from the environmental model and the circuit module data of each circuit module, so as to obtain an environmental parasitic parameter file and a module parasitic parameter file corresponding to each circuit module.
In the embodiment of the application, the parasitic parameter extraction is performed by combining the environment model and the module data, and the module parasitic parameter file (Block SPEF) and the environment parasitic parameter file (Context SPEF) are generated.
The standard parasitic parameter format file SPEF (Standard Parasitic Exchange Format) is a parasitic parameter format file that is generated by a place and route tool or a parasitic parameter extraction tool and then used in a timing analysis tool.
For example, the parasitic parameter information of an interconnection line may specifically describe the capacitance information by using the CAP part, the numbers 1 and 2 are the capacitance values of the pins connected by the connection line, the numbers 3 to 17 describe the capacitance to ground of each segment of metal line, and the numbers 18 to 20 describe the coupling capacitance between the two lines.
When independent parasitic parameter extraction is performed on the circuit module, due to the lack of data of the top layer, the extraction of coupling capacitance parameters is only limited between the interconnection lines inside the module, and the coupling capacitance between the interconnection lines inside the module and the interconnection lines of the top layer cannot be extracted.
Therefore, in the embodiment of the present application, after the environmental model generated in the above embodiment is read in, the parasitic parameter extraction is performed in combination with the circuit module data, so that the complete coupling capacitance information can be extracted, and two parasitic parameter files are generated altogether, where the module parasitic parameter file (Block SPEF) contains the parasitic parameters inside the module, and the environmental parasitic parameter file (Context SPEF) contains the coupling capacitance between the interconnection lines in the environmental model and the interconnection lines in the module.
In an alternative embodiment, the full-chip timing analysis of the integrated circuit chip according to the top-level data, the environmental model of each of the circuit modules, and the circuit module data includes:
s401, extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file.
S402, assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file.
S403, carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
In the hierarchical chip design flow, each circuit module can perform design, timing sequence convergence and other works in parallel, and finally, the assembly is completed on the top layer, and the timing sequence analysis and the signature flow of the whole chip are performed. And generating a top-layer parasitic parameter file by extracting parasitic parameters of the top-layer data. And assembling the top layer parasitic parameter file, the environment parasitic parameter file and the module parasitic parameter file to form a complete full-chip parasitic parameter file. And then, adopting the full-chip parasitic parameter file generated in the mode to perform full-chip time sequence analysis, for example, analyzing through a static time sequence analysis tool to obtain an accurate noise analysis result and delay change caused by crosstalk.
It should be noted that, in the conventional module level timing analysis, the required input files include: a module netlist file, a module parasitic parameter file; SDC constraint files; standard cell library, IP library.
The technical scheme is that the following input files are added on the basis: an environment parasitic parameter file (Context SPEF); an environment model (Context model). It should be noted that the newly added environmental model and environmental parasitic parameter file may be used to analyze the crosstalk effect of the top-level interconnect line on the module interconnect line.
Taking the schematic diagram of the parasitic parameter file assembly of each layer as shown in fig. 5 as an example, a part of connecting line (net_top_0) of a certain interconnection line at the TOP layer is positioned above the BlockA, and a coupling capacitor exists between the connecting line (for example net_a_0) which passes through the interior of the BlockA in parallel, and the information of the coupling capacitor is represented in Context SPEF; the coupling capacitance between net_a_0 and net_a_1 inside the BlockA is represented in the BlockA SPEF; and the coupling capacitance between net_top_0 and net_top_1 of the TOP layer is represented in the TOP parasitic parameter file TOP SPEF; for NET_A_0, the complete coupling capacitance information is obtained by integrating the BlockA SPEF and the Context SPEF; the complete coupling capacitance information of net_top_0 needs to integrate TOP SPEF and Context SPEF.
Compared with the flattening parasitic parameter extraction flow, the embodiment of the application has the advantages that: when parasitic parameters are extracted from each layer, the data of the layer and the environment model corresponding to the layer are only needed to be contained, the data size of the environment model is small, and the added operation cost is almost negligible.
In an optional implementation manner, extracting parasitic parameters of the environmental model and the circuit module data of each circuit module to obtain an environmental parasitic parameter file and a module parasitic parameter file corresponding to each circuit module, where the parasitic parameter file includes:
according to the environment model of each circuit module and the circuit module data, extracting parasitic parameters jointly to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
the parasitic parameter file of the module includes: parasitic parameters inside the circuit module, and the environmental parasitic parameter file includes: coupling capacitance between the interconnect lines in the environmental model and the interconnect lines in the circuit module.
And extracting parasitic parameters of the internal interconnection lines and the external interconnection lines of each circuit module by combining the environment model of each circuit module with the circuit module data to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module. And then, according to the parasitic parameter files, carrying out time sequence analysis on the internal signals and the external signals of each circuit module to obtain time sequence analysis results corresponding to each circuit module, wherein the time sequence analysis results comprise information such as delay, rising time, falling time, establishing time, holding time, clock offset and the like.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide corresponding operation entries for the user to select authorization or rejection.
According to one or more embodiments of the present application, there is provided a timing analysis device for an integrated circuit chip, and fig. 6 is a block diagram of a timing analysis device for an integrated circuit chip according to an embodiment of the present application, as shown in fig. 6, where the device includes:
an obtaining module 601, configured to obtain hierarchical design data of an integrated circuit chip, where the hierarchical design data includes top-level data, and circuit module data of each of a plurality of circuit modules;
a generating module 602, configured to generate an environmental model corresponding to each of the circuit modules according to the location information of each of the circuit modules in the integrated circuit chip;
The timing analysis module 603 is configured to perform timing analysis on each of the circuit modules according to the environmental model and the circuit module data of each of the circuit modules, and perform full-chip timing analysis on the integrated circuit chip according to the top-level data, the environmental model and the circuit module data of each of the circuit modules, so as to obtain a timing analysis result.
According to one or more embodiments of the present application, the generating module includes:
the extracting unit is used for extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
and the generating unit is used for generating an environment model corresponding to each circuit module according to the top-layer interconnection line with the coupling capacitance between each circuit module.
According to one or more embodiments of the present application, the above-mentioned timing analysis module includes:
the first extraction unit is used for extracting parasitic parameters of the environment model and the circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
And the first time sequence analysis unit is used for performing time sequence analysis on each circuit module according to the environment model, the module parasitic parameter file and the environment parasitic parameter file corresponding to each circuit module to obtain a time sequence analysis result corresponding to each circuit module.
According to one or more embodiments of the present application, the timing analysis module further includes:
the second extraction unit is used for extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file;
the assembly unit is used for assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file;
and the second time sequence analysis unit is used for carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
In an exemplary embodiment, an embodiment of the present application further provides an electronic device, including: a processor and a memory connected with the processor;
the memory stores computer-executable instructions;
the processor executes the computer-executable instructions stored in the memory to implement the method as described in any one of the above.
In an exemplary embodiment, an embodiment of the application further provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement a method as any one of the above.
In an exemplary embodiment, the application also provides a computer program product comprising a computer program which, when executed by a processor, implements any of the methods described above.
In order to achieve the above embodiment, the embodiment of the present application further provides an electronic device. Referring to fig. 7, there is shown a schematic structural diagram of an electronic device 700 suitable for use in implementing an embodiment of the present application, where the electronic device 700 may be a terminal device or a server. The terminal device may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a messaging device, a game console, a medical device, an exercise device, a personal digital assistant (Personal Digital Assistant, PDA for short), a tablet computer (Portable Android Device, PAD for short), a portable multimedia player (Portable Media Player, PMP for short), an in-vehicle terminal (e.g., in-vehicle navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 7 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments of the application.
As shown in fig. 7, the electronic apparatus 700 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 701 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 702 or a program loaded from a storage device 708 into a random access Memory (Random Access Memory, RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device 700 are also stored. The processing device 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.
In general, the following devices may be connected to the I/O interface 705: input devices 706 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 707 including, for example, a liquid crystal display (Liquid Crystal Display, LCD for short), a speaker, a vibrator, and the like; storage 708 including, for example, magnetic tape, hard disk, etc.; and a communication device 709. The communication means 709 may allow the electronic device 700 to communicate wirelessly or by wire with other devices to exchange data. While fig. 7 shows an electronic device 700 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via communication device 709, or installed from storage 708, or installed from ROM 702. When being executed by the processing means 701, performs the above-described functions defined in the method of the embodiment of the present application.
The computer readable medium of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above-described embodiments.
Computer program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network, LAN for short) or a wide area network (Wide Area Network, WAN for short), or it may be connected to an external computer (e.g., connected via the internet using an internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present application may be implemented in software or in hardware. The name of the unit does not in any way constitute a limitation of the unit itself, for example the first acquisition unit may also be described as "unit acquiring at least two internet protocol addresses".
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of the present application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A method of timing analysis of an integrated circuit chip, the method comprising:
acquiring top layer data of an integrated circuit chip and circuit module data of each of a plurality of circuit modules in the integrated circuit chip;
generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip;
And carrying out time sequence analysis on each circuit module according to the environment model of each circuit module and circuit module data, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top-layer data, the environment model of each circuit module and the circuit module data to obtain a time sequence analysis result.
2. The method of claim 1, wherein generating an environment model corresponding to each of the circuit modules based on the location information of each of the circuit modules in the integrated circuit chip comprises:
extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
and generating an environment model corresponding to each circuit module according to the top-layer interconnection lines with coupling capacitors between each circuit module.
3. The method of claim 1, wherein performing a timing analysis on each of the circuit modules based on the environmental model and circuit module data for each of the circuit modules comprises:
extracting parasitic parameters from the environment model and the circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
And according to the environment model corresponding to each circuit module, the module parasitic parameter file and the environment parasitic parameter file perform time sequence analysis on each circuit module to obtain a time sequence analysis result corresponding to each circuit module.
4. The method of claim 3, wherein performing full-chip timing analysis of the integrated circuit chip based on the top-level data, the environmental model of each of the circuit modules, and circuit module data comprises:
extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file;
assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file;
and carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
5. The method according to claim 3 or 4, wherein extracting parasitic parameters from the environmental model and circuit module data of each circuit module to obtain an environmental parasitic parameter file and a module parasitic parameter file corresponding to each circuit module, includes:
According to the environment model of each circuit module and the circuit module data, carrying out parasitic parameter extraction in a combined mode to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
wherein the module parasitic parameter file comprises: parasitic parameters inside the circuit module; the environment parasitic parameter file includes: coupling capacitance between the interconnect lines within the environmental model and the interconnect lines within the circuit module.
6. A timing analysis apparatus for an integrated circuit chip, the apparatus comprising:
the device comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring top-layer data of an integrated circuit chip and circuit module data of each of a plurality of circuit modules in the integrated circuit chip;
the generating module is used for generating an environment model corresponding to each circuit module according to the position information of each circuit module in the integrated circuit chip;
and the time sequence analysis module is used for carrying out time sequence analysis on each circuit module according to the environment model and the circuit module data of each circuit module, and carrying out full-chip time sequence analysis on the integrated circuit chip according to the top layer data, the environment model and the circuit module data of each circuit module to obtain a time sequence analysis result.
7. The apparatus of claim 6, wherein the generating module comprises:
the extracting unit is used for extracting a top-layer interconnection line with a coupling capacitor between each circuit module from the top-layer data according to the position information of each circuit module in the integrated circuit chip;
and the generating unit is used for generating an environment model corresponding to each circuit module according to the top-layer interconnection line with the coupling capacitance between each circuit module.
8. The apparatus of claim 7, wherein the timing analysis module comprises:
the first extraction unit is used for extracting parasitic parameters of the environment model and the circuit module data of each circuit module to obtain an environment parasitic parameter file and a module parasitic parameter file corresponding to each circuit module;
the first time sequence analysis unit is used for performing time sequence analysis on each circuit module according to the environment model corresponding to each circuit module, the module parasitic parameter file and the environment parasitic parameter file to obtain a time sequence analysis result corresponding to each circuit module;
the second extraction unit is used for extracting parasitic parameters of the top-level data to obtain a top-level parasitic parameter file;
The assembly unit is used for assembling the top layer parasitic parameter file, the module parasitic parameter file and the environment parasitic parameter file to obtain a full-chip parasitic parameter file;
and the second time sequence analysis unit is used for carrying out full-chip time sequence analysis on the integrated circuit chip based on the full-chip parasitic parameter file to obtain a time sequence analysis result corresponding to the integrated circuit chip.
9. An electronic device, comprising: a processor, and a memory coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1 to 5.
10. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1 to 5.
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