CN114330200A - Data processing system for very large scale circuit design partitioning - Google Patents
Data processing system for very large scale circuit design partitioning Download PDFInfo
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Abstract
The invention relates to a data processing system for designing and dividing a super-large scale circuit, which comprises a preset pin data structure, a preset weight mapping table and a processor, wherein the pin data structure comprises a pin identification data section and at least one pin parameter data section, and the pin parameter data section comprises a pin level identification data section and a pin pad parameter data section corresponding to a pin on the level; the weight mapping table comprises a pre-configured pin pad parameter and a mapping relation between a level and a corresponding weight value. According to the invention, the circuit design of the third party is segmented based on the pin parameters, and the segmented electronic design data is imported into the EDA software in parallel, so that the data import performance of the EDA software is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a data processing system for super-large scale circuit design segmentation.
Background
Electronic Design Automation (EDA) is a design method for completing the processes of functional design, integration, verification, physical design (including layout, wiring, layout, design rule check, etc.) of a Very Large Scale Integration (VLSI) chip by using Computer Aided Design (CAD) software. In the prior art, when the EDA software processes the import of the very large scale circuit design data, the design data of a third party is usually imported directly, and because the data volume is huge and there is some data without importing the DEA software, if the design data of the third party is directly imported into the DEA software in a large amount, the performance of the EDA software is seriously reduced. Therefore, how to improve the data importing performance of the EDA software for designing and importing the super-large scale circuit becomes an urgent technical problem to be solved.
Disclosure of Invention
The invention aims to provide a data processing system for designing and dividing a super-large scale circuit, which divides the circuit design of a third party based on pin parameters, and leads divided electronic design data into EDA software in parallel, thereby improving the data lead-in performance of the EDA software.
The invention provides a data processing system for designing and dividing a super-large scale circuit, which comprises a preset pin data structure, a preset weight mapping table and a processor, wherein the pin data structure comprises a pin identification data section and at least one pin parameter data section, and the pin parameter data section comprises a pin level identification data section and a pin pad parameter data section corresponding to a pin on the level; the weight mapping table comprises a pre-configured pin pad parameter and a mapping relation between a level and a corresponding weight value; the processor implements the steps of:
step S1, acquiring original design file data;
step S2, extracting all pin data { P ] from the original design file data based on the pin data structure1，P2，…PNWhere, the nth pin data
，
Is PnThe information of the x-th hierarchical level of (c),
is composed of
Corresponding pin pad parameter information, wherein the value range of x is 1 to Mn，MnIs PnCorresponding to the total number of the levels, wherein the value range of N is 1 to N, and N is the total number of pins;
step S3 based on PnAnd the weight mapping table acquisition PnCorresponding target state value Rn:
Wherein the content of the first and second substances,
is composed of
The corresponding weight values in the weight mapping table,
is composed of
Corresponding weight values in the weight mapping table;
step S4, acquiring CPU core number T, acquiring assignment state value U:
step S5 based on U and RnWill { P1，P2，…PNAnd equally distributing the original design file data into T groups, dividing the original design file data into T groups of design files to be imported based on T group distribution information, and importing the T groups of design files to be imported into EDA software in parallel.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the data processing system for designing and dividing the super-large scale circuit can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
according to the invention, the circuit design of the third party is segmented based on the pin parameters, and the segmented electronic design data is imported into the EDA software in parallel, so that the import performance of the EDA software for processing large-scale electronic design data is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the technical solutions can be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a diagram of a data processing system for partitioning a VLSI design according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of a data processing system for partitioning a very large scale circuit design according to the present invention.
An embodiment of the present invention provides a data processing system for design partitioning of a very large scale circuit, as shown in fig. 1, the data processing system includes a preset pin (pin) data structure, a preset weight mapping table, a processor, and a memory storing a computer program, where the pin data structure includes a pin identification data segment and at least one pin parameter data segment, and the pin parameter data segment includes a pin hierarchy identification data segment and a pin pad (pad) parameter data segment corresponding to a pin at the hierarchy. The weight mapping table comprises a mapping relation between a pre-configured pin pad parameter and a level and a corresponding weight value, namely the pin pad parameter, the corresponding weight value and the weight value corresponding to the level.
The processor implements the steps of:
step S1, acquiring original design file data;
the original design file data, that is, the design file data directly exported by the third-party software in the prior art, may be, for example, Printed Circuit Board (PCB) design file data, System In Package (SIP) design file data, or the like. The device file structure generally comprises a component (symbol) file, a pin file, a pad file and a hierarchy file, the sizes of the four files are generally unbalanced, the sizes of the component file and the pin file are generally far larger than those of the pad file and the hierarchy file, and the component file is generally smaller than that of the pin file. Because the pin file data volume corresponding to the super-large scale circuit design is huge and is the root cause for reducing the import performance of EDA software for processing large-scale electronic design data, the invention divides the original design file data based on the pin data.
As an embodiment, the step S1 is preceded by:
step S0, obtaining the total number N of pins corresponding to the original design file data, and if N is greater than the preset threshold value of the number of pins, executing step S1.
The pin number threshold is comprehensively determined based on factors such as specific application requirements and the computing power of EDA software. By setting the condition, the original design file with the pin data reaching a certain scale can be divided according to the invention, and if the scale is small, the file import cannot be influenced, and the division is not needed.
Step S2, extracting all pin data { P ] from the original design file data based on the pin data structure1，P2，…PNWhere, the nth pin data
，
Is PnThe information of the x-th hierarchical level of (c),
is composed of
Corresponding pin pad parameter information, wherein the value range of x is 1 to Mn，MnIs PnCorresponding to the total number of the levels, wherein the value range of N is 1 to N, and N is the total number of pins;
the component file includes component parameter information, which may specifically include X coordinates, Y coordinates, rotation state information, or component type information of the component. The pad file is used for storing pad parameter information, and specifically may include parameters such as pad shape and size. The hierarchical file is used for storing hierarchical file information. The pin file comprises pin parameter information and component pointer information, hierarchy pointer information and pad pointer information corresponding to the pins, wherein the corresponding component pointer information, hierarchy pointer information and pad pointer information can be specifically set as character string pointing information. The component pointer information points to component information corresponding to the component file, the level pointer information points to level information corresponding to the level file, and the pad pointer information points to pad information corresponding to the pad file. Based on corresponding component pointer information, level pointer information and pad pointer information, pin data { P } can be read from an original design file1，P2，…PN}。
As an example, the step S2 includes:
step S21, obtaining the nth pin identification ID from the pin filenBased on IDnCorresponding target level pointer information and target pad pointer information;
step S22, extracting corresponding target level information and target welding from the pad file and the level fileDisk information, generating corresponding pin data according to the pin data structure
。
Because the pin data volume is huge and the attribute information is more, the invention reads the required pin data from the original design file by setting the pin data structure without reading all the pin data, thereby reducing the data processing amount and improving the accuracy of data processing.
Step S3 based on PnAnd the weight mapping table acquisition PnCorresponding target state value Rn:
Wherein the content of the first and second substances,
is composed of
The corresponding weight values in the weight mapping table,
is composed of
And the corresponding weight value in the weight mapping table.
It should be noted that the target state value is mainly obtained by the pin pad parameter information and the corresponding weight, and in order to further improve the accuracy of the processing result, the weight corresponding to the hierarchy may also be added to the calculation. However, it is understood that, in a scenario where the requirement for accuracy is low and the amount of computation needs to be reduced, the influence of the weights of the hierarchies may not be considered, and in this case, the weights corresponding to the hierarchies may be set to equal weights, for example, may be directly set to 1.
It should be noted that, if the pins are evenly distributed into a plurality of CPU cores according to the number of the pins, the amount of data allocated to a certain core may still be huge because the number of the pins is large, and the amount of calculation required by different pins is different due to the difference of the number of the attributes and the difference of the attribute information. Therefore, the invention extracts the needed pin information by setting the pin data structure, integrates the extracted pin attribute and the belonged level, and the weight corresponding to the pin attribute and the belonged level, accurately obtains the target state value corresponding to each pin, and divides the target state value based on the state values, thereby being capable of dividing the target state value into a plurality of CPU cores in a balanced manner based on the calculated amount needed by the pin data processing.
Step S4, acquiring CPU core number T, acquiring assignment state value U:
step S5 based on U and RnWill { P1，P2，…PNAnd equally distributing the original design file data into T groups, dividing the original design file data into T groups of design files to be imported based on T group distribution information, and importing the T groups of design files to be imported into EDA software in parallel.
As an example, the step S5 includes:
step S51 based on U and RnWill { P1，P2，…PNEqually distributing the information into T groups, and distributing P corresponding to the information of each groupnCorresponding target state value RnThe difference between the sum and the U is less than or equal to a preset difference threshold;
based on U and RnWill { P1，P2，…PNThe allocation of the T groups as evenly as possible is the most ideal case if full averaging can be achieved, and if absolute averaging is not possible, relative even allocation is required to achieve as even as possible.
Step S52, calling a preset file output interface based on the T group distribution information to read corresponding pin data from the original design file, and parallelly outputting the T groups of design files to be imported;
after the pin information is divided, the corresponding file output interface can be directly called to read the corresponding pin data from the original design file in parallel. The specific configuration method of the file output interface is directly realized by adopting the prior art, and is not described herein again.
And step S53, reading the T groups of design files to be imported in parallel and importing the design files into EDA software.
As an embodiment, the following method may be specifically adopted to configure the weight mapping table, and the processor further implements the following steps:
step S10, acquiring geometric parameter information and geometric parameter description information corresponding to each pad parameter related in the original design file data;
the geometric parameter is specifically a shape, and the pad shape specifically includes a circle, a rectangle, a square, a regular octagon, and the like. The quantity of the geometric parameter description information corresponding to different shapes is different, and the required calculation amount is different.
Step S20, judging whether the quantity of the geometric parameter description information corresponding to the pad parameters is larger than a preset parameter quantity threshold value, if so, executing step S30, otherwise, executing step S40;
step S30, setting corresponding weight values according to the quantity of the geometric parameter description information corresponding to the pad parameters, wherein the quantity of the geometric parameter description information is in direct proportion to the corresponding weight values;
step S40, obtaining a weight value corresponding to another pad parameter which is closest to the geometric parameter information corresponding to the pad parameter, taking the weight value as a reference weight value, and adding a preset floating weight value to the reference weight value to obtain the weight value corresponding to the pad parameter.
Through the steps S10-S40, the weight value corresponding to each pad parameter may be obtained and stored in the weight mapping table. It should be noted that, the quantity of the geometric parameter description information corresponding to the pad parameter is greater than the preset parameter quantity threshold value, i.e., the description information is excessive (is a small amount of special data), if the weights are directly obtained all in a consistent processing manner, the processing of such special data consumes a large amount of computation, and may calculate a distorted weight, which affects the accuracy of the global partition, the present invention, therefore, performs a further classification process through step S20, acquires weights in different ways for the general data through step S30, by obtaining the weight for the special data based on the weight of the general data directly through step S40, it should be noted that, the floating weight value may be a fixed floating value according to the specific application scenario, through the steps S10-S40, the calculation amount is reduced, and the accuracy and the reliability of the global data processing result are improved.
The processor further implements the steps of:
step S100, obtaining the number of parameters corresponding to each level involved in the original design document data, and setting the weight corresponding to each level based on the number of parameters of each level, where the weight corresponding to each level is in direct proportion to the number of parameters of each level.
In step S100, the weight value corresponding to each level may be obtained and stored in the weight mapping table. It is understood that if the influence of the hierarchy factor is not considered, the hierarchy weight does not need to be set.
According to the embodiment of the invention, the circuit design of the third party is segmented based on the pin parameters, and the segmented electronic design data is imported into the EDA software in parallel, so that the import performance of the EDA software for processing large-scale electronic design data is improved. The data volume to be processed is determined before the program is executed, and the change of the task volume cannot be generated in the running process, so that a static load balancing mode is suitable for distributing the divided tasks to each execution thread in a fixed mode, and the load balancing can be achieved and the extra expense caused by dynamic task distribution can be avoided.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A data processing system for very large scale circuit design partitioning,
the device comprises a preset pin data structure, a preset weight mapping table and a processor, wherein the pin data structure comprises a pin identification data section and at least one pin parameter data section, and the pin parameter data section comprises a pin level identification data section and a pin pad parameter data section corresponding to a pin on the level; the weight mapping table comprises a pre-configured pin pad parameter and a mapping relation between a level and a corresponding weight value; the processor implements the steps of:
step S1, acquiring original design file data;
step S2, extracting all pin data { P ] from the original design file data based on the pin data structure1，P2，…PNWhere, the nth pin data
，
Is PnThe information of the x-th hierarchical level of (c),
is composed of
Corresponding pin pad parameter information, wherein the value range of x is 1 to Mn，MnIs PnCorresponding to the total number of the levels, wherein the value range of N is 1 to N, and N is the total number of pins;
step S3 based on PnAnd the weight mapping table acquisition PnCorresponding target state value Rn:
Wherein the content of the first and second substances,
is composed of
The corresponding weight values in the weight mapping table,
is composed of
Corresponding weight values in the weight mapping table;
step S4, acquiring CPU core number T, acquiring assignment state value U:
step S5 based on U and RnWill { P1，P2，…PNAnd equally distributing the original design file data into T groups, dividing the original design file data into T groups of design files to be imported based on T group distribution information, and importing the T groups of design files to be imported into EDA software in parallel.
2. The system of claim 1,
the step S1 is preceded by:
step S0, obtaining the total number N of pins corresponding to the original design file data, and if N is greater than the preset threshold value of the number of pins, executing step S1.
3. The system of claim 1,
the processor further implements the steps of:
step S10, acquiring geometric parameter information and geometric parameter description information corresponding to each pad parameter related in the original design file data;
step S20, judging whether the quantity of the geometric parameter description information corresponding to the pad parameters is larger than a preset parameter quantity threshold value, if so, executing step S30, otherwise, executing step S40;
step S30, setting corresponding weight values according to the quantity of the geometric parameter description information corresponding to the pad parameters, wherein the quantity of the geometric parameter description information is in direct proportion to the corresponding weight values;
step S40, obtaining a weight value corresponding to another pad parameter which is closest to the geometric parameter information corresponding to the pad parameter, taking the weight value as a reference weight value, and adding a preset floating weight value to the reference weight value to obtain the weight value corresponding to the pad parameter.
4. The system of claim 3,
the processor further implements the steps of:
step S100, obtaining the number of parameters corresponding to each level involved in the original design document data, and setting the weight corresponding to each level based on the number of parameters of each level, where the weight corresponding to each level is in direct proportion to the number of parameters of each level.
5. The system of claim 3,
the corresponding weight sizes of the hierarchies are set to be equal weight.
6. The system of claim 1,
the original design file data comprises a pin file, a component file, a pad file and a level file, wherein the component file comprises component parameter information, the pad file is used for storing the pad parameter information, the level file is used for storing the level file information, the pin file comprises the pin parameter information and component pointer information, level pointer information and pad pointer information corresponding to the pin, the component pointer information points to the component information corresponding to the component file, the level pointer information points to the level information corresponding to the level file, and the pad pointer information points to the pad information corresponding to the pad file.
7. The system of claim 6,
the step S2 includes:
step S21, obtaining the nth pin identification ID from the pin filenBased on IDnCorresponding target level pointer information and target pad pointer information;
step S22, extracting corresponding target level information and target pad information from the pad file and the level file, and generating corresponding pin data according to the pin data structure
8. The system of claim 1,
the step S5 includes:
step S51 based on U and RnWill { P1，P2，…PNEqually distributing the information into T groups, and distributing P corresponding to the information of each groupnCorresponding toTarget state value RnThe difference between the sum and the U is less than or equal to a preset difference threshold;
step S52, calling a preset file output interface based on the T group distribution information to read corresponding pin data from the original design file, and parallelly outputting the T groups of design files to be imported;
and step S53, reading the T groups of design files to be imported in parallel and importing the design files into EDA software.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116661856A (en) * | 2023-08-01 | 2023-08-29 | 上海合见工业软件集团有限公司 | Data splicing system of EDA software |
| CN117829044A (en) * | 2024-03-01 | 2024-04-05 | 上海合见工业软件集团有限公司 | EDA constraint detection system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1735891A (en) * | 2001-06-08 | 2006-02-15 | 韵律设计系统公司 | Method and system for chip design using remotely located resources |
| US20130111422A1 (en) * | 2011-10-31 | 2013-05-02 | Jeffrey B. Reed | Managing consistency of multiple-source fabrication data in an electronic design environment |
| CN113673192A (en) * | 2021-10-22 | 2021-11-19 | 南京集成电路设计服务产业创新中心有限公司 | Parallel accelerated extraction method for SPEF parasitic parameters of ultra-large scale integrated circuit |
| CN113761285A (en) * | 2021-11-09 | 2021-12-07 | 中科雨辰科技有限公司 | Metadata generation system based on multi-source data |
| CN113919252A (en) * | 2021-12-16 | 2022-01-11 | 北京云枢创新软件技术有限公司 | Component connectivity detection system based on different design data |
| CN113935276A (en) * | 2021-12-16 | 2022-01-14 | 北京云枢创新软件技术有限公司 | Design data mapping relation construction system |
-
2022
- 2022-03-15 CN CN202210250513.2A patent/CN114330200B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1735891A (en) * | 2001-06-08 | 2006-02-15 | 韵律设计系统公司 | Method and system for chip design using remotely located resources |
| US20130111422A1 (en) * | 2011-10-31 | 2013-05-02 | Jeffrey B. Reed | Managing consistency of multiple-source fabrication data in an electronic design environment |
| CN113673192A (en) * | 2021-10-22 | 2021-11-19 | 南京集成电路设计服务产业创新中心有限公司 | Parallel accelerated extraction method for SPEF parasitic parameters of ultra-large scale integrated circuit |
| CN113761285A (en) * | 2021-11-09 | 2021-12-07 | 中科雨辰科技有限公司 | Metadata generation system based on multi-source data |
| CN113919252A (en) * | 2021-12-16 | 2022-01-11 | 北京云枢创新软件技术有限公司 | Component connectivity detection system based on different design data |
| CN113935276A (en) * | 2021-12-16 | 2022-01-14 | 北京云枢创新软件技术有限公司 | Design data mapping relation construction system |
Non-Patent Citations (1)
| Title |
|---|
| 孔轶艳: "高职《EDA设计及应用》课程单元教学设计探析", 《大众科技》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116661856A (en) * | 2023-08-01 | 2023-08-29 | 上海合见工业软件集团有限公司 | Data splicing system of EDA software |
| CN116661856B (en) * | 2023-08-01 | 2023-10-20 | 上海合见工业软件集团有限公司 | Data splicing system of EDA software |
| CN117829044A (en) * | 2024-03-01 | 2024-04-05 | 上海合见工业软件集团有限公司 | EDA constraint detection system |
| CN117829044B (en) * | 2024-03-01 | 2024-05-14 | 上海合见工业软件集团有限公司 | EDA constraint detection system |
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