CN113671730A - Silicon photon pin junction light attenuation structure - Google Patents
Silicon photon pin junction light attenuation structure Download PDFInfo
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
- G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
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- G—PHYSICS
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- G02F1/0151—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction modulating the refractive index
- G02F1/0152—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction modulating the refractive index using free carrier effects, e.g. plasma effect
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Abstract
The application discloses silicon photon pin knot light attenuation structure, silicon photon pin knot light attenuation structure is based on SOI wafer and makes, and the SOI wafer includes: the device comprises a substrate layer, an oxygen burying layer and a device layer, wherein at least a first part is remained after the device layer is etched, and the first part is a silicon optical transmission waveguide; a first step and a second step are respectively formed on two sides of the silicon optical transmission waveguide; forming a P area and/or an N area on the first step, and forming an N area and/or a P area on the second step; forming a metal interconnection column on the P area and forming a metal interconnection column on the N area; forming a metal interconnection layer on one of the P regions; a metal interconnect layer is formed over one of the N regions. The problem that the adjustable optical attenuation structure in the prior art exists is solved through the application, and therefore the adjustable optical attenuation structure with wide attenuation range and quick response is provided.
Description
Technical Field
The application relates to the field of optical chips, in particular to a pin junction optical attenuation structure of a silicon photon.
Background
The Variable Optical Attenuator (VOA) plays an important role in an optical fiber communication network, and forms a gain balance optical amplifier with an erbium-doped fiber amplifier (EDFA); and an Amplified Spontaneous Emission (ASE) light source to form a gain controller; forming a gain balance ROADM with a reconfigurable optical add-drop multiplexer (ROADM); fig. 1 is a schematic diagram of VOA channel equalization according to the prior art; as shown in fig. 1, a gain balance MUX/DEMUX or the like is composed with a multiplexer/demultiplexer (MUX/DEMUX). Therefore, VOAs are one of the essential key components of fiber optic communication systems.
VOAs have a discrete type, i.e. they are formed by optical fibers, lenses, actuators, etc., and an integrated type, i.e. they are manufactured by semiconductor manufacturing processes and other functional devices on the same substrate material. Optical fiber communication systems are developing towards high speed, large capacity and reconfigurable direction, and VOAs are developing towards integration direction.
Silicon photonics is a new generation of technology based on silicon materials that utilizes existing CMOS processes for photonic device development and integration. The core of the silicon photon technology is to replace electricity by light, integrate a photon device and an electronic device on the same substrate material, and combine the advantages of ultra-large scale and ultra-high precision of integrated circuits represented by micro-electronics and the advantages of ultra-high speed and ultra-low power consumption of the photon technology. The method is widely applied to the fields of data centers, telecommunication, intelligent sensing and the like at present, and is one of the development directions for continuing moore's law.
Silicon has a good carrier dispersion effect, and the concentration of carriers of the pin junction is changed under the action of an external electric field, so that the distribution of an optical mode field is changed and light is absorbed, and a dimmable attenuation function is formed based on the carrier dispersion effect.
The silicon photonic core cladding has large refractive index difference and large effective refractive index, while the standard single-mode optical fiber core cladding based on fused silica has small refractive index difference and small effective refractive index, and the optical loss of the direct coupling of the silicon photonic core cladding and the standard single-mode optical fiber core cladding is very large. For silicon photonics chip applications, low loss optical coupling is a requirement to reduce the power consumption of optical devices.
Patents ZL201910413070.2 (adjustable optical attenuator and control method), patent ZL201310216150.1 (planar waveguide type adjustable optical attenuator), utility model ZL201821388443.2 (a silica-based silica thermo-optic adjustable optical attenuator), patent ZL201610024461.1 (a PLC type adjustable optical attenuator and method for improving temperature dependence thereof), utility model ZL201520835273.8 (a silica-based silica thermo-optic adjustable optical attenuator) and the like all realize optical attenuation based on MZI thermo-optic adjustable principle, and the structure is simple and low in cost, but slow in response; and due to the different materials and different thermal expansion coefficients, stress is generated, which leads to polarization dependent loss.
Patent 201510506308.8 (planar waveguide based graphene phase type optical modulator) proposes a planar waveguide based graphene phase type optical modulator, which can also be applied to optical attenuation, but graphene layers are difficult to manufacture in high volume and quality and are costly.
Disclosure of Invention
The embodiment of the application provides a silicon photonic pin junction optical attenuation structure to at least solve the problems of a dimmable optical attenuation structure in the prior art.
According to an aspect of the present application, there is provided a silicon photonic pin junction light attenuation structure, which is manufactured based on an SOI wafer, the SOI wafer including: the device comprises a substrate layer, a buried oxide layer and a device layer, wherein at least a first part is remained after the device layer is etched, the device layer on two sides of the first part is etched, and the first part is a silicon optical transmission waveguide; a first step and a second step are respectively formed on two sides of the silicon optical transmission waveguide, wherein the first step is an ion implantation or diffusion step, and the second step is an ion implantation or diffusion step; forming a P area and/or an N area on the first step, and forming the N area and/or the P area on the second step; forming a metal interconnection column on the P region, and forming a metal interconnection column on the N region; forming a metal interconnection layer on one of the P regions, wherein the metal interconnection layer formed on the P region is used for connecting metal interconnection columns on the P region; and forming a metal interconnection layer on one of the N regions, wherein the metal interconnection layer formed on the N region is used for connecting metal interconnection columns on the N region.
Further, one P region is formed on the first step, and one N region is formed on the second step; and/or forming at least one P area on the first step, forming a corresponding N area at the position of the second step corresponding to the P area on the first step, forming at least one N area on the first step, and forming a corresponding P area at the position of the second step corresponding to the N area on the first step.
Further, no metal interconnection layer is formed and the P region and the N region on the silicon optical transmission waveguide side are connected.
Further, a passivation layer is deposited on the metal interconnection layer on the P area and the N area, and the passivation layer is windowed to form metal pads of the P area and the N area.
Further, filling of a filling medium is carried out on the formed P region and the N region, and the distance between the filling medium and the thickness of the silicon optical transmission waveguide after filling is a preset distance.
Further, the fill medium includes at least one of: silicon dioxide, silicon dioxide doped with phosphorus and boron, divinyl siloxane bis-benzocyclobutene and monocrystalline silicon.
Further, the silicon optical transmission waveguide is of a stripe type or a ridge type.
Furthermore, an isolation groove is etched on the device layer, and the device layer between the isolation groove and the etched-out parts on two sides of the silicon optical transmission waveguide is reserved.
Further, after the device layer is etched, a second part coupled with the first part is remained besides the first part, and the second part comprises a silicon photonic waveguide taper section and a broadening section, wherein the silicon photonic waveguide taper section is coupled with the silicon photon transmission waveguide, and the width of the broadening section is greater than that of the silicon photonic waveguide taper section; and the silicon photonic waveguide taper section and the broadening section are provided with a vertical tapered waveguide and an outer broadening section, wherein the width of the outer broadening section is greater than that of the vertical tapered waveguide.
Further, the vertical tapered waveguide is a linear vertical tapered waveguide or a curved vertical tapered waveguide.
In the embodiment of the present application, the silicon photonic pin junction light attenuation structure is manufactured based on an SOI wafer, where the SOI wafer includes: the device comprises a substrate layer, a buried oxide layer and a device layer, wherein at least a first part is remained after the device layer is etched, the device layer on two sides of the first part is etched, and the first part is a silicon optical transmission waveguide; a first step and a second step are respectively formed on two sides of the silicon optical transmission waveguide, wherein the first step is an ion implantation or diffusion step, and the second step is an ion implantation or diffusion step; forming a P area and/or an N area on the first step, and forming the N area and/or the P area on the second step; forming a metal interconnection column on the P region, and forming a metal interconnection column on the N region; forming a metal interconnection layer on one of the P regions, wherein the metal interconnection layer formed on the P region is used for connecting metal interconnection columns on the P region; and forming a metal interconnection layer on one of the N regions, wherein the metal interconnection layer formed on the N region is used for connecting metal interconnection columns on the N region. The problem that the adjustable optical attenuation structure in the prior art exists is solved through the application, and therefore the adjustable optical attenuation structure with wide attenuation range and quick response is provided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 is a schematic diagram of VOA channel equalization according to the prior art;
FIG. 2 is a schematic perspective view of a silicon photonic pin junction light attenuating structure according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a strip waveguide of a silicon photonic pin junction light attenuating structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a ridge waveguide of a silicon photonic pin junction light attenuating structure according to an embodiment of the present application;
FIG. 5 is a first schematic diagram of a P region and an N region in a structure according to an embodiment of the present application;
FIG. 6 is a second schematic diagram of a P region and an N region in a structure according to an embodiment of the present application;
FIG. 7 is a third schematic diagram of P and N regions in a structure according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a linear vertical taper waveguide according to an embodiment of the present application; and the number of the first and second groups,
FIG. 9 is a schematic diagram of a curved vertical tapered waveguide according to an embodiment of the present application.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In this embodiment, a silicon photonic pin junction optical attenuation structure is provided, where the silicon photonic pin junction optical attenuation structure is manufactured based on an SOI wafer, and the SOI wafer includes: the device comprises a substrate layer, an oxygen burying layer and a device layer, wherein at least a first part is remained after the device layer is etched, the device layer on two sides of the first part is etched, and the first part is a silicon optical transmission waveguide; a first step and a second step are respectively formed on two sides of the silicon optical transmission waveguide, wherein the first step is an ion implantation or diffusion step, and the second step is an ion implantation or diffusion step; forming a P area and/or an N area on the first step, and forming an N area and/or a P area on the second step; forming a metal interconnection column on the P area and forming a metal interconnection column on the N area; forming a metal interconnection layer on one of the P regions, wherein the metal interconnection layer formed on the P region is used for connecting metal interconnection columns on the P region; and forming a metal interconnection layer on one of the N regions, wherein the metal interconnection layer formed on the N region is used for connecting the metal interconnection columns on the N region.
When etching, an isolation groove can be etched on the device layer, and the device layer between the isolation groove and the etched-off parts on two sides of the silicon optical transmission waveguide is reserved.
The problem that the adjustable optical attenuation structure in the prior art exists is solved through the embodiment, and therefore the adjustable optical attenuation structure with wide attenuation range and quick response is provided.
The P region and the N region may be formed in various ways, for example, a P region is formed on the first step, and an N region is formed on the second step; for another example, at least one P region is formed on the first step, a corresponding N region is formed at a position of the second step corresponding to the P region on the first step, at least one N region is formed on the first step, and a corresponding P region is formed at a position of the second step corresponding to the N region on the first step.
In the case where a plurality of P regions or N regions are present, no metal interconnection layer is formed and the P regions and the N regions on the silicon optical transmission waveguide side are connected.
There are also a number of ways to make the metal pads, and in an alternative embodiment, a passivation layer is deposited on the metal interconnect layer over the P and N regions, and the metal pads for the P and N regions are formed by windowing the passivation layer.
And filling a filling medium on the formed P region and the N region, wherein the filling medium is a preset distance away from the thickness of the silicon optical transmission waveguide after filling. The filling medium may be of various types, for example, the filling medium may include at least one of: silicon dioxide, silicon dioxide doped with phosphorus and boron, divinyl siloxane bis-benzocyclobutene and monocrystalline silicon.
The shape of the silicon light-transmitting waveguide may be various, and for example, may be a stripe or a ridge.
After the device layer is etched, a second part coupled with the first part is remained besides the first part, and the second part comprises a silicon photonic waveguide taper section and a broadening section, wherein the silicon photonic waveguide taper section is coupled with the silicon photon transmission waveguide, and the width of the broadening section is greater than that of the silicon photonic waveguide taper section; and a vertical tapered waveguide and an outer extension wide section are arranged on the silicon optical waveguide tapered section and the extension wide section, wherein the width of the outer extension wide section is larger than that of the vertical tapered waveguide. The vertical tapered waveguide may be a linear vertical tapered waveguide or may be a curved vertical tapered waveguide.
An optional embodiment is described below with reference to the accompanying drawings, and the optional embodiment provides a pin junction type tunable optical attenuation structure based on a carrier dispersion effect, which has a wide attenuation range and a fast response, and is compatible with a CMOS process and capable of being manufactured in batch. The preferred embodiment also provides a low-loss optical coupling structure of the silicon photonic chip, which has high optical coupling efficiency and is easy to manufacture. The embodiment also provides a silicon photon adjustable attenuation structure and a low-loss optical coupling structure, which are easily integrated with other silicon optical functional structures to form an integrated silicon optical chip. In the present alternative embodiment, the principle of light absorption attenuation based on carrier absorption is first described.
In classical dispersion theory, the change of the free carrier concentration changes the real part and the imaginary part of the complex refractive index of the silicon material, namely the change of the general refractive index n and the absorption coefficient alpha. The drive model is described below (SorefR. AandLorenzo J. P. all-silicon active and identified-wave components for. lambda. 1.3 and. lambda. 1.6 μm. IEEE Journal of Quantum Electronics,1986,22(6):873 and 879),
wherein q is the electronic charge, λ is the wavelength of light wave, n is the general refractive index of pure silicon, ε0Is the free space dielectric constant, c is the speed of light in vacuum,
and
respectively an electron effective mass and a hole effective mass, NeAnd NhRespectively, the free electron concentration and the free hole concentration, μeAnd mupRespectively electron mobility and hole mobility.
The Drude model does not take into account the scattering process of carriers, including phonon assist or impurity assist in the material, NedeljkovicM and SorefR et al (NedeljkovicM, SorefR. A, and MashanovichG. Z. free-carrier electro-recovery and electro-adsorption modulation schemes for silicon over the changes of the 1-14 micro-injected wavelengthwide range, IEEE Photonics Journal,2011,3(6): 1171-1180) have obtained the changes in the complex refractive index and imaginary part of the silicon material under the change of the carrier concentration through experiments and the Kramers-Kronig relationship, and the change in the real part and imaginary part of the silicon material under the condition of 1550nm has:
Δn＝-5.4×10-22ΔN1.011-1.53×10-18ΔP0.838 (3)
Δα＝8.88×10-21ΔN1.167+5.84×10-20ΔP1.109 (4)
when the input optical power is PInThen, through the power-on pn region with length L, the output optical power is as follows due to the absorption of the carriers
Pout＝Pin·exp(-α·L) (5)
Wherein α comprises the intrinsic absorption coefficient α of the silicon material0And a carrier absorption coefficient Δ α. According to the definition of insertion loss, there are
Attenuation(dB)＝-10×log{exp[(α0+Δα)×L]}
＝4.3429×(α0+Δα)×L (6)
In the formula, alpha0Generally taken as alpha0＝0.023/cm。
In this embodiment, the silicon photonic pin junction optical attenuation structure and the 3D optical coupling structure shown in fig. 2, 3and 4 are described, which are manufactured using an SOI wafer substrate, and may be a thin device layer (top silicon) SOI wafer having a thickness of 220nm, 310nm, 340nm, or the like, or a thick device layer SOI wafer having a thickness of 1-10 μm, so that an integrated silicon photonic chip having an optical attenuation structure and an optical coupling structure with low power consumption, high-speed response, and low insertion loss can be realized, and the device layer having a thickness of 3 μm is described as an example. The scheme is as follows:
1) the SOI wafer is composed of a base silicon 1, a buried oxide layer 2(BOX layer), and a device layer 3 (top silicon). The isolation groove 32 is processed on the device layer through the semiconductor micro-processing technology such as masking, photoetching, etching and the like, the etching is carried out until the oxygen burying layer 2 is reached, and the over-etching amount of the oxygen burying layer 2 is more than 0.2 mu m.
2) And etching the device layer by 2.4-2.7 μm through mask, photoetching, etching and other semiconductor micromachining technologies, leaving a thickness of 0.3-0.6 μm above the oxygen buried layer, and forming a silicon light transmission waveguide 31 in an un-etched area.
3) Next, 2) the buried oxide layer 2 is etched down by semiconductor microfabrication techniques such as masking, photolithography, etching, etc., to form an ion implantation or diffusion step 33 and a silicon light-transmitting waveguide 31.
4) The silicon optical waveguide transmission structure 31 may be a strip waveguide or a ridge waveguide, as shown at 31 in fig. 3and 4.
5) The silicon optical waveguide 31 and the ion implantation or diffusion step 33 can be fabricated by mask, photolithography, etching, or other semiconductor microfabrication techniques.
6) P region 34 and N region 35, or P region 35 and N region 34, respectively, are formed on ion implantation or diffusion step 33 by masking, photolithography, ion implantation or diffusion, annealing.
7) Filling the structure formed in the step 6) with a filling medium 4 such as silicon dioxide or silicon dioxide doped with phosphorus and boron, divinyl siloxane bis (benzocyclobutene) (DVS-BCB), monocrystalline silicon and the like, and then flattening the structure by a Chemical Mechanical Polishing (CMP) process, wherein the thickness of the filling medium 4 from the silicon optical waveguide 31 is at least 0.2 mu m.
8) The low loss coupling of silicon photonics chips with standard single mode optical fibers is a prerequisite for their application. The coupling waveguide 5 is composed of a silicon optical waveguide taper section 52, an extension section 51, a vertical taper waveguide 54 and an epitaxial extension section 53, and the silicon optical waveguide taper section 52, the extension section 51 and the silicon optical transmission waveguide 31 are manufactured together by semiconductor microfabrication techniques such as masking, photolithography and etching. After the CMP planarization, the silicon photonic waveguide taper segment 52 and the extension segment 51 are windowed by a semiconductor microfabrication technique such as masking, photolithography, etching, etc., then single crystal silicon is epitaxially grown, and then the vertical tapered waveguide 54 and the epitaxial extension segment 53 are formed by a semiconductor microfabrication technique such as masking, photolithography, etching, etc. The vertical taper waveguide 54 may be a linear vertical taper (see FIG. 8) or a curved vertical taper (see FIG. 9).
9) Metal interconnection pillars 36 and 37 for P and N regions are then formed by masking, photolithography, sputtering, and metal interconnection layers 38 and 39 for P and N regions are then formed by masking, photolithography, etching.
10) And then depositing a passivation layer on the substrate by a low-pressure chemical vapor deposition method, and then windowing to form metal pads of the P area and the N area.
The P region and the N region on the ion implantation or diffusion step 33, which may be fig. 5, or fig. 6 and fig. 7, are in a segmented form, and the P region and the N region are formed by crossing, and the number of segments may be 2, 3, 4, 5 … …, and in principle, the length of the P region or the N region after segmentation cannot be smaller than the minimum lithography size.
In the above embodiment, the dimmable attenuation silicon photonic chip based on the carrier dispersion effect is composed of an input/output coupling waveguide, a pin junction cascade, a filling medium, an interconnection metal and an electrode, and a passivation layer is deposited on the interconnection electrode for protection. The pin junction is composed of a P-doped region, an N-doped region and a silicon optical transmission waveguide, wherein the P-doped region and the N-doped region are respectively interconnected through a metal interconnection column, an interconnection electrode and a metal bonding pad. The filling medium can be silicon dioxide or silicon dioxide doped with phosphorus and boron, divinyl siloxane bis-benzene cyclobutene (DVS-BCB) or monocrystalline silicon. The input/output coupling waveguide is composed of a vertical waveguide and a widening waveguide, and is actually grown on the silicon optical transmission waveguide through a region epitaxial single crystal silicon.
The embodiment has the advantages that the pin junction type dimmable attenuation structure based on the carrier dispersion effect, the silicon optical waveguide and standard single-mode fiber low-loss optical coupling structure are provided, the attenuation range is wide, the response is fast, the optical coupling efficiency is high, the integrated silicon optical chip is easily integrated with other silicon optical functional structures to form the integrated silicon optical chip, the manufacturing process is compatible with the CMOS process, and batch manufacturing can be realized.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A silicon photon pin junction light attenuation structure is characterized in that the silicon photon pin junction light attenuation structure is manufactured based on an SOI wafer,
the SOI wafer comprises: the device comprises a substrate layer, a buried oxide layer and a device layer, wherein at least a first part is remained after the device layer is etched, the device layer on two sides of the first part is etched, and the first part is a silicon optical transmission waveguide;
a first step and a second step are respectively formed on two sides of the silicon optical transmission waveguide, wherein the first step is an ion implantation or diffusion step, and the second step is an ion implantation or diffusion step;
forming a P area and/or an N area on the first step, and forming the N area and/or the P area on the second step;
forming a metal interconnection column on the P region, and forming a metal interconnection column on the N region; forming a metal interconnection layer on one of the P regions, wherein the metal interconnection layer formed on the P region is used for connecting metal interconnection columns on the P region; and forming a metal interconnection layer on one of the N regions, wherein the metal interconnection layer formed on the N region is used for connecting metal interconnection columns on the N region.
2. The structure of claim 1,
forming one of the P regions on the first step and one of the N regions on the second step; and/or the presence of a gas in the gas,
and forming at least one P area on the first step, forming a corresponding N area at the position of the second step corresponding to the P area on the first step, forming at least one N area on the first step, and forming a corresponding P area at the position of the second step corresponding to the N area on the first step.
3. The structure of claim 2, wherein no metal interconnect layer is formed and the P and N regions on one side of the silicon light-transmitting waveguide are connected.
4. The structure of claim 1, wherein a passivation layer is deposited on the metal interconnect layer over the P and N regions, and wherein the passivation layer is windowed to form metal pads for the P and N regions.
5. The structure of claim 1, wherein a filling of a filling medium is performed on the formed P region and N region, and the filling medium is a predetermined distance from a thickness of the silicon optical transmission waveguide after filling.
6. The structure of claim 5, wherein the fill medium comprises at least one of: silicon dioxide, silicon dioxide doped with phosphorus and boron, divinyl siloxane bis-benzocyclobutene and monocrystalline silicon.
7. The structure of claim 1, wherein the silicon light-transmitting waveguide is stripe or ridge shaped.
8. The structure of claim 1, wherein an isolation trench is etched in the device layer, and the device layer between the isolation trench and the etched-away portions on both sides of the silicon optical transmission waveguide is retained.
9. The structure of any one of claims 1 to 8, wherein a second portion coupled to the first portion remains in addition to the first portion after the device layer is etched, the second portion comprising a silicon photonic waveguide taper and a broadening, wherein the silicon photonic waveguide taper is coupled to the silicon photon transmitting waveguide, and the broadening has a width greater than the silicon photonic waveguide taper; and the silicon photonic waveguide taper section and the broadening section are provided with a vertical tapered waveguide and an outer broadening section, wherein the width of the outer broadening section is greater than that of the vertical tapered waveguide.
10. The structure of claim 9, wherein the vertical taper waveguide is a linear vertical taper waveguide or a curved vertical taper waveguide.
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