CN113660763A - Circuit board - Google Patents

Circuit board Download PDF

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Publication number
CN113660763A
CN113660763A CN202010396445.1A CN202010396445A CN113660763A CN 113660763 A CN113660763 A CN 113660763A CN 202010396445 A CN202010396445 A CN 202010396445A CN 113660763 A CN113660763 A CN 113660763A
Authority
CN
China
Prior art keywords
layer
circuit
circuit layer
circuit board
inlayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010396445.1A
Other languages
Chinese (zh)
Other versions
CN113660763B (en
Inventor
郭宏艳
何明展
沈芾云
韦文竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Original Assignee
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avary Holding Shenzhen Co Ltd, Qing Ding Precision Electronics Huaian Co Ltd filed Critical Avary Holding Shenzhen Co Ltd
Priority to CN202010396445.1A priority Critical patent/CN113660763B/en
Publication of CN113660763A publication Critical patent/CN113660763A/en
Application granted granted Critical
Publication of CN113660763B publication Critical patent/CN113660763B/en
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Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0215—Grounding of printed circuits by connection to external grounding means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/045—Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details

Abstract

A circuit board comprises an outer layer circuit layer and a plurality of inner layer circuit layers, wherein the circuit board comprises a signal line and a power supply voltage line, the signal line is arranged on the outer layer circuit layer and one of the inner layer circuit layers, and the signal line on the outer layer circuit layer is electrically connected with the signal line on the inner layer circuit layer in a hole jumping mode through a first via hole; the power voltage line is located a plurality ofly inlayer circuit layer is located a plurality of the power voltage line on inlayer circuit layer passes through second via electric connection.

Description

Circuit board
Technical Field
The present invention relates to a circuit board.
Background
The 5G technology has the technical characteristics of large bandwidth, low time delay and super-large scale connection, and especially the millimeter wave frequency band puts higher requirements on antenna receiving, transmitting and transmitting, so that the use amount of radio frequency cables is increased. In the 5G middle and high-end models, LCP/MPI flexible boards are gradually adopted to directly undertake the radio frequency connection function. Compared with a radio frequency cable, the LCP/MPI flexible printed circuit board has a compact structure and a small occupied volume.
In the conventional design, the power voltage line, the power line, the control line and the signal transmission line are usually disposed in the same inner layer. This results in too many cables in the same layer and a large occupied space. The supply voltage lines need to pass large currents and therefore require conductors of large dimensions. If the wiring is to be arranged on the outer layer, a shielding layer is required to be added, and the problems of current shunt and circuit allowance are also required to be considered.
Disclosure of Invention
Accordingly, there is a need for a circuit board to solve the above problems.
A circuit board comprises an outer layer circuit layer and a plurality of inner layer circuit layers, wherein the circuit board comprises a signal line and a power supply voltage line, the signal line is arranged on the outer layer circuit layer and one of the inner layer circuit layers, and the signal line on the outer layer circuit layer is electrically connected with the signal line on the inner layer circuit layer in a hole jumping mode through a first via hole; the power voltage line is located a plurality ofly inlayer circuit layer is located a plurality of the power voltage line on inlayer circuit layer passes through second via electric connection.
Further, the second via hole forms an isolated connection pad or an isolated connection pad on the outer layer circuit layer.
Furthermore, the circuit board further comprises a power line, the inner layer circuit layer comprises a first inner layer circuit layer adjacent to the outer layer circuit layer, the power line is arranged on the first inner layer circuit layer, the power line is connected with a third via hole, and the third via hole is formed in the outer layer circuit layer to form an isolated connecting pad or an isolated connecting pad.
Furthermore, a plurality of the inner layer circuit layers further comprise a second inner layer circuit layer adjacent to the first inner layer circuit layer, the power line is further arranged on the second inner layer circuit layer, and the power line on the second inner layer circuit layer is electrically connected with the power line on the first inner layer circuit layer through a third via hole.
Furthermore, the inner circuit layers further comprise a third inner circuit layer adjacent to the second inner circuit layer and a fourth inner circuit layer adjacent to the third inner circuit layer, the power line is further arranged on the third inner circuit layer and the fourth inner circuit layer, and the power line on the third inner circuit layer and the power line on the fourth inner circuit layer are electrically connected through a fourth via hole.
Further, the power lines on the first inner layer circuit layer and the second inner layer circuit layer are electrically connected to the power lines on the third inner layer circuit layer and the fourth inner layer circuit layer through a fifth via hole.
Further, the signal line is located on the outer layer circuit layer and the third inner layer circuit layer, and the first via hole penetrates through and is not electrically connected with the second inner layer circuit layer and the first inner layer circuit layer.
Furthermore, the circuit board further comprises a control wire, the control wire is located on the first inner layer circuit layer and connected with a sixth via hole, and an isolated connecting pad or an isolated connecting pad is formed on the outer layer circuit layer by the sixth via hole.
The circuit board further comprises a grounding wire, the grounding wire is arranged on the outer layer circuit layer and the plurality of inner layer circuit layers which are positioned on two sides of the signal wire, and the grounding wire is electrically connected to a grounding end through a seventh via hole.
Furthermore, the material of the dielectric layer is a liquid crystal high molecular polymer.
The circuit board of this embodiment sets up a plurality of inlayer circuit layers, locates a plurality ofly with mains voltage line on the inlayer circuit layer, improved mains voltage line and concentrated the too big problem of circuit board that distributes and lead to in the intermediate level.
Drawings
Fig. 1 is a sectional view of a circuit board according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of the circuit board of fig. 1 at another angle.
Fig. 3a and 3b are schematic diagrams of a first via connection signal line of the circuit board shown in fig. 1.
Fig. 4a and 4b are schematic diagrams of isolated connection pads and isolated connection pads formed by the second via holes of the circuit board shown in fig. 1.
Fig. 5 is a partial cross-sectional view of the power line connection of the circuit board shown in fig. 1.
Description of the main elements
Circuit board 100
Outer layer circuit layer 10
First outer layer circuit layer 11
Second outer wiring layer 12
Inner wiring layer 20
First inner wiring layer 21
Second inner wiring layer 22
Third inner wiring layer 23
Fourth inner wiring layer 24
Signal line 30
First via hole 31
Supply voltage line 40
Second via hole 41
Isolated connection pads 411, 512
Isolated connection pads 412, 532
Power cord 50
Third via hole 51
Fourth via hole 52
Fifth via hole 53
Control line 60
Sixth via hole 61
Ground wire 70
Seventh via hole 71
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Referring to fig. 1, a circuit board 100 according to a preferred embodiment of the invention includes an outer circuit layer 10, a plurality of inner circuit layers 20, and a dielectric layer 101. The dielectric layer 101 is a Liquid Crystal Polymer (LCP). In the illustrated embodiment, the outer wiring layer 10 includes a first outer wiring layer 11 and a second outer wiring layer 12. The plurality of inner layer wiring layers 20 include a first inner layer wiring layer 21, a second inner layer wiring layer 22, a third inner layer wiring layer 23, and a fourth inner layer wiring layer 24. The first inner layer circuit layer 21, the second inner layer circuit layer 22, the third inner layer circuit layer 23 and the fourth inner layer circuit layer 24 are sequentially stacked between the first outer layer circuit layer 11 and the second outer layer circuit layer 12.
It is understood that in other embodiments, the inner circuit layer 20 may be provided in any number greater than one as desired.
The circuit of the circuit board 100 includes a signal line 30(IF), a power voltage line 40(VBATT), a power line 50, a control line 60(PON), and a ground line 70 (GND).
Referring to fig. 1 to fig. 3b, the signal line 30 is disposed on the outer circuit layer 10 and one of the inner circuit layers 20. The signal line 30 is preferably disposed on the inner wiring layer 20 located in the middle of the circuit board 100. The signal line 30 on the outer circuit layer 20 and the signal line 20 on the inner circuit layer are electrically connected in a via-hole manner through the first via hole 31 30.
In the illustrated embodiment, the signal lines 30 are disposed on the first outer layer circuit layer 11 and the third inner layer circuit layer 23. The wires of the first and second inner wire layers 21 and 22 are not in electrical contact with the first via hole 31. Specifically, the first inner circuit layer 21 and the second inner circuit layer 22 may be provided with an avoiding hole 311 to avoid the first via hole 31.
For the signal line 30 on the third inner wiring layer 23, the outer wiring layer 10 is a reference layer. As for the signal line 30 on the first outer layer line layer 11, any one of the first inner layer line layer 21, the second inner layer line layer 22, the third inner layer line layer 23, and the fourth inner layer line layer 24 is a reference layer. The impedance matching can be flexibly selected according to the impedance matching.
Referring to fig. 1, fig. 4a and fig. 4b, the power voltage line 40 is disposed on the inner circuit layers 20, and the power voltage lines 40 on the inner circuit layers 20 are electrically connected through the second via holes 41.
In the illustrated embodiment, the power voltage lines 40 are respectively disposed on the first inner circuit layer 21, the second inner circuit layer 22, the third inner circuit layer 23, and the fourth inner circuit layer 24.
The second via hole 41 is formed through the entire circuit board 100 and forms an isolated connection pad 411 or an isolated connection pad 412 on the outer circuit layer 10. When the second via hole 41 is used as a connection port. The second via hole forms an isolated connection pad 411 in the outer layer circuit layer 10. When the second via hole 41 is used as a ground port. The second via hole forms an isolated connection pad 412 in the outer circuit layer 10.
Referring to fig. 1 and 5, the power line 50 is disposed on the first inner circuit layer 21. The power line 50 is connected to the third via hole 51. The third via hole 51 forms an isolated connection pad 512 or an isolated connection pad 532 on the first outer layer circuit layer 11.
In the illustrated embodiment, the power line 50 may also be disposed on the second inner circuit layer 22. The third via hole 51 is electrically connected to the power line 50 on the first inner circuit layer 21 and the power line 50 on the second inner circuit layer 22.
In the illustrated embodiment, the power line 50 may also be disposed on the third inner circuit layer 23 and the fourth inner circuit layer 24. The power line 50 on the third inner circuit layer 23 and the power line 50 on the fourth inner circuit layer 24 are electrically connected through a fourth via 52.
The power lines 50 on the first inner circuit layer 21 and the second inner circuit layer 22 are electrically connected to the power lines 50 on the third inner circuit layer 23 and the fourth inner circuit layer 24 through fifth via holes 53. The fifth via hole 53 further forms an isolation connection pad 412 on the first outer layer circuit layer 11 and the second outer layer circuit layer 12, respectively.
Referring to fig. 1, the control line 60 is located on the first inner circuit layer 21. The control line 21 connects the sixth via hole 61. The sixth via hole 61 forms an isolated connection pad or an isolated connection pad on the first outer layer circuit layer 11.
The ground line 70 is disposed on the outer layer circuit layer 10 and the plurality of inner layer circuit layers 20 on both sides of the signal line 30. The outer wiring layer 10 and the ground wires 70 of the inner wiring layers 20 are electrically connected to the ground terminal through the seventh via holes 71.
The circuit board 100 of the embodiment is provided with a plurality of inner layer circuit layers 20, and the power supply voltage lines 40 are arranged on the inner layer circuit layers 20, so that the problem that the circuit board 100 is too large due to the fact that the power supply voltage lines 40 are distributed on the middle layers in a concentrated mode is solved.
Although the present invention has been described with reference to the above preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. The utility model provides a circuit board, includes outer layer circuit layer, a plurality of inlayer circuit layer and dielectric layer, its characterized in that: the circuit board comprises signal wires and a power supply voltage wire, the signal wires are arranged on the outer layer circuit layer and one of the inner layer circuit layers, and the signal wires on the outer layer circuit layer are electrically connected with the signal wires on the inner layer circuit layer in a hole jumping mode through a first via hole; the power voltage line is located a plurality ofly inlayer circuit layer is located a plurality of the power voltage line on inlayer circuit layer passes through second via electric connection.
2. The circuit board of claim 1, wherein: the second via hole forms an isolated connecting pad or an isolated connecting pad on the outer layer circuit layer.
3. The circuit board of claim 1, wherein: the circuit board further comprises a power line, the inner layer circuit layer is a plurality of inner layer circuit layers adjacent to the outer layer circuit layer, the power line is arranged on the first inner layer circuit layer, the power line is connected with a third conducting hole, and the outer layer circuit layer forms an isolated connecting pad or an isolated connecting pad.
4. The circuit board of claim 3, wherein: a plurality of the inner layer circuit layer further comprises a second inner layer circuit layer adjacent to the first inner layer circuit layer, the power line is further arranged on the second inner layer circuit layer, and the power line on the second inner layer circuit layer is electrically connected with the power line on the first inner layer circuit layer through the third via hole.
5. The circuit board of claim 4, wherein: a plurality of inlayer circuit layer still includes and is close to the third inlayer circuit layer on second inlayer circuit layer and is close to the fourth inlayer circuit layer on third inlayer circuit layer, the power cord still set up in third inlayer circuit layer and fourth inlayer circuit layer are located the power cord on third inlayer circuit layer and being located the power cord on fourth inlayer circuit layer passes through the fourth via hole electricity and connects.
6. The circuit board of claim 5, wherein: and the power lines on the first inner layer circuit layer and the second inner layer circuit layer are electrically connected with the power lines on the third inner layer circuit layer and the fourth inner layer circuit layer through a fifth via hole.
7. The circuit board of claim 5, wherein: the signal line is located in the outer layer circuit layer and the third inner layer circuit layer, and the first via hole penetrates through the second inner layer circuit layer and is not electrically connected with the first inner layer circuit layer.
8. The circuit board of claim 3, wherein: the circuit board further comprises a control wire, the control wire is located on the first inner layer circuit layer and connected with a sixth via hole, and the sixth via hole is used for forming an isolated connecting pad or an isolated connecting pad on the outer layer circuit layer.
9. The circuit board of claim 1, wherein: the circuit board further comprises a grounding wire, the grounding wire is arranged on the outer layer circuit layer and the inner layer circuit layers which are positioned on two sides of the signal wire, and the grounding wire is electrically connected to a grounding end through a seventh conducting hole.
10. The circuit board of claim 1, wherein: the medium layer is made of liquid crystal high molecular polymer.
CN202010396445.1A 2020-05-12 2020-05-12 Circuit board Active CN113660763B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010396445.1A CN113660763B (en) 2020-05-12 2020-05-12 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010396445.1A CN113660763B (en) 2020-05-12 2020-05-12 Circuit board

Publications (2)

Publication Number Publication Date
CN113660763A true CN113660763A (en) 2021-11-16
CN113660763B CN113660763B (en) 2022-12-06

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ID=78488652

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010396445.1A Active CN113660763B (en) 2020-05-12 2020-05-12 Circuit board

Country Status (1)

Country Link
CN (1) CN113660763B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1294484A (en) * 1999-10-27 2001-05-09 华硕电脑股份有限公司 Printed circuit board structure
CN202262021U (en) * 2011-09-01 2012-05-30 青岛海信电器股份有限公司 Six-layer circuit board and electronic terminal
CN102548183A (en) * 2010-12-30 2012-07-04 北大方正集团有限公司 Multilayer circuit board and manufacturing method thereof
CN108668425A (en) * 2017-03-31 2018-10-16 鹏鼎控股(深圳)股份有限公司 Signal transmssion line ontology and preparation method thereof, USBTypeC connectors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1294484A (en) * 1999-10-27 2001-05-09 华硕电脑股份有限公司 Printed circuit board structure
CN102548183A (en) * 2010-12-30 2012-07-04 北大方正集团有限公司 Multilayer circuit board and manufacturing method thereof
CN202262021U (en) * 2011-09-01 2012-05-30 青岛海信电器股份有限公司 Six-layer circuit board and electronic terminal
CN108668425A (en) * 2017-03-31 2018-10-16 鹏鼎控股(深圳)股份有限公司 Signal transmssion line ontology and preparation method thereof, USBTypeC connectors

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Publication number Publication date
CN113660763B (en) 2022-12-06

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