CN113656234A

CN113656234A - Self-testing device and self-testing method for chip USB module

Info

Publication number: CN113656234A
Application number: CN202111208195.5A
Authority: CN
Inventors: 罗盛裕; 杨智华; 周黄
Original assignee: Shenzhen Zhixiang Technology Co ltd
Current assignee: Shenzhen Zhixiang Technology Co ltd
Priority date: 2021-10-18
Filing date: 2021-10-18
Publication date: 2021-11-16
Anticipated expiration: 2041-10-18
Also published as: CN113656234B

Abstract

The invention discloses a self-testing device and a self-testing method of a chip USB module, and relates to the technical field of chip testing. The device comprises: the special function register interface is used for providing a starting signal for the serial interface engine module; the serial interface engine module starts a chip USB test mode according to the starting signal, sends preset test data to the PHY module and receives decoded self-test data from the PHY module; the PHY module receives preset test data, encodes the preset test data according to a preset encoding algorithm, sends the encoded preset test data to the USB bus, receives self-test data returned after passing through the self-test circuit from the USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the self-test data to the serial interface engine module; and the self-test circuit is used for outputting the coded test data output by the PHY module to the USB bus to form self-test data, and then the self-test data is returned to the PHY module. According to the embodiment of the invention, the self-test circuit is added in the chip to realize that the USB module completes self-test in the chip without a tester, so that the cost is reduced.

Description

Self-testing device and self-testing method for chip USB module

Technical Field

The invention relates to the technical field of chip testing, in particular to a self-testing device and a self-testing method of a chip USB module.

Background

Universal Serial Bus (USB) is a common Serial interface, has the advantages of fast speed and plug-in capability, and is widely used in computers, mobile phones, and various devices. Therefore, more and more chips are embedded with USB functional modules during design.

Currently, as shown in fig. 1 and fig. 2, a general chip USB module 11 mainly includes the following functional modules: a Serial Interface Engine (SIE) module 112, a Physical (PHY) module 111, a Cyclic Redundancy Check (CRC) module 113, a Special Function Register (SFR) 116, a First Input First Output (FIFO) module 114, and a CLOCK module (CLOCK) 115.

In a common chip USB module self-testing method, as shown in fig. 1, a chip USB module 11 is located inside a chip and is a USB module to be tested;

units

13, 14 are PADs, through which USB data is transmitted externally; unit 12 is a tester that generates and receives USB test data signals. In fig. 1, a testing machine 12 generates a USB test data signal according to a USB protocol standard, and transmits the USB test data signal to a chip USB module through

pins

13 and 14, and the testing machine 12 receives a test data signal returned from the chip USB module, and tests the quality of the chip USB module by determining the returned test data, so as to detect a defective USB module.

Because the tester 12 generates the USB test data signal according to the USB protocol standard, the width of each serial data bit in the USB test data is fixed, and the requirement for the accuracy of the clock frequency is high. For example, the high speed HS is. + -. 500ppm, the fast FS is 2500ppm and the low speed LS is 15000 ppm. For LS transmission, the data bit width is 666.67ns, and the corresponding clock frequency is 6 MHz; for FS transmission, the data bit width is 83.33ns, and the corresponding clock frequency is 48 MHz; for HS transmission, the data bit width is 10.42ns, and the corresponding clock frequency is 384 MHz. If the tester 12 is used to directly send the standard baud rate test data to test the USB module, the test data is difficult to be correctly received by the chip USB module at the device side due to the difference between the internal and external clock frequencies. If the tester 12 sends test data at the frequency of the oscillator inside the chip, the chip is not easy to implement, and the clock frequency inside the chip may not be tested accurately in the test stage and does not reach the standard frequency, so that the test is more difficult to implement, the detection accuracy of the USB module of the chip is not high, and the purpose of detecting a bad USB module cannot be achieved; and because the test circuit is formed by an external tester, the test circuit is more complex and the cost is higher.

Disclosure of Invention

The embodiment of the invention aims to provide a self-testing device and a self-testing method of a chip USB module, which can realize that the chip USB module completes self-testing in the chip by adding a self-testing circuit in the chip, and does not need an external testing machine to assist in testing, thereby reducing the cost.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions: a self-test apparatus of a chip USB module, the apparatus comprising: the system comprises a special function register interface, a serial interface engine module, a PHY module and a self-test circuit; wherein:

the special function register interface is connected with the serial interface engine module and is used for providing a starting signal for the serial interface engine module;

the serial interface engine module is respectively connected with the PHY module and the self-test circuit, and is used for starting a chip USB test mode according to the starting signal and controlling the sending and receiving of USB data, and the serial interface engine module comprises: sending preset test data to the PHY module, and receiving decoded self-test data from the PHY module;

the PHY module is connected to the USB bus, connected with the self-test circuit and used for receiving the preset test data, coding the preset test data according to a preset coding algorithm and sending the coded test data to the USB bus; the USB interface engine module is used for receiving self-test data returned after passing through the self-test circuit from the USB bus, decoding the self-test data according to a preset decoding algorithm and sending the decoded self-test data to the serial interface engine module;

and the self-test circuit is connected to the USB bus and used for outputting the coded test data output by the PHY module to the USB bus to form self-test data which is then returned to the PHY module.

Optionally, the preset test data includes any data that conforms to a data length within a maximum USB packet length.

Optionally, the preset test data includes special data of 5 bytes in total length of several consecutive bits 1.

Optionally, the apparatus further includes a cyclic redundancy check module, where the cyclic redundancy check module is connected to the serial interface engine module and the PHY module, respectively, and is configured to generate a cyclic redundancy check code, and send the cyclic redundancy check code to the serial interface engine module and the PHY module, respectively.

Optionally, the PHY module comprises TX transmit circuitry and RX receive circuitry; wherein:

the TX transmitting circuit is respectively connected with the serial interface engine module and the self-testing circuit and is used for receiving the preset test data and the cyclic redundancy check code; and the USB interface is used for outputting the coded test data to a USB bus;

and the RX receiving circuit is connected with the serial interface engine module and the self-testing circuit and is used for receiving self-testing data returned after passing through the self-testing circuit from a USB bus and sending the decoded self-testing data to the serial interface engine module and the cyclic redundancy check module.

Optionally, the PHY module is configured to receive the preset test data, encode the preset test data according to a preset encoding algorithm, and send the encoded test data to a USB bus; the method comprises the following steps:

the PHY module receives the preset test data and the cyclic redundancy check code through a TX (transmission X) transmission circuit, firstly carries out bit insertion operation, and inserts a0 after every 6 continuous 1; and then coding the bit-inserted data according to a preset coding algorithm to form coded test data, converting the coded test data into differential voltage and differential signals of a USB bus standard, and transmitting the differential voltage and the differential signals to the USB bus through a TX (transmission X) transmitting circuit.

Optionally, the PHY module is configured to receive self-test data returned after passing through the self-test circuit from the USB bus, decode the self-test data according to a preset decoding algorithm, and send the decoded self-test data to the serial interface engine module; the method comprises the following steps:

the PHY module receives differential voltage and differential signals formed by self-test data returned by the self-test circuit on the USB bus through an RX receiving circuit, decodes the differential voltage and the differential signals into standard digital signals according to a preset decoding algorithm, deletes one 0 for every 6 continuous 1 of the data signals, restores to form decoded self-test data, and sends the decoded self-test data to the serial interface engine module and the cyclic redundancy check module through the RX receiving circuit.

Optionally, the apparatus further includes a memory, connected to the serial interface engine module, for storing the decoded self-test data received by the serial interface engine module from the PHY module.

Optionally, the apparatus further includes a clock module, connected to the serial interface engine module, and configured to provide a working clock frequency for the serial interface engine module.

Optionally, the self-test circuit includes a switch loop, and the switch loop is connected to the PHY module, and is configured to form self-test data from the encoded test data output by the PHY module to the USB bus, and then return the self-test data to the input end of the PHY module.

Optionally, the switch loops are respectively connected with a TX transmitting circuit and an RX receiving circuit of the PHY module; and the switch loop forms self-test data by the coded test data output by the PHY module to the USB bus through the TX transmission circuit, and then returns to the RX receiving circuit of the PHY module.

In order to solve the above technical problems, embodiments of the present invention further provide the following technical solutions: a self-test method of a chip USB module is applied to a self-test device of the chip USB module in any embodiment of the invention, and the device comprises: the USB interface test system comprises a special function register interface, a serial interface engine module, a PHY module and a self-test circuit, wherein the serial interface engine module is respectively connected with the special function register interface, the PHY module and the self-test circuit; wherein the method comprises the following steps:

the special function register interface provides a starting signal for the serial interface engine module;

the serial interface engine module starts a chip USB test mode according to the starting signal and sends preset test data to the PHY module;

the PHY module receives the preset test data, encodes the preset test data according to a preset encoding algorithm, and sends the encoded test data to a USB bus;

the self-test circuit outputs the coded test data output by the PHY module to the USB bus to form self-test data, and the self-test data is connected back to the PHY module;

the PHY module receives self-test data returned after passing through the self-test circuit from the USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the decoded self-test data to the serial interface engine module;

and the serial interface engine module receives the decoded self-test data from the PHY module.

Compared with the prior art, the self-testing device and the self-testing method of the chip USB module provided by the embodiment of the invention provide the starting signal for the SIE module through the SFR interface; the SIE module starts a chip USB test mode according to the starting signal and sends preset test data to the PHY module; the PHY module receives preset test data sent by the SIE module, encodes the preset test data according to a preset encoding algorithm, and sends the encoded test data to a USB bus; the self-test circuit outputs the coded test data output by the PHY module to the USB bus to form self-test data, and the self-test data is connected back to the PHY module; the PHY module receives self-test data returned after passing through the self-test circuit from a USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the decoded self-test data to the SIE module; the SIE module receives decoded self-test data from the PHY module. Therefore, the chip USB module can complete self-test in the chip without an external test machine, and the cost is reduced; the chip internal test circuit is extremely simple to start, and only one starting signal needs to be given from the outside; the judgment result is simple, only need to judge whether the decoded self-test data in the SIE module is matched with the preset self-test data, if not, the manufacture of the USB module circuit has defects and the circuit has errors, and the USB module is marked as a defective product; the self-test circuit added in the chip is simple to realize and does not need a complex additional circuit; the self-test device has no relation with the clock frequency of the chip, the test can be completed before the clock calibration of the chip, and the very accurate clock does not need to be provided. Therefore, the technical problems that the clock frequency in the existing chip is not the standard frequency, the test circuit is complex and the like are solved.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic structural diagram of a self-test apparatus of a chip USB module provided in the prior art.

Fig. 2 is a schematic structural diagram of a chip USB module provided in the prior art.

Fig. 3 is a schematic structural diagram of a self-test apparatus of a chip USB module according to the present invention.

Fig. 4 is a schematic diagram of a transmission flow of a CONTROL transmission (CONTROL) mode of a USB bus according to the present invention.

Fig. 5 is a schematic diagram of a transmission flow of a BULK transfer (BULK) method of the USB bus according to the present invention.

FIG. 6 is a schematic diagram illustrating a transmission flow of an INTERRUPT transmission (INTERRUPT) method of a USB bus according to the present invention.

Fig. 7 is a schematic diagram of a transmission flow of an ISOCHRONOUS (ISOCHRONOUS) mode of a USB bus according to the present invention.

Fig. 8 is a schematic diagram of forced insertion of a '0' when 6 '1's are continuously present as specified by the USB protocol.

Fig. 9 is a schematic flow chart of a self-test method of a chip USB module according to the present invention.

Detailed Description

In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. As used in this specification, the terms "upper," "lower," "inner," "outer," "bottom," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the invention and simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

Universal Serial Bus (USB) is a common Serial interface, has the advantages of fast speed and plug-in capability, and is widely used in computers, mobile phones, and various devices.

USB2.0 contains 3 different operating speeds LS, FS and HS. The difference between LS and FS is that the states of DP and DM are opposite, except for the difference in speed. The difference between FS and HS is the clock speed. The data transmission modes of the three modes are the same, especially self-sending and self-receiving, and the data transmission modes are the same and have no relation with the high and low levels of DP and DM and the speed of the working clock.

The USB bus includes 4 transmission modes, namely, CONTROL transmission (CONTROL), BULK transmission (BULK), INTERRUPT transmission (INTERRUPT), and ISOCHRONOUS transmission (ISOCHRONOUS). Fig. 4 shows a transmission flow of a CONTROL transmission (CONTROL) mode, fig. 5 shows a transmission flow of a BULK transmission (BULK) mode, fig. 6 shows a transmission flow of an INTERRUPT transmission (INTERRUPT) mode, and fig. 7 shows a transmission flow of an ISOCHRONOUS transmission (ISOCHRONOUS) mode.

As known from the USB protocol, the 4 transmissions are accomplished by data transmission in two different directions, i.e. the gray boxes in fig. 4-7 represent transmission from the host side to the device side, and the white boxes represent transmission from the device side to the host side. Whatever the transmission, it is initially initiated by the host side (e.g., PC, TESTER, etc.) (as shown in the gray portion of fig. 4-7).

In the USB protocol, the data in each block shown in fig. 4-7 has a strict value and transmission direction, and if the data is violated, the transmission will be in error. When an error occurs, the host end and the equipment end have respective processing modes, so that the two sides can be ensured to recover from the error state.

When the host end and the device end transmit data, the host end firstly sends a TOKEN data packet (SETUP, OUT, IN, etc.), and according to the data packet, the transmitter and the receiver agree on what transmission direction the second data is, and a third data packet (ACK, NAK, etc.). The host side and the device side agree on a basic format for transmission when transmitting data, and two most basic formats are commonly used as follows:

transmission from the host side to the device side: an OUT packet, a DATA0/1 packet, and an ACK packet;

transmission from the device side to the host side: IN packet, DATA0/1 packet, ACK packet.

Almost all data transfer is accomplished by both types of transfer, i.e., all data transfer of the USB is accomplished by the same circuit. In the test of the chip USB module, the chip USB module is used as a device side. The chip test is to detect the defective products through simple and basic operations.

The DP/DM of the USB bus is a differential encoding, and employs an NRZI (No Return Zero-Inverse) encoding scheme. Send data bit '0', DP/DM is to change state; the data bit '1' is transmitted, and the DP/DM remains in the original state. At this time, there is a problem in that if the '1' sequence is always transmitted, the USB bus is always still, resulting in another problem. The USB protocol thus provides that a '0' is forced to be inserted when 6 '1's occur in succession. As shown in fig. 8. When decoding, decoding is carried out in reverse.

In one embodiment, as shown in fig. 3, the present invention provides a self-test apparatus for a chip USB module, the apparatus comprising: an SFR (Special Function Register) Interface 316, an SIE (Serial Interface Engine) module 312, a PHY (Physical) module 31, and a self-test circuit 35; wherein:

the SFR interface 316, connected to the SIE module 312, is configured to provide a start signal to the SIE module 312; wherein the start signal comes from one of the designated bits of the special function register SFR or a signal from an external device, for example, a start signal given from the CPU.

The SIE module 312 is connected to the SFR interface 316, the PHY module 31, and the self-test circuit 35, respectively, and configured to start a chip USB test mode according to the start signal, and control sending and receiving of USB data, including: sending preset test data to the PHY module 31, and receiving decoded self-test data from the PHY module 31.

The PHY module 31 is connected to the USB bus, connected to the self-test circuit 35, and configured to receive preset test data sent by the SIE module 312, encode the preset test data according to a preset encoding algorithm, and send the encoded test data to the USB bus; and a module 312 for receiving the self-test data returned after passing through the self-test circuit 35 from the USB bus, decoding the self-test data according to a preset decoding algorithm, and sending the decoded self-test data to the SIE module.

The self-test circuit 35 is connected to the USB bus, connected to the PHY module 31, and configured to form self-test data from the encoded test data output by the PHY module 31 to the USB bus, and then return the self-test data to the PHY module 31.

In this embodiment, the start signal is provided to the SIE module through the SFR interface; the SIE module starts a chip USB test mode according to the starting signal and sends preset test data to the PHY module; the PHY module receives preset test data sent by the SIE module, encodes the preset test data according to a preset encoding algorithm, and sends the encoded test data to a USB bus; the self-test circuit outputs the coded test data output by the PHY module to the USB bus to form self-test data, and the self-test data is connected back to the PHY module; the PHY module receives self-test data returned after passing through the self-test circuit from a USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the decoded self-test data to the SIE module; the SIE module receives decoded self-test data from the PHY module. Therefore, the chip USB module can complete self-test in the chip without an external test machine, and the cost is reduced; the chip internal test circuit is extremely simple to start, and only one starting signal needs to be given from the outside; the judgment result is simple, only need to judge whether the decoded self-test data in the SIE module is matched with the preset self-test data, if not, the manufacture of the USB module circuit has defects and the circuit has errors, and the USB module is marked as a defective product; the self-test circuit added in the chip is simple to realize and does not need a complex additional circuit; the self-test device has no relation with the clock frequency of the chip, the test can be completed before the clock calibration of the chip, and the very accurate clock does not need to be provided. Therefore, the technical problems that the clock frequency in the existing chip is not the standard frequency, the test circuit is complex and the like are solved.

In one embodiment, as shown in fig. 3, the SIE module 312, respectively connected to the SFR interface 316, the PHY module 31, and the self-test circuit 35, is configured to start a chip USB test mode according to the start signal, and control transmission and reception of USB data, including: sending preset test data to the PHY module 31, and receiving decoded self-test data from the PHY module 31.

The SIE module 312 is connected to the PHY module 31 through a UTMI (USB 2.0 driver macro cell Interface, USB2.0 high speed device detection protocol) Interface.

The preset test data comprises any data which accords with the data length within the maximum value of the USB data packet length.

Preferably, the preset test data includes a total length of 5 bytes of special data of several consecutive bits 1.

In the embodiment, regular preset test data are preset, so that a test developer can easily judge whether the data is correct or incorrect, CRC can be well tested, and in-place insertion operation can also be detected.

According to the protocol of the USB, the PID of each data packet follows a certain sequence. The invention relates to a self-testing device of a chip USB module, which is mainly used for USB testing, and the USB module can not only send data, but also receive data at the same time. Thus, in test mode, there is no need to fully comply with the USB protocol, i.e. regardless of the specific values and meanings of the PID. The transmitting circuit only transmits data out, and the receiving circuit only receives data in and stores the data in FIFO (or RAM). Accordingly, corresponding modifications are required in the SIE module 312, and in test mode, the sending and receiving of data by the SIE module 312 can be performed simultaneously, and the undesired PID values can be ignored.

According to the above description, the following modifications are required in the SIE module 312 to achieve the purpose of self-testing the chip USB module:

1) the chip USB module is originally used as an equipment end, and does not need to actively initiate a transmission according to a USB protocol. In the test mode, a send state machine is added to the SIE module 312 to invoke the send circuitry of the SIE module 312 to actively initiate a transfer, including the SETUP transfer and the DATA0 transfer, and finally receive HANDSHAKE. Meanwhile, the receiving state machine of the SIE module 312 invokes the receiving circuitry of the SIE module 312, which can automatically receive the DATA received from DATA0, save it to FIFO (or RAM), and finally send it back HANDSHAKE. The two state machines, the transmit state machine and the receive state machine, may operate simultaneously.

2) The UTMI interface between the SIE module 312 and the PHY module 31 is modified accordingly to allow simultaneous transmission and reception of data.

In one embodiment, as shown in fig. 3, the apparatus further includes a Cyclic Redundancy Check (CRC) module 313, where the CRC module 313 is connected to the SIE module 313 and the PHY module 31, respectively, for generating CRC Check codes, and sending the CRC Check codes to the SIE module 313 and the PHY module 31, respectively. The CRC code is mainly used for being accessed by a CPU (central processing unit), so that the CPU can analyze the state of the USB data.

The CRC check code with two byte lengths received from the USB bus can conveniently judge whether the decoded self-test data is correct, if the received CRC check code is not matched with the preset CRC check code, the manufacture of the tested USB module circuit is defective, the circuit is wrong, and the tested USB module is marked as a defective product. Therefore, the judgment result is simple, and only the CRC code received from the USB bus needs to be judged whether to be matched with the preset CRC code.

In one embodiment, as shown in fig. 3, the PHY module 31 includes TX transmit circuitry 310 and RX receive circuitry 311.

The TX transmitting circuit 310 is respectively connected to the SIE module 312 and the self-test circuit 35, and is configured to enable the PHY module 31 to receive the preset test data sent by the SIE module 312 and the CRC check code sent by the CRC module 313 through the TX transmitting circuit 310; and for outputting the encoded test data onto the USB bus.

Specifically, the PHY module 31 is configured to receive preset test data sent by the SIE module 312, encode the preset test data according to a preset encoding algorithm, and send the encoded test data to a USB bus; the method comprises the following steps: the PHY module 31 receives the preset test data sent by the SIE module 312 and the CRC check code sent by the CRC module 313 through the TX sending circuit 310, performs bit insertion operation first, and inserts a0 after every 6 consecutive 1 s; then, the bit-inserted data is encoded according to a preset encoding algorithm to form encoded test data, and the encoded test data is converted into differential voltage and differential signal of the USB bus standard and transmitted to the USB bus through the TX transmitting circuit 310.

The RX receiving circuit 311 is connected to the SIE module 312 and the self-test circuit 35, and is used for the PHY module 31 to receive the self-test data returned from the USB bus after passing through the self-test circuit 35 via the RX receiving circuit 311, and to send the decoded self-test data to the SIE module 312 and the CRC module 313 via the RX receiving circuit 311.

Specifically, the PHY module 31 is configured to receive self-test data returned after passing through the self-test circuit 35 from the USB bus, decode the self-test data according to a preset decoding algorithm, and send the decoded self-test data to the SIE module 312; the method comprises the following steps:

the PHY module 31 receives, through the RX receiving circuit 311, a differential voltage and a differential signal formed by self-test data returned on the USB bus after passing through the self-test circuit 35, decodes the differential voltage and the differential signal into standard digital signals according to a preset decoding algorithm, deletes one 0 for every 6 consecutive 1 of the data signals, restores to form decoded self-test data, and sends the decoded self-test data to the SIE module 312 and the CRC module 313 through the RX receiving circuit 311.

Preferably, the preset encoding algorithm and the preset decoding algorithm include an NRZI (No Return Zero-Inverse coding) encoding algorithm.

In this embodiment, the PHY module 31 is composed of a TX transmitting circuit 310 and an RX receiving circuit 311 in two transmission directions, and during testing, the chip USB module is used as an output signal of the device side and is connected back to the input terminal of the device side, so that the chip USB module serves as both the host side and the device side. The hardware circuit in the chip USB module can be effectively tested by simply and effectively sending fixed special data. Since the same clock is used for the transmission circuit 310 and the reception circuit 311 of the PHY module 31, the reception data can be correctly transmitted regardless of whether the clock frequency is deviated or not. Therefore, the self-test device of the invention has no relation with the clock frequency of the chip, the test can be completed before the clock calibration of the chip, and the very accurate clock does not need to be provided. Therefore, the problem that the clock frequency in the existing chip is not the standard frequency is solved.

In one embodiment, as shown in fig. 3, the apparatus further comprises a memory 314, wherein the memory 314 is connected to the SIE module 312 for storing the decoded self-test data received by the SIE module 312 from the PHY module 31; the memory space of the memory 314 is required to accommodate the longest data packet of USB and 2-byte CRC check code.

The Memory 314 may be implemented by a FIFO (First Input First Output) circuit, or may be implemented by a RAM (Random Access Memory).

In this embodiment, when receiving the decoded self-test data, the SIE module writes the decoded self-test data into the FIFO (or RAM) while calculating the CRC check code, where the decoded self-test data includes two-byte CRC check codes received from the USB bus. The CRC check code can conveniently judge whether the decoded self-test data is correct or not. If the decoded self-test data and CRC check code saved in FIFO (or RAM) by the SIE module are not matched with the preset self-test data and CRC check code, the manufacture of the tested USB module circuit is defective, the circuit is wrong, and the tested USB module is marked as a defective product. Therefore, the judgment result is simple, and only the judgment of whether the decoded self-test data and the CRC check code stored in the FIFO (or the RAM) by the SIE module are matched with the preset self-test data and the preset CRC check code is needed.

In one embodiment, as shown in FIG. 3, the apparatus further comprises a CLOCK (CLOCK) module 315, wherein the CLOCK module 315 is coupled to the SIE module 312 for providing an operating CLOCK frequency to the SIE module 312.

In one embodiment, as shown in fig. 3, the self-test circuit 35 includes a switch loop, and the switch loop is connected to the PHY module 31, and configured to form self-test data from encoded test data output by the PHY module 31 onto the USB bus, and then connect the self-test data back to the input terminal of the PHY module 31. Specifically, the method comprises the following steps:

the switch loops are respectively connected with the TX transmitting circuit 310 and the RX receiving circuit 311 of the PHY module 31; the coded test data output from the PHY module 31 to the USB bus by the TX transmitting circuit 310 forms self-test data, and then passes through the switch loop to be returned to the RX receiving circuit 311 of the PHY module 31.

Preferably, the switching circuit comprises a selector (MUX). The selector is connected to the PHY module 31, and is configured to form self-test data from the encoded test data output by the PHY module 31 to the USB bus, and then return the self-test data to the input end of the PHY module 31. Specifically, the method comprises the following steps: the selector is respectively connected with the TX transmitting circuit 310 and the RX receiving circuit 311 of the PHY module 31; the coded test data output from the PHY module 31 to the USB bus by the TX transmitting circuit 310 forms self-test data, and then passes through the selector, and then returns to the RX receiving circuit 311 of the PHY module 31.

In this embodiment, a self-test circuit is added inside the chip, and the self-test circuit is implemented by using a switch loop, specifically, by using a selector MUX, so that the self-test circuit is simple to implement, and does not need a complex additional circuit, thereby reducing the cost. Therefore, the technical problems that the test circuit is complex and the like because an external test machine is required to form a test circuit in the prior art are solved.

In one embodiment, the CRC module 312 includes CRC circuitry as in a self-test device of a chip USB module; the SIE module 313 includes a force insert 0 circuit that acts on more than 6 consecutive data bits "1" of the predetermined test packet to cause a force insert 0. Therefore, when the preset test data is selected, both the CRC circuit and the forced insertion 0 circuit can be detected relatively well.

In the actual chip USB module, a set of special data such as 0xFF, and 0x00 is selected in order to generate as many data bits "1" as possible, and the CRC circuit can always perform an operation.

Meanwhile, the above-mentioned group of special data may have more than 6 consecutive data bits "1", which may cause the transmitting circuit that forcibly inserts 0 to operate, and the circuit that discards 0 to operate at the time of reception.

The above group of special data is operated by the CRC module of the USB, and a CRC value with a length of two bytes is obtained: 0x8E, 0x 3F.

If the two circuits of the above-described CRC circuit and the circuit of the forced insertion 0 are made defective, there is a problem in receiving the stored data or CRC check code, and it can be found in time.

Under the above group of special data, the data transmitted on the USB bus is:

and

and

based on the same concept, in an embodiment, as shown in fig. 9, the present invention provides a self-test method for a chip USB module, which is applied to a self-test apparatus for a chip USB module according to any of the above embodiments, the apparatus includes: the system comprises an SFR interface, an SIE module, a PHY module and a self-testing circuit, wherein the SIE module is respectively connected with the SFR interface, the PHY module and the self-testing circuit, the PHY module is connected to a USB bus and is connected with the self-testing circuit, and the self-testing circuit is connected to the USB bus; wherein the method comprises the following steps:

s1, the SFR interface provides a starting signal for the SIE module; wherein the start signal comes from one of the designated bits of the special function register SFR or a signal from an external device, for example, a start signal given from the CPU.

S2, the SIE module starts a chip USB test mode according to the starting signal and sends preset test data to the PHY module;

s3, the PHY module receives preset test data sent by the SIE module, codes the preset test data according to a preset coding algorithm, and sends the coded test data to a USB bus;

and S4, the self-test circuit outputs the coded test data output by the PHY module to the USB bus to form self-test data, and the self-test data is returned to the PHY module.

S5, the PHY module receives self-test data returned after passing through the self-test circuit from the USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the decoded self-test data to the SIE module;

and S6, the SIE module receives the decoded self-test data from the PHY module.

In this embodiment, the start signal is provided to the SIE module through the SFR interface; the SIE module starts a chip USB test mode according to the starting signal and sends preset test data to the PHY module; the PHY module receives preset test data sent by the SIE module, encodes the preset test data according to a preset encoding algorithm, and sends the encoded test data to a USB bus; the self-test circuit outputs the coded test data output by the PHY module to the USB bus to form self-test data, and the self-test data is connected back to the PHY module; the PHY module receives self-test data returned after passing through the self-test circuit from a USB bus, decodes the self-test data according to a preset decoding algorithm, and sends the decoded self-test data to the SIE module; the SIE module receives decoded self-test data from the PHY module.

In one embodiment, in step S2, the preset test data includes any data that conforms to a data length within a maximum USB packet length.

Preferably, the predetermined test data includes 5 bytes of special data with consecutive 1 s and consecutive 0 s.

In one embodiment, the apparatus further comprises a Cyclic Redundancy Check (CRC) module coupled to the SIE module and the PHY module, respectively.

The method further comprises the following steps: the CRC module generates CRC check codes which are respectively sent to the SIE module and the PHY module. The CRC code is mainly used for being accessed by a CPU (central processing unit), so that the CPU can analyze the state of the USB data.

In one embodiment, the PHY module includes TX transmit circuitry and RX receive circuitry.

The TX transmitting circuit is respectively connected with the SIE module and the self-test circuit and is used for the PHY module to receive the preset test data sent by the SIE module and the CRC check code sent by the CRC module through the TX transmitting circuit; and for outputting the encoded test data onto the USB bus.

Specifically, in step S3, the PHY module receives preset test data sent by the SIE module, encodes the preset test data according to a preset encoding algorithm, and sends the encoded test data to the USB bus; the method comprises the following steps:

the PHY module receives the preset test data sent by the SIE module and the CRC check code sent by the CRC module through a TX sending circuit, firstly carries out bit insertion operation, and inserts a 1 after every 6 continuous 0 s; and then coding the bit-inserted data according to a preset coding algorithm to form coded test data, converting the coded test data into differential voltage and differential signals of a USB bus standard, and transmitting the differential voltage and the differential signals to the USB bus through a TX (transmission X) transmitting circuit.

The RX receiving circuit is connected with the SIE module and the self-test circuit, and is used for the PHY module to receive self-test data returned from a USB bus after passing through the self-test circuit through the RX receiving circuit and send the decoded self-test data to the SIE module and the CRC module through the RX receiving circuit.

Specifically, in step S5, the PHY module is configured to receive self-test data returned after passing through the self-test circuit from the USB bus, decode the self-test data according to a preset decoding algorithm, and send the decoded self-test data to the SIE module; the method comprises the following steps:

the PHY module receives differential voltage and differential signals formed by self-test data returned by the self-test circuit on a USB bus through an RX receiving circuit, the differential voltage and the differential signals are decoded into standard digital signals according to a preset decoding algorithm, then one 1 is deleted for every 6 continuous 1 of the data signals, the decoded self-test data is recovered and formed, and the decoded self-test data is sent to the SIE module and the CRC module through the RX receiving circuit.

Preferably, the preset coding algorithm comprises an NRZI (No Return Zero-Inverse coding) coding algorithm.

In this embodiment, the PHY module is composed of a TX transmitting circuit and an RX receiving circuit in two transmission directions, and during testing, the chip USB module is used as an output signal of the device end and is connected back to the input end of the device end, so that the chip USB module serves as both the host end and the device end. The hardware circuit in the chip USB module can be effectively tested by simply and effectively sending fixed special data. Since the same clock is used for the transmission circuit and the reception circuit of the PHY module, the transmission and reception data can be correctly transmitted and received regardless of whether the clock frequency is deviated or not. Therefore, the self-test device of the invention has no relation with the clock frequency of the chip, the test can be completed before the clock calibration of the chip, and the very accurate clock does not need to be provided. Therefore, the problem that the clock frequency in the existing chip is not the standard frequency is solved.

In one embodiment, the apparatus further comprises a memory coupled to the SIE module.

The method further comprises the following steps: the memory stores the decoded self-test data received by the SIE module from the PHY module; the memory space of the memory is required to be capable of accommodating the longest data packet of the USB and the CRC check code with the length of 2 bytes.

The Memory may be implemented by a FIFO (First Input First Output) circuit, or may be implemented by a RAM (Random Access Memory).

In one embodiment, the apparatus further comprises a CLOCK (CLOCK) module coupled to the SIE module for providing an operating CLOCK frequency to the SIE module.

In one embodiment, the self-test circuit includes a switch loop, and the switch loop is connected to the PHY module, and configured to form self-test data from encoded test data output by the PHY module onto the USB bus, and then return the self-test data to the input terminal of the PHY module. Specifically, the method comprises the following steps:

the switch loop is respectively connected with a TX transmitting circuit and an RX receiving circuit of the PHY module; and the coded test data output by the PHY module to the USB bus through the TX transmitting circuit forms self-test data, and then the self-test data passes through the switch loop and is connected back to the RX receiving circuit of the PHY module.

Preferably, the switching circuit comprises a selector (MUX). The selector is connected with the PHY module and is used for outputting the coded test data output by the PHY module to the USB bus to form self-test data, and then the self-test data is connected back to the input end of the PHY module. Specifically, the method comprises the following steps: the selector is respectively connected with a TX transmitting circuit and an RX receiving circuit of the PHY module; and the coded test data output by the PHY module to the USB bus through the TX transmission circuit forms self-test data, and then the self-test data passes through the selector and is connected back to the RX receiving circuit of the PHY module.

It should be noted that the method embodiment and the apparatus embodiment belong to the same concept, and specific implementation processes thereof are described in the apparatus embodiment, and technical features in the apparatus embodiment are correspondingly applicable in the method, and repeated parts are not described again.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device for self-test of a chip USB module, the device comprising: the system comprises a special function register interface, a serial interface engine module, a PHY module and a self-test circuit; wherein:

2. The apparatus of claim 1, wherein the predetermined test data comprises any data that conforms to a data length within a maximum USB packet length.

3. The apparatus of claim 2, wherein the predetermined test data comprises a total length of 5 bytes of special data of consecutive bit 1.

4. The apparatus of claim 1, further comprising a cyclic redundancy check module, wherein the cyclic redundancy check module is connected to the serial interface engine module and the PHY module, respectively, for generating cyclic redundancy check codes, which are sent to the serial interface engine module and the PHY module, respectively.

5. The apparatus of claim 4, wherein the PHY module comprises TX transmit circuitry and RX receive circuitry; wherein:

6. The apparatus of claim 5, wherein the PHY module is configured to receive the predetermined test data, encode the predetermined test data according to a predetermined encoding algorithm, and send the encoded test data to a USB bus; the method comprises the following steps:

7. The device of claim 5, wherein the PHY module is configured to receive self-test data returned after passing through the self-test circuit from the USB bus, decode the self-test data according to a preset decoding algorithm, and send the decoded self-test data to the serial interface engine module; the method comprises the following steps:

8. The apparatus of claim 7, further comprising a memory coupled to the serial interface engine module for storing the decoded self-test data received by the serial interface engine module from the PHY module.

9. The apparatus of claim 1, further comprising a clock module coupled to the serial interface engine module for providing an operating clock frequency to the serial interface engine module.

10. The apparatus of claim 5, wherein the self-test circuit comprises a switch circuit, and the switch circuit is connected to the PHY module, and configured to form the encoded test data output by the PHY module onto the USB bus into self-test data, which is then returned to the input of the PHY module.

11. The apparatus of claim 10, wherein the switching loops are respectively connected to TX transmit circuitry and RX receive circuitry of the PHY module; and the switch loop forms self-test data by the coded test data output by the PHY module to the USB bus through the TX transmission circuit, and then returns to the RX receiving circuit of the PHY module.

12. A self-test method of a chip USB module, which is applied to the self-test apparatus of a chip USB module according to any one of claims 1 to 11, the apparatus comprising: the USB interface test system comprises a special function register interface, a serial interface engine module, a PHY module and a self-test circuit, wherein the serial interface engine module is respectively connected with the special function register interface, the PHY module and the self-test circuit; wherein the method comprises the following steps: