CN111367850A - Rapid communication method between FPGA and MCU - Google Patents

Abstract

The invention discloses a rapid communication method between an FPGA and an MCU, which comprises the following steps that the FPGA and the MCU are connected through 2 data lines, the MISO direction is configured from the FPGA to the MCU, and the MOSI is from the MCU to the FPGA; the FPGA receives a coded data code stream sent by the MCU, recovers message contents from the code stream, then is used as a slave machine of the SPI interface, and sends data to be sent to the MCU through the SPI interface; and the MCU reads the response data of the FPGA through the MISO interface. By adopting the method, the FPGA and the MCU can complete communication by only using 2 data lines, and the communication speed can reach hundreds of Mbps at the fastest speed.

Description

Rapid communication method between FPGA and MCU

Technical Field

The invention relates to a rapid communication method between an FPGA and an MCU, belonging to the technical field of industrial control and embedding.

Background

FPGAs (field programmable gate arrays) have been increasingly used in the fields of industrial control, communication, image processing, etc. due to their hardware programmability, parallel processing, etc.; in the application of the FPGA, data interaction with the FPGA is often required, and the method is used for operations such as configuration, parameter setting, data import and export of an FPGA chip, and the number of interface signals for performing data interaction is required to be as small as possible, and an asynchronous serial interface (UART) is often used as an interface for chip debugging, monitoring and the like due to the characteristics of simple protocol, few required data lines and the like, but due to the characteristics of UART coding and protocol, the speed of the UART interface is limited by the frequency of a decoding clock, the actual transmission speed is limited, even if the fastest MCU is an UART interface with the speed of about 10Mbps, the UART interface is also applicable to the FPGA, and in the application requiring a large amount of data transmission, particularly for the FPGA chip, the transmission speed is limited, the advantages of the FPGA chip cannot be exerted, and the communication.

The SPI interface is a common synchronous serial interface, the speed of the SPI interface is far greater than that of a UART, the bandwidth of 50Mhz can be achieved in the MCU with the current general performance, and the high-end MCU can even reach hundreds of Mhz; unlike UARTs, an SPI interface requires at least 3 signal lines to achieve bidirectional communication, which limits its application to some special applications, for example, industrial communication fibers are generally paired to transmit and receive signals, and communication using UARTs is very suitable but SPI communication cannot be used.

Although the SPI is limited by its own characteristics and cannot use 2 data lines for duplex communication, if the SPI is matched with the programmable hardware characteristics of the FPGA and then processed in software, the SPI can be used for fast communication between the FPGA and the MCU.

Disclosure of Invention

The invention aims to provide a rapid communication method between an FPGA and an MCU, which can realize duplex communication by only using 2 data lines of an SPI and fully exert the speed advantage of the SPI.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a method for rapid communication between an FPGA and an MCU comprises the following steps:

(1) the MCU configures the SPI peripheral equipment, configures the SPI transmission word length to be 10bit, and the polarity of an idle clock is high level, and samples at the second edge of the SCK;

(2) the MCU calculates the check code of the data packet to be transmitted, and the check code is placed at the end of the data packet to generate an original data packet;

(3) encoding the original data packet into a 10bit code by 8B/10B;

(4) adding a packet head and a packet tail to a 10-bit data packet, and packaging into an encoded data packet;

(5) the MCU sends the coded data packet to the FPGA through the MOSI; the FPGA successfully receives the message, decodes the message into original data through the 8B/10B message decoding and receiving module, prepares corresponding response data according to the command of the data packet, starts the enhanced SPI slave module and waits for the MCU to read;

(6) after the coded data packet is sent, the MCU checks the level of the MISO and judges the working state of the FPGA according to the level of the MISO;

(7) performing handshake operation between the FPGA and the MCU according to the working state of the FPGA, and transmitting response data by the FPGA;

(8) the MCU reconfigures the SPI peripheral, configures the character length of SPI transmission to be 8bit, and the polarity of an idle clock is high level, and samples at the second edge of the SCK;

(9) the MCU reads response data of the FPGA through the MISO;

(10) and (4) jumping to the step (1) and starting to carry out next transmission.

Further comprises the step of connecting the FPGA and the MCU through 2 data lines,

configuring MISO as a host input of the SPI and outputting signals from a slave;

configuring a host with MOSI as SPI to send and a slave to receive signals;

the MCU is a host computer of the SPI, and the FPGA is a slave computer of the SPI.

Furthermore, the FPGA comprises an 8B/10B message decoding and receiving module, a command interpretation and execution module, an enhanced SPI slave module and an external interface module;

the 8B/10B message decoding and receiving module is used for receiving the code stream sent on the MOSI signal line, carrying out 8B/10B decoding on the code stream and checking the correctness of the message;

the command interpretation and execution module is used for analyzing the message decoded by the 8B/10B message decoding and receiving module to obtain a command and parameters and preparing response data;

the enhanced SPI slave module is used for sending response data prepared by the command interpretation and execution module to the external interface module;

the external interface module is used for transmitting data to the MCU through the MISO.

Further, the adding a header and a trailer to the 10-bit data packet, and packing into an encoded data packet, includes:

special characters K28.7 and K29.7 coded by 8B/10B are used as packet headers of the data packets, and special characters K28.7 and K27.7 are used as packet tails of the data packets;

the high order of 10B code is complemented with 0 to obtain the code of the header as 0B0000_0000_0111_1100 and 0B0000_0000_0101_1101, and the code of the tail as 0B0000_0000_0111_1100 and 0B0000_0000_0101_ 1011.

Further, the MCU sends the encoded data packet to the FPGA by using DMA.

Further, the judging the working state of the FPGA according to the MISO level includes:

in the S _ WAIT and S _ CMD states, the MISO is kept at a high level;

in the S _ SEND state, MISO is low level;

the working state of the FPGA comprises a message receiving state, an S _ WAIT state, an S _ CMD state and an S _ SEND state;

the message receiving and the rest states are carried out in parallel, and an 8B/10B message decoding and receiving module of the FPGA receives and decodes the code stream on the MOSI data line;

in the S _ WAIT state, the FPGA WAITs for the 8B/10B message decoding and receiving module to receive a new message, if the message is received, the message is verified, if the message is verified, the FPGA jumps to the S _ CMD state, and if the message is verified, the FPGA stays in the S _ WAIT state;

in the S _ CMD state, a command interpretation and execution module of the FPGA checks the received message, and if the command format is wrong or the command is not supported, the FPGA jumps back to the S _ WAIT state, otherwise, responds to the command, prepares response data of the command, WAITs for the MCU to read the command, and jumps to the S _ SEND state;

in the S _ SEND state, the enhanced SPI slave module of the FPGA takes a signal of an MOSI data line as an SPI clock, response data are shifted out through a MISO data line, and the MCU reads data on the MISO data line through an SPI peripheral device and then jumps to an S _ WAIT state; and if a new message is received, directly giving up the response and entering an S _ WAIT state.

Further, the performing of the handshake operation between the FPGA and the MCU according to the working status of the FPGA includes:

in the S _ WAIT state, the MISO is kept at a high level, the MCU detects that the MISO is at the high level, a data packet is sent to the FPGA, the FPGA does not successfully receive the data packet or command analysis of the data packet fails, the MISO is kept at the high level, and the MCU continues to WAIT until the MISO is at the low level;

entering an S _ SEND state, changing the MISO into a low level, reading response data by the MCU, or retransmitting a data packet and executing a new command;

and if the MCU finishes reading all the response data, jumping to the S _ WAIT state.

Further, if the waiting time is out, the data packet retransmission is carried out.

Further, the MCU reads the response data of the FPGA through the MISO, and during reading, the MCU needs to transmit fixed data 0b 01010101.

The invention achieves the following beneficial effects:

by using the method of the invention, the following steps can be realized: (1) the FPGA and the MCU can complete communication by only using 2 data lines; (2) the communication speed can reach hundreds of Mbps at the fastest speed.

Drawings

FIG. 1 is a schematic diagram of signal connection between an FPGA and an MCU according to the present invention;

FIG. 2 is an exemplary timing sequence of the SPI interface of the present invention;

FIG. 3 is an example of 8B/10B packet format transmitted by the MCU in the present invention;

FIG. 4 is a functional block diagram of an FPGA according to the present invention;

FIG. 5 is a schematic diagram of FPGA operating state transition according to the present invention;

FIG. 6 is a control diagram of the FPGA for the MISO data line of the SPI interface in the present invention;

FIG. 7 is the enhanced SPI slave interface timing in the present invention.

Detailed Description

The invention is further described below. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The invention provides a rapid communication method between an FPGA and an MCU, which comprises the following steps:

as shown in fig. 1, the FPGA and the MCU are connected through only 2 data lines, where MISO is a master input of the SPI, and a slave outputs a signal, and since the MCU is a master of the SPI and the FPGA is a slave, the MISO is directed from the FPGA to the MCU; the MOSI is sent by a host computer of the SPI, the slave computer receives signals, and the direction is from the MCU to the FPGA; whereas the SCK and CS signals of the SPI interface are no longer needed.

MCU SPI interface configuration

a. SPI send word length

Communication data between the MCU and the FPGA takes bytes as a unit, but data sent to the FPGA by the MCU needs to be coded by 8b/10b, so that 1 byte is coded into 10 bits, generally, the SPI interface of the MCU supports the configuration of a sending word length, for example, a common STM32 chip supports the configuration of the sending word length of 4-16 bits, so that the word length can be configured into 10 bits.

b. SPI idle clock state

The SPI interface may be idle with either a high or low clock state, but since the invention does not use the SCK signal, the idle clock state may be configured high or low.

c. SPI data sampling edge

The SPI interface data sampling edge may be a first edge sampling or a second edge sampling, the present invention requires the SPI master/slave to put data on the data line at the second edge, i.e., the first edge, the SPI master/slave samples data on the data line, the second clock edge, the SPI slave/master samples data on the data line, and the interface timing is as shown in fig. 2.

d. DMA transmission

The invention requires that the SPI message sent to the FPGA by the MCU must be sent through the DMA, so that the data code stream on the MOSI data line is ensured to be continuous, and the received data can be decoded by the FPGA.

In the invention, the data sent by the MCU needs to be coded by 8B/10B, and the 8B/10B coding is briefly introduced below.

In wired communication, the selection of data coding is important, for high-speed communication, the transmitted data is coded to include clock information (one data includes enough jumps), so that the receiving end can recover the clock from the received data to complete the data reception, such coding is generally manchester code, 4B/5B coding, 8B/10B coding and the like, while 8B/10B coding has high efficiency (80%), has rich control codes, can perform DC balance, and is widely used in optical fiber and wired communication.

8B/10B encodes and encodes the data code of 8bit into the code of 10bit, the data of 8bit is 256 altogether, and 10bit code has 1024, actually 8bit divides into 2 groups of codes, 0 that contains in the 1 st group of codes is more, 1 that contains in the 2 nd group of codes is more, like this during transmission, can dynamic selection code, come to balance the quantity of 0 and 1 in the whole transmission course, thus reach DC balance. In addition to the encoding of data, the 10-bit code has 512 more codes, except for the non-compliant codes (which contain too many consecutive 0's or 1's), and many more characters, called special characters, which can be used for control.

The coding format of 8B/10B belongs to the industry standard, the invention does not introduce, 4 special characters of 8B/10B coding are used as a packet head and a packet tail, and any 1 group of normal characters are used for completing the coding of message data.

The invention uses special characters K28.7 and K29.7 as the packet head of the data packet sent by MCU, uses special characters K28.7 and K27.7 as the packet tail, their 10B codes are respectively:

K28.7：0b0001111100

K29.7：0b0001011101

K27.7：0b0001011011

the format of the transmitted data packet is shown in fig. 3.

The use of the header and the trailer is very convenient for receiving by the FPGA, the shift register of the FPGA sequentially shifts the received data into a 20-bit register, if the value of the register is equal to K28.7+ K29.7, the header is considered to be received (because such a sequence does not appear in the encoded normal data), then the data is valid data, and similarly, when the value of the register is detected to be K28.7+ K27.7, the data packet is received completely, and the received data packet can be checked and the like.

The method for receiving the data packet by the FPGA is beyond the scope of the invention, and the invention assumes that when the MCU sends data according to the coding format, the FPGA can successfully receive the message and decode the message into the original data through 8B/10B.

In the invention, the FPGA comprises an 8B/10B message decoding and receiving module, a command interpreting and executing module, an enhanced SPI slave module and an external interface module as shown in figure 4.

The 8B/10B message decoding and receiving module is used for receiving the code stream sent on the MOSI signal line, carrying out 8B/10B decoding on the code stream and checking the correctness of the message; the command interpretation and execution module analyzes commands and parameters contained in the messages decoded by the 8B/10B message decoding and receiving module, prepares response data and waits for the MCU to read through the SPI; the enhanced SPI slave module sends the data prepared by the command interpretation and execution module to the MCU; and the external interface module is interfaced with other logic circuits of the FPGA to finish the actual application.

The working state transition of the FPGA is shown in fig. 5:

message receiving: the message receiving is carried out in parallel with other states, and an 8B/10B message decoding and receiving module of the FPGA always receives and decodes the code stream on the MOSI data line.

S _ WAIT: in the state, the FPGA WAITs for the 8B/10B message decoding and receiving module to receive a new message, if the message is received, the message is verified, if the message is verified, the FPGA jumps to the S _ CMD state, and if the message is verified, the FPGA stays in the S _ WAIT state.

S _ CMD: in this state, the command interpretation and execution module checks the received message, and jumps back to the S _ WAIT state if the command format is wrong or the command is not supported, or else, responds to the command, prepares the response data of the command, WAITs for the MCU to read, and jumps to the S _ SEND state.

S _ SEND: in this state, the enhanced SPI slave module of the FPGA takes a signal of an MOSI data line as an SPI clock, response data are shifted out through a MISO data line, and the MCU reads data on the MISO data line through an SPI peripheral device, then jumps to an S _ WAIT state and carries out next transmission; in addition, in the S _ SEND state, if a new message is received, the response is directly abandoned, the S _ WAIT state is entered, and new transmission is started.

The FPGA data processing process comprises the following steps:

handshaking mechanism

MCU sends the data packet to FPGA, need to guarantee FPGA is correct to receive and explain, can go to read the response data, the invention uses MISO data link to carry out the handshake operation, its principle is:

in the S _ WAIT state, the MISO is kept at a high level, the MCU detects that the MISO is at a high level, and can transmit a packet to the FPGA, and the FPGA does not successfully receive the packet or the command analysis of the packet fails, and keeps the MISO high, and the MCU can retransmit the packet until the MISO is at a low level, that is, the MISO is kept at a high level in the S _ WAIT and S _ CMD states.

Entering an S _ SEND state, changing the MISO into a low level, informing the MCU that the response data can be read, reading the response data by the MCU at the moment, and retransmitting a data packet to execute a new command; if the MCU finishes reading all the response data, the state jumps to S _ WAIT, the MISO also changes to high level, and the MCU is told to start new transmission.

MISO data line control as shown in figure 6,

in the S _ WAIT state and the S _ CMD state, the control right of the MISO is in the state machine, the MISO keeps high level, the state is entered into the S _ SEND state, the MISO is pulled low, in the state, the MOSI signal is used as a clock signal of the SPI, when the clock edge of the MOSI comes, the control of the MISO is transferred to the SPI slave, namely, response data is output, after all the response data are sent, the state is entered into the S _ WAIT state, the control of the MISO is transferred back to the state machine, and the MISO outputs high level.

The SPI slave shifts the transmission data by one bit on both the rising edge and the falling edge of a clock signal (here, the MOSI signal is used as a clock) and places the transmission data on the MISO data line, so this logic is adopted because only two data lines, MOSI and MISO, are connected between the MCU and the FPGA, and the FPGA cannot receive the SCK signal of the SPI, but if the MCU transmits fixed data (0 b 01010101), the falling edge and the rising edge of the MOSI signal will have the same timing as the SCK and can be used as an SPI clock, but the edge flip speed is half of the SCK, so the SPI master interface of the MCU can adopt correct data using the double-edge data output method.

If the response data has 2 bytes, 0x12 and 0x34, respectively, then the timing of MOSI and MISO in S _ SEND state is shown in fig. 7.

The MCU reads 2 bytes of response data, 2 pieces of 0x55 are sent through the SPI interface, the waveform of the MOSI signal is shown in fig. 7, the FPGA takes the waveform as a clock signal, the response data are shifted and placed on a MISO data line on a rising edge and a falling edge, the waveform of the MISO is shown in fig. 7, the data on the MISO are received by the SPI interface of the MCU on the rising edge of an SCK clock, correct response data 0x12 and 0x34 can be obtained, therefore, the data of the SPI slave can be correctly read without using the SCK signal, and the full-speed operation of the SPI is guaranteed.

The communication process between the FPGA and the MCU is as follows:

the MCU sends a data packet to the FPGA through the SPI interface, each data in the data packet is 1 byte, 10 bits are programmed through 8b/10b coding, and the data packet comprises a packet head and a packet tail.

The FPGA receives the code stream sent by the MCU, decodes the code stream to obtain original data, prepares corresponding response data according to the command of the data packet, starts the enhanced SPI slave module and waits for the MCU to read.

The MCU reads the response data of the FPGA through the SPI interface, and each data is 16 bits without being coded.

The whole communication process is as follows.

(1) MCU configures SPI peripheral equipment, and SPI transmission word length is 10 bits, and idle clock polarity is the high level, samples at the second border of SCK.

(2) The MCU calculates the check code of the data packet to be transmitted, and the check code is placed at the end of the data packet to generate an original data packet.

(3) The original data packet is coded into 10bit code by 8B/10B, the original 1 byte occupies 16bit after coding (SPI only sends 10bit lower), namely the occupied space is 2 times of the original.

(4) Adding a header and a tail to a coded data packet, adopting special characters K28.7 and K29.7 as the header and special characters K28.7 and K27.7 as the tail, because 10B is coded into 10 bits, and when the MCU processes data, the unit of byte (8 bits) is used for indicating that 10 bits need 2 bytes, and when coding, the high bit of 10B coding is supplemented with 0 to indicate.

And packaging into an encoded data packet, wherein the header and the trailer are both 2 × 10 bits, and each occupy 4 bytes, and the header is encoded as 0b0000_0000_0111_1100, 0b0000_0000_0101_1101, and the trailer is encoded as 0b0000_0000_0111_1100, 0b0000_0000_0101_ 1011.

(5) The MCU sends the coded data packet to the FPGA by using the DMA; the FPGA successfully receives the message and decodes the message into original data through 8B/10B, corresponding response data are prepared according to the command of the data packet, the SPI slave module is started, and the MCU is waited for reading.

(6) And (3) after the coded data packet is sent, the MCU checks the level of the MISO, if the level is high, the FPGA receives or interprets the data packet or the data packet is in error transmission, the MCU continues to wait, if the waiting time is out, the MCU returns to the step (5) to retransmit, and if the MISO is changed into low level, the MCU enters the step (7).

(7) The MCU reconfigures the SPI peripheral to have the transmission word length of 8 bits (only 1 byte is needed for one data because the received data is not coded by 8B/10B), the polarity of the idle clock is high level, and the sampling is carried out on the second edge of the SCK.

(8) The MCU reads the response data of the FPGA through the MISO interface (DMA is not necessarily used), and it is noted that at the time of reading, the MCU transmits fixed data 0b01010101, so that the waveform of the equivalent SCK appears on the MOSI signal line, as described earlier.

(9) And (4) jumping to the step (1) and starting to carry out next transmission.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (9)

1. A method for fast communication between an FPGA and an MCU is characterized by comprising the following steps:

(1) the MCU configures the SPI peripheral equipment, configures the SPI transmission word length to be 10bit, and the polarity of an idle clock is high level, and samples at the second edge of the SCK;

(2) the MCU calculates the check code of the data packet to be transmitted, and the check code is placed at the end of the data packet to generate an original data packet;

(3) encoding the original data packet into a 10bit code by 8B/10B;

(4) adding a packet head and a packet tail to a 10-bit data packet, and packaging into an encoded data packet;

(5) the MCU sends the coded data packet to the FPGA through the MOSI; the FPGA successfully receives the message, decodes the message into original data through the 8B/10B message decoding and receiving module, prepares corresponding response data according to the command of the data packet, starts the enhanced SPI slave module and waits for the MCU to read;

(6) after the coded data packet is sent, the MCU checks the level of the MISO and judges the working state of the FPGA according to the level of the MISO;

(7) performing handshake operation between the FPGA and the MCU according to the working state of the FPGA, and transmitting response data by the FPGA;

(8) the MCU reconfigures the SPI peripheral, configures the character length of SPI transmission to be 8bit, and the polarity of an idle clock is high level, and samples at the second edge of the SCK;

(9) the MCU reads response data of the FPGA through the MISO;

(10) and (4) jumping to the step (1) and starting to carry out next transmission.

2. The method of claim 1, further comprising the step of connecting the FPGA and the MCU via 2 data lines,

configuring MISO as a host input of the SPI and outputting signals from a slave;

configuring a host with MOSI as SPI to send and a slave to receive signals;

the MCU is a host computer of the SPI, and the FPGA is a slave computer of the SPI.

3. The method according to claim 2, wherein the FPGA comprises an 8B/10B message decoding and receiving module, a command interpreting and executing module, an enhanced SPI slave module and an external interface module;

the 8B/10B message decoding and receiving module is used for receiving the code stream sent on the MOSI signal line, carrying out 8B/10B decoding on the code stream and checking the correctness of the message;

the command interpretation and execution module is used for analyzing the message decoded by the 8B/10B message decoding and receiving module to obtain a command and parameters and preparing response data;

the enhanced SPI slave module is used for sending response data prepared by the command interpretation and execution module to the external interface module;

the external interface module is used for transmitting data to the MCU through the MISO.

4. The method according to claim 1, wherein the adding a header and a trailer to a 10-bit data packet, and packing the data packet into an encoded data packet comprises:

special characters K28.7 and K29.7 coded by 8B/10B are used as packet headers of the data packets, and special characters K28.7 and K27.7 are used as packet tails of the data packets;

the high order of 10B code is complemented with 0 to obtain the code of the header as 0B0000_0000_0111_1100 and 0B0000_0000_0101_1101, and the code of the tail as 0B0000_0000_0111_1100 and 0B0000_0000_0101_ 1011.

5. The method of claim 1, wherein the MCU sends the encoded data packets to the FPGA using DMA.

6. The method of claim 1, wherein said determining the operating state of the FPGA according to the MISO level comprises:

in the S _ WAIT and S _ CMD states, the MISO is kept at a high level;

in the S _ SEND state, MISO is low level;

the working state of the FPGA comprises a message receiving state, an S _ WAIT state, an S _ CMD state and an S _ SEND state;

the message receiving and the rest states are carried out in parallel, and an 8B/10B message decoding and receiving module of the FPGA receives and decodes the code stream on the MOSI data line;

in the S _ WAIT state, the FPGA WAITs for the 8B/10B message decoding and receiving module to receive a new message, if the message is received, the message is verified, if the message is verified, the FPGA jumps to the S _ CMD state, and if the message is verified, the FPGA stays in the S _ WAIT state;

in the S _ CMD state, a command interpretation and execution module of the FPGA checks the received message, and if the command format is wrong or the command is not supported, the FPGA jumps back to the S _ WAIT state, otherwise, responds to the command, prepares response data of the command, WAITs for the MCU to read the command, and jumps to the S _ SEND state;

in the S _ SEND state, the enhanced SPI slave module of the FPGA takes a signal of an MOSI data line as an SPI clock, response data are shifted out through a MISO data line, and the MCU reads data on the MISO data line through an SPI peripheral device and then jumps to an S _ WAIT state; and if a new message is received, directly giving up the response and entering an S _ WAIT state.

7. The method according to claim 6, wherein the performing of the handshake operation between the FPGA and the MCU according to the working status of the FPGA comprises:

in the S _ WAIT state, the MISO is kept at a high level, the MCU detects that the MISO is at the high level, a data packet is sent to the FPGA, the FPGA does not successfully receive the data packet or command analysis of the data packet fails, the MISO is kept at the high level, and the MCU continues to WAIT until the MISO is at the low level;

entering an S _ SEND state, changing the MISO into a low level, reading response data by the MCU, or retransmitting a data packet and executing a new command;

and if the MCU finishes reading all the response data, jumping to the S _ WAIT state.

8. The method of claim 7, wherein if the wait time is out, retransmitting the data packet.

9. The method of claim 1, wherein the MCU reads the response data of the FPGA through the MISO, and the MCU transmits the fixed data 0b 01010101.

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