CN201886466U

CN201886466U - Seamless transition module from MDIO (management data input output) bus slave computer to SPI (serial peripheral interface) bus

Info

Publication number: CN201886466U
Application number: CN2010206608836U
Authority: CN
Inventors: 袁涛; 陈龙; 祝成军; 李丹; 邹晖; 胡毅
Original assignee: Wuhan Telecommunication Devices Co Ltd
Current assignee: Wuhan Telecommunication Devices Co Ltd
Priority date: 2010-12-15
Filing date: 2010-12-15
Publication date: 2011-06-29
Anticipated expiration: 2020-12-15

Abstract

The utility model discloses a seamless transition module from an MDIO (management data input output) bus slave computer to an SPI (serial peripheral interface) bus, which comprises an FPGA (field programmable gate array), wherein the FPGA is respectively connected with a system planar and an MCU (micro control unit) of an optical module. According to the seamless transition module provided by the utility model, the switching over of the system planar and the MCU of the optical module is realized by the FPGA; by utilizing the programmable characteristic of the FPGA, the analysis of an MDIO bus interface can be realized, thus data streams received by the MDIO bus slave computer can be decoded and converted to be output by an SPI host computer interface, and the data streams received by the SPI host computer can be decoded and converted to be output by the MDIO bus slave computer. According to the seamless transition module, the timing sequence requirement of an MDIO protocol can be met and realized, and the SPI interface is realized by a plurality of main stream MCUs, thus the protocol requirement of the optical module can be realized by a universal MCU and the control requirement can be finished.

Description

The MDIO bus slave computer is to the bumpless transfer module of spi bus

Technical field

The utility model relates to a kind of interface protocol modular converter, specifically, is the bumpless transfer module of a kind of MDIO bus slave computer to SPI (Serial Peripheral Interface (SPI)) bus.

Background technology

At present, (interface of optical module of 40G～100G) and system communication adopts MDIO (management data input and output) interface to the part novel high speed, slightly variant with the MDIO interface on the PHY chip of using always (ethernet physical layer transceiver), be embodied on speed and the frame structure.On the other hand, the realization of the control section of optical module is limited by size and complexity, selects for use MCU (Micro Control Unit, micro-control unit) to realize control mostly, but realizes that without any MCU MDIO is from interface now.Be exactly that existing MCU can't carry out communication with the MDIO interface on the system board in simple terms.

The utility model content

The technical problems to be solved in the utility model provides a kind of interface protocol modular converter, can realize that the MDIO interface on MCU and the system board carries out communication.

In order to solve the problems of the technologies described above, the utility model provides the bumpless transfer module of a kind of MDIO bus slave computer to spi bus, comprise on-site programmable gate array FPGA, described FPGA links to each other by the micro-control unit MCU of interface with System Backplane and optical module respectively.

Described interface is an IO interface.

It is the MCU switching of System Backplane and optical module that the utility model adopts FPGA, utilize the programmable features of FPGA, realization is to the parsing of MDIO bus interface, the data stream decoding conversion of MDIO slave is exported by the SPI host interface, the data stream decoding conversion that the SPI main frame receives is exported by the MDIO slave.Can satisfy and the requirement of realization MDIO agreement sequential, and the SPI interface is realized by most of main flow MCU, so just can realize the protocol requirement of optical module and finish the control requirement with general MCU.

Description of drawings

Fig. 1 is the frame diagram of MDIO bus slave computer of the present utility model to the bumpless transfer module of spi bus;

Fig. 2 be embodiment illustrated in fig. 1 in the schematic diagram that leads to of each module.

Embodiment

The utility model is described in further detail below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the utility model and being implemented, but illustrated embodiment is not as to qualification of the present utility model.

As shown in Figure 1, MDIO bus slave computer of the present utility model is to the bumpless transfer module of spi bus, comprise FPGA (Field-Programmable Gate Array, field programmable gate array), described FPGA links to each other by the micro-control unit MCU of interface with System Backplane and optical module respectively.Wherein, said interface is input and output (I/O) interfaces.

Wherein, SCK is the spi bus serial clock of FPGA simulation; MOSI is the spi bus output data line for FPGA, is the spi bus input data line for MCU; MISO is the spi bus input data line for FPGA, is the spi bus output data line for MCU; NSS is a spi bus chip selection signal line, and when being high level, the spi bus of MCU is invalid, and when being low level, the spi bus of MCU is effective; Condition line 1 and condition line 2, when being 00 be MDIO send for the address, be 01 o'clock be MDIO send be the write data order, be 10 o'clock be MDIO send be continuous read command; Be 11 o'clock be MDIO send be the single read command; The handshake line is guaranteed communication just often when FPGA need shake hands, and FPGA will send a pulse, and notice MCU will carry out handshake operation, after the success of shaking hands, level is put height, and notice MCU shakes hands successful; The MCU condition line, a pulse notice FPGA is sent out in acting as of this line, and MCU is ready to, can carry out next step operation

See also Fig. 1, the MDIO data stream that FPGA receiving system backboard transmits converts the SPI stream data transmission to and gives MCU, carries out the mutual of MDIO data between FPGA and the System Backplane, and becomes SPI data and MCU mutual the MDIO data-switching.

The above embodiment is the preferred embodiment that proves absolutely that the utility model is lifted, and protection domain of the present utility model is not limited thereto.Being equal to that those skilled in the art are done on the utility model basis substitutes or conversion, all within protection domain of the present utility model.Protection domain of the present utility model is as the criterion with claims.

Claims

1. a MDIO bus slave computer is characterized in that to the bumpless transfer module of spi bus comprise on-site programmable gate array FPGA, described FPGA links to each other by the micro-control unit MCU of interface with System Backplane and optical module respectively.

2. MDIO bus slave computer according to claim 1 is characterized in that to the bumpless transfer module of spi bus described interface is an IO interface.