CN113645751B - Signal line and anti-interference structure determining method and device - Google Patents
Signal line and anti-interference structure determining method and device Download PDFInfo
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- CN113645751B CN113645751B CN202110843898.9A CN202110843898A CN113645751B CN 113645751 B CN113645751 B CN 113645751B CN 202110843898 A CN202110843898 A CN 202110843898A CN 113645751 B CN113645751 B CN 113645751B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
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Abstract
The application discloses a signal wire, anti-interference structure's determination method and device, the signal wire includes: the first circuit and the second circuit are of asymmetric structures, and the first circuit comprises an anti-interference structure; the anti-interference structure is a fence-type structure; the phase speed of one signal wire in the asymmetric structure is regulated by the signal wire through the anti-interference structure, so that the phase speeds of the two signal wires are kept consistent, the phase difference change is avoided, and the electromagnetic interference problem is avoided; the anti-interference structure and the circuit are made of the same material as the whole, and any anti-interference component is not required to be added, so that the hardware cost is reduced.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a method and an apparatus for determining a signal line and an anti-interference structure.
Background
In the circuit design of the circuit board in the electronic product, the differential mode signals between the two paths of differential mode signal lines should keep a certain phase difference, which is usually 180 degrees. If the signal line is in a corner condition, the phase velocity at the inner side of the corner is generally larger than that at the outer side due to the asymmetric shape of the signal line, so that the phase difference is changed, and a certain electromagnetic interference problem is generated.
In the prior art, certain anti-interference components such as resistors, capacitors, inductors and the like can be added at the corner part of the signal line so as to solve the phase change problem and avoid electromagnetic interference. However, the additional components are added at additional cost.
Disclosure of Invention
The application provides a method and a device for determining a signal wire and an anti-interference structure, which are used for at least solving the technical problems in the prior art.
In a first aspect, the present application provides a signal line, the signal line comprising:
the first circuit and the second circuit are of asymmetric structures, and the first circuit comprises an anti-interference structure;
the anti-interference structure is a fence-type structure.
Preferably, the first circuit and the second circuit have an asymmetric structure, including:
the length of the first circuit is smaller than that of the second circuit.
Preferably, the anti-interference structure is a fence-type structure comprising:
the anti-interference structure comprises at least one first line section and at least one second line section;
the line width of the first line section is larger than the standard line width of the first line;
and the line width of the second line section is smaller than the standard line width of the first line.
Preferably, the length of each of the first line sections is equal to the length of each of the second line sections.
Preferably, the anti-interference structure is used for:
and enabling the differential mode signal in the first circuit to generate slow wave characteristics so as to adjust the phase speed of the differential mode signal in the first circuit.
In a second aspect, the present application provides a method for determining an anti-interference structure, where the anti-interference structure includes at least one first line segment and at least one second line segment; the method comprises the following steps:
determining a target phase velocity;
determining estimated size data of each first line segment and estimated size data of each second line segment;
determining estimated phase velocity according to the estimated size data of each first line section and the estimated size data of each second line section;
when the estimated phase velocity and the target phase velocity meet preset conditions, determining the estimated size data of each first line section as target size data of each first line section; and determining the estimated size data of each second line section as target size data of each second line section.
Preferably, the determining the estimated phase velocity according to the estimated size data of each first line section and the estimated size data of each second line section includes:
determining a capacitance value of the first line segment according to the estimated size data of the first line segment;
determining an inductance value of the second line section according to the estimated size data of the second line section;
and determining the estimated phase speed according to the capacitance value of the first line section and the inductance value of the second line section.
Preferably, when the estimated phase velocity and the target phase velocity meet a preset condition, determining the estimated size data of each first line segment as target size data of each first line segment; and determining the estimated size data of each second line segment as target size data of each second line segment includes:
when the difference value between the estimated phase velocity and the target phase velocity is smaller than a preset threshold value, determining the estimated size data of each first line section as the target size data of each first line section; and determining the estimated size data of each second line section as target size data of each second line section.
Preferably, the estimated size data of the first line section includes: the estimated length and the estimated line width of the first line section;
the estimated size data of the second line section includes; the estimated length and the estimated line width of the second line section;
the estimated length of the first line segment is equal to the estimated length of the second line segment.
In a third aspect, the present application provides a device for determining an anti-interference structure, where the anti-interference structure includes at least one first line segment and at least one second line segment; the device comprises:
the phase velocity determining module is used for determining a target phase velocity;
the estimated size determining module is used for determining estimated size data of each first line section and estimated size data of each second line section;
the phase velocity estimation module is used for determining estimated phase velocity according to the estimated size data of each first line section and the estimated size data of each second line section;
the target size determining module is used for determining the estimated size data of each first line section as the target size data of each first line section when the estimated phase speed and the target phase speed meet preset conditions; and determining the estimated size data of each second line section as target size data of each second line section.
Compared with the prior art, the method and the device for determining the signal wire and the anti-interference structure provided by the application have the advantages that the phase speed of one signal wire in the asymmetric structure is adjusted through the anti-interference structure, so that the phase speeds of the two signal wires are kept consistent, the phase difference change is avoided, and the electromagnetic interference problem is avoided; the anti-interference structure and the circuit are made of the same material as the whole, and any anti-interference component is not required to be added, so that the hardware cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art signal line;
fig. 2 is a schematic structural diagram of a signal line according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an anti-interference structure in a signal line according to an embodiment of the present application;
FIG. 4 is a flow chart of a method for determining an anti-interference structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating a portion of an anti-interference structure in a method for determining an anti-interference structure according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a device for determining an anti-interference structure according to an embodiment of the present application.
Detailed Description
In order to make the objects, features and advantages of the present application more obvious and understandable, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the circuit design of the circuit board in the electronic product, the differential mode signals between the two paths of differential mode signal lines should keep a certain phase difference, which is usually 180 degrees. If the signal line is in a corner condition, the phase velocity at the inner side of the corner is generally larger than that at the outer side due to the asymmetric shape of the signal line, so that the phase difference is changed, and a certain electromagnetic interference problem is generated.
As shown in fig. 1, a schematic diagram of the case that two differential mode signal lines form a right angle is shown. In order to avoid electromagnetic interference, certain anti-interference components, such as resistors, capacitors, inductors, etc., can be added at the corner of the signal line, so as to solve the phase change problem and avoid electromagnetic interference. However, the additional components are added at additional cost. Particularly, on the premise of mass production of electronic products, any slight additional improvement can cause a large economic burden.
Therefore, the embodiments of the present application provide a signal line to at least solve the above technical problems in the prior art. As shown in fig. 2, the signal line specifically includes:
a first line 01 and a second line 02. The first line 01 and the second line 02 have an asymmetric structure. In the case shown in fig. 2, the first line 01 and the second line 02 have an asymmetric structure with right angles. And the first circuit 01 is located inside the right angle corner. In other words, the length of the first line 01 is smaller than the length of the second line 02.
Therefore, under normal conditions, the phase velocity on the first line 01 will be greater than that on the second line 02, so that the phase difference will change when the differential mode signal passes through the asymmetric structure, and the electromagnetic interference problem will be derived. In this embodiment, therefore, a specific anti-interference structure 13 will be designed on the first line 01. The anti-tamper structure 13 is a "fence" structure, as shown in fig. 3.
The so-called "barrier-type" anti-interference structure 13 may in particular comprise at least one first line section 31 and at least one second line section 32. The line width of the so-called first line segment 31, i.e. the thicker part of the anti-interference structure 13, i.e. the line width of the first line segment 31, is larger than the standard line width of the first line 01 (i.e. the normal line width of the other parts than the anti-interference structure). The so-called second line segment 32, i.e. the part of the interference-free structure 13 with a smaller line width, i.e. the line width of the second line segment 32, is smaller than the standard line width of the first line 01. The first line segments 31 and the second line segments 32 are alternately arranged at the corner positions, so that the interference-free structure 13 is formed.
The materials of the first line segment 31 and the second line segment 32 in the anti-interference structure 13 may be the same as the entire material of the first line 01. That is, the interference preventing structure 13 is constituted by essentially only changing the line width at different positions of the first wiring 01 by design. Therefore, no anti-interference component is needed to be added, and the hardware cost is reduced. It is also preferable that the length of each first line segment 31 is set to be equal to the length of each second line segment 32. I.e. an equally spaced alternating arrangement of first line segments 31 and second line segments 32.
Due to the form of the anti-interference structure 13, the differential mode signal in the first line 01 can generate slow wave characteristics when passing through the anti-interference structure 13, so as to adjust (or reduce) the phase velocity of the differential mode signal in the first line 01. So that the phase velocity of the differential mode signal is kept uniform among the asymmetric structures of the first line 01 and the second line 02. Therefore, the phase difference change caused by the phase speed change of the differential mode signal can be avoided, namely the electromagnetic interference problem is avoided.
In the signal lines described in the embodiments shown in fig. 2 to 3, the anti-interference structure 13 may generate slow wave characteristics of the differential mode signal, so as to reduce the phase velocity thereof, so that the phase velocity of the differential mode signal in the first line 01 and the second line 02 is kept consistent. However, in practice, how to design the shape and the size of the anti-interference structure 13 is specifically needed, and the requirement of phase velocity consistency can be met, and the following method for determining the anti-interference structure is needed.
Fig. 4 shows a specific embodiment of a method for determining an anti-interference structure described in the present application. The method specifically comprises the following steps:
step 410, determining a target phase velocity.
In the present embodiment, the target phase velocity is the phase velocity of the differential mode signal in the second line 02 on the outer side in the foregoing embodiment. This will be taken as the target phase velocity in this embodiment. That is, the method in this embodiment aims to make the phase velocity in the first line 01 on the inner side coincide with the target phase velocity by designing the anti-interference structure. In this embodiment, the target phase velocity may be represented by v 1.
As shown in fig. 5, a portion of one basis in the tamper resistant structure is shown. Similar to the previous embodiments, the part is a combination of a first line section and a second line section. In practice, the interference-free structure determined in this embodiment is formed by a plurality of such combinations. In this embodiment, the estimated size data of the first line section is determined, mainly by determining the estimated length L1 and the estimated line width W1 of the first line section. The estimated size data of the second line section is determined, and the estimated length L2 and the estimated line width W2 of the second line section are mainly determined. Generally, for facilitating subsequent calculations, it may be determined that the estimated length L1 of the first line segment is equal to the estimated length L2 of the second line segment. In this embodiment, the estimated length L1 and the estimated line width W1 of the first line segment, and the estimated length L2 and the estimated line width W2 of the second line segment may be temporary values set by estimation.
Other relevant data, such as the distance from the first line segment and the second line segment to the outside second line, etc., may also be included in the estimated size data of the first line segment and the second line segment. This is not limited in this embodiment.
As can be seen from the transmission line theory known in the art, the increase of the line width can cause the impedance of the line segment to be reduced, thereby generating a capacitance effect; the decrease in line width causes an increase in impedance of the line segment, creating an inductive effect. For the anti-interference structure, the line width of the first line section is larger than the standard line width of the first line; the line width of the second line section is smaller than the standard line width of the first line. It can thus be considered that the first line section corresponds to a capacitance and the second line section corresponds to an inductance.
The estimated length L1 and the estimated line width W1 of the first line segment determine the capacitance value C of the first line segment. The estimated length L2 and the estimated line width W2 of the second line segment determine the inductance value L of the second line segment. That is, the capacitance value of the first line segment may be determined based on the estimated size data of the first line segment; and determining the inductance value of the second line section according to the estimated size data of the second line section. Namely, according to the estimated size data, the corresponding capacitance value C and inductance value L can be calculated. The above calculation process may be calculated using calculation software commonly used in the art, for example, using Q3D calculation software. In other cases, of course, the calculation can be performed by other calculation software.
The estimated phase velocity v2 can be determined from the capacitance value of the first line segment and the inductance value of the second line segment. Under the capacitance value and the inductance value, the anti-interference structure can enable the estimated phase velocity v2 reached by the differential mode signal to be calculated by the following formula:
The method in this embodiment aims at determining the anti-interference structure so that the phase velocity obtained by the structure adjustment of the anti-interference structure is consistent with or close to the target phase velocity. After the estimated phase velocity v2 is obtained, it may be determined whether the difference between the estimated phase velocity and the target phase velocity is smaller than a preset threshold. When the difference between the estimated phase velocity and the target phase velocity is smaller than the preset threshold, the preset condition, namely the setting of the estimated size data, can be considered to be reasonable. Further determining the estimated size data of each first line segment as target size data of each first line segment; and determining the estimated size data of each second line segment as target size data of each second line segment. Thus, the design of the anti-interference structure is completed.
Conversely, if the difference between the estimated phase velocity and the target phase velocity is greater than the preset threshold, the preset condition may not be satisfied, that is, the setting of the estimated size data is unreasonable. The predicted size data may be reset at this time and steps 402-404 may be repeated until the predetermined condition is satisfied.
According to the method for determining the signal line and the anti-interference structure in the embodiment, the beneficial effects of the method are as follows: the phase speed of one signal wire in the asymmetric structure is regulated through the anti-interference structure, so that the phase speeds of the two signal wires are kept consistent, the phase difference change is avoided, and the electromagnetic interference problem is avoided; the anti-interference structure and the circuit are made of the same material as the whole, and any anti-interference component is not required to be added, so that the hardware cost is reduced.
Fig. 6 shows an embodiment of a device for determining an anti-interference structure according to the present application. The device of this embodiment is a physical device for performing the method described in fig. 4. The technical solution is essentially identical to the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in this embodiment includes:
a phase velocity determining module 601, configured to determine a target phase velocity;
the estimated size determining module 602 is configured to determine estimated size data of each first line segment and estimated size data of each second line segment;
a phase velocity estimating module 603, configured to determine an estimated phase velocity according to the estimated size data of each first line segment and the estimated size data of each second line segment;
a target size determining module 604, configured to determine the estimated size data of each first line segment as target size data of each first line segment when the estimated phase velocity and the target phase velocity meet a preset condition; and determining the estimated size data of each second line segment as target size data of each second line segment.
In addition to the methods and apparatus described above, embodiments of the present application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform steps in a method according to various embodiments of the present application described in the "exemplary methods" section of the present specification.
The computer program product may write program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present application may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform steps in a method according to various embodiments of the present application described in the above section "exemplary method" of the present specification.
The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not intended to be limited to the details disclosed herein as such.
The block diagrams of the devices, apparatuses, devices, systems referred to in this application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
It is also noted that in the apparatus, devices and methods of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent to the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (9)
1. A signal line, the signal line comprising:
the first circuit and the second circuit are of asymmetric structures, and the first circuit comprises an anti-interference structure;
the anti-interference structure is a fence-type structure;
the first circuit and the second circuit are in an asymmetric structure and comprise: the length of the first circuit is smaller than that of the second circuit.
2. The signal line of claim 1, wherein the anti-tamper structure is a "fence" structure comprising:
the anti-interference structure comprises at least one first line section and at least one second line section;
the line width of the first line section is larger than the standard line width of the first line;
and the line width of the second line section is smaller than the standard line width of the first line.
3. The signal line of claim 2, wherein a length of each of the first line segments is equal to a length of each of the second line segments.
4. A signal line according to any one of claims 1 to 3, wherein the anti-interference structure is for:
and enabling the differential mode signal in the first circuit to generate slow wave characteristics so as to adjust the phase speed of the differential mode signal in the first circuit.
5. A method for determining an anti-interference structure, wherein the anti-interference structure comprises at least one first line section and at least one second line section; the anti-interference structure is positioned on the first circuit; the width of the first line section is larger than the standard line width of the first line, and the width of the second line section is smaller than the standard width of the first line; the method comprises the following steps:
determining a target phase velocity;
determining estimated size data of each first line segment and estimated size data of each second line segment;
determining estimated phase velocity according to the estimated size data of each first line section and the estimated size data of each second line section;
when the estimated phase velocity and the target phase velocity meet preset conditions, determining the estimated size data of each first line section as target size data of each first line section; and determining the estimated size data of each second line section as target size data of each second line section.
6. The method of claim 5, wherein determining the estimated phase velocity based on the estimated size data for each of the first line segments and the estimated size data for each of the second line segments comprises:
determining a capacitance value of the first line segment according to the estimated size data of the first line segment;
determining an inductance value of the second line section according to the estimated size data of the second line section;
and determining the estimated phase speed according to the capacitance value of the first line section and the inductance value of the second line section.
7. The method of claim 5, wherein the determining the estimated size data of each of the first line segments as the target size data of each of the first line segments when the estimated phase velocity and the target phase velocity satisfy a preset condition; and determining the estimated size data of each second line segment as target size data of each second line segment includes:
when the difference value between the estimated phase velocity and the target phase velocity is smaller than a preset threshold value, determining the estimated size data of each first line section as the target size data of each first line section; and determining the estimated size data of each second line section as target size data of each second line section.
8. The method of any of claims 5-7, wherein the pre-estimated size data of the first line segment comprises: the estimated length and the estimated line width of the first line section;
the estimated size data of the second line section includes; the estimated length and the estimated line width of the second line section;
the estimated length of the first line segment is equal to the estimated length of the second line segment.
9. A device for determining an anti-interference structure, wherein the anti-interference structure comprises at least one first line section and at least one second line section; the anti-interference structure is positioned on the first circuit; the width of the first line section is larger than the standard line width of the first line, and the width of the second line section is smaller than the standard width of the first line; the device comprises:
the phase velocity determining module is used for determining a target phase velocity;
the estimated size determining module is used for determining estimated size data of each first line section and estimated size data of each second line section;
the phase velocity estimation module is used for determining estimated phase velocity according to the estimated size data of each first line section and the estimated size data of each second line section;
the target size determining module is used for determining the estimated size data of each first line section as the target size data of each first line section when the estimated phase speed and the target phase speed meet preset conditions; and determining the estimated size data of each second line section as target size data of each second line section.
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