CN105574289B - The capacitance wiring method and device such as one kind - Google Patents
The capacitance wiring method and device such as one kind Download PDFInfo
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- CN105574289B CN105574289B CN201610030445.3A CN201610030445A CN105574289B CN 105574289 B CN105574289 B CN 105574289B CN 201610030445 A CN201610030445 A CN 201610030445A CN 105574289 B CN105574289 B CN 105574289B
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Abstract
The present invention relates to the capacitance wiring method such as one kind, it is characterised in that the method includes at least：Identification treats the geometric parameter of wiring area and treats the geometry subsegment that wiring area is the tandem with unique number based on geometric parameter segmentation；Primary route is produced by wide mode, detects the geometry subsegment that simultaneously secondary cut does not meet standard conditions；At least one geometry subsegment and/or the capacitive differential of every cable based on calculating adaptively adjust geometric properties and/or the position of corresponding geometry subsegment and/or cable with the comparative result of predetermined capacitance.The present invention is on the premise of the minimum feature and minimum spacing of technological requirement is met, the capacitance of the cable of institute's cloth is set to try one's best small and approximately equal, it is equal to reach the brightness of the corresponding display pixel of every cable on liquid crystal panel, improves FPD performance, further increases integrated performance.
Description
Technical Field
The invention relates to the field of electronic design automation, in particular to a method and a device for equal capacitance wiring.
Background
With the continuous development of electronic technology, the wiring requirements for electronic design automation software of integrated circuits are increased. The current mainstream wiring method is to firstly adopt a mode of fine tuning by combining automatic wiring with manual wiring, the automatic wiring has the characteristics of high speed and high accuracy, and the manual wiring adjusts the local unreasonable design of the automatic wiring, so that the wiring efficiency is improved, and the huge workload brought by a large number of components of an integrated circuit is reduced.
Different wiring schemes are required to be adopted according to different application requirements, the current common wiring schemes comprise equal-resistance wiring, constant-value resistance wiring and the like, and the wiring requirements for equal-resistance wiring are common. At present, in a wiring process of a common integrated circuit, the requirement of minimum line width and minimum distance is not violated only by considering the arranged network lines, and the problem of equal capacitance of each network line is not considered. For the tablet circuit, when the circuit is wired, the capacitance values of the network cables are equal or the capacitance difference is within an acceptable range, so that the tablet computer can show more excellent performance.
Chinese patent publication No. CN1983236A discloses an auxiliary wiring system and method, in which the auxiliary wiring system is connected to wiring software, and a user sets a wiring constraint area and signal line types that can pass through the wiring constraint area on a circuit board, thereby improving the flexibility of wiring. However, this patent does not address the problem of performing equal capacitance routing to the routing constraint region.
Chinese patent publication No. CN203882295U discloses a wiring structure of a capacitive touch screen display, which includes: the flexible circuit board, the first wiring layer and the second wiring layer; a vertical lead wire led out from the short edge of the touch screen and a transverse lead wire led out from the short edge of the touch screen; the vertical lead is connected to the flexible circuit board through the second wiring layer; the lateral leads include at least one set of first lateral leads and at least one set of second lateral leads; the first transverse lead is connected to the flexible circuit board through the first wiring layer; the second transverse lead is connected to the flexible circuit board by the second wiring layer; the first transverse lead and the second transverse lead are both arranged close to the long edge of the touch screen. This patent relates to a wiring structure, but does not address the problem of wiring for isocapacitance. The disadvantage of this patent is that the length of the network cable is increased, and the resistance is increased to influence the signal transmission. Further, the patent increases the volume and area of the circuit board, which is not favorable for the design of the integrated circuit.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a method for equal capacitance wiring, which is characterized by at least comprising:
identifying geometric parameters of a region to be wired and dividing the region to be wired into geometric subsections with a string with a unique number based on the geometric parameters;
generating initial wiring in an equal-width mode, and detecting and secondarily cutting the geometric subsections which do not meet standard conditions;
and adaptively adjusting the geometric characteristics and/or positions of the corresponding geometric subsections and/or net lines based on the comparison result of the calculated capacitance difference value of at least one geometric subsection and/or each net line and the preset capacitance value.
According to a preferred embodiment, when the capacitance difference in the capacitance values is greater than a preset capacitance value, a reticle width adjustment value of the corresponding geometric sub-section and/or reticle is calculated and a geometric feature and/or position of the corresponding geometric sub-section and/or reticle is adjusted.
According to a preferred embodiment, the method further comprises: and adjusting the geometric characteristics and/or positions of the corresponding geometric subsections and/or network lines again based on the comparison result of the capacitance difference values of the adjusted geometric subsections and/or network lines and the preset capacitance values.
According to a preferred embodiment, the method of dividing the area to be wired comprises at least:
finding out a vertex which is not positioned on the initial edge and/or the terminal edge, and making a first angular bisector in the angular to-be-routed area formed by the vertex;
and making a corresponding inner edge according to the condition that the first angle bisector firstly intersects one of the outer edge, the second angle bisector, the starting edge and the terminating edge, thereby dividing the region to be wired into a convex quadrangle and/or a triangle.
According to a preferred embodiment, the method of dividing the area to be wired comprises at least:
and connecting the vertexes of the non-starting edge and the non-ending edge with at least one vertex in the opposite direction, thereby dividing the area to be wired into a triangle and/or a quadrangle.
According to a preferred embodiment, the capacitance calculation method with the geometrical subsections being convex quadrangles at least comprises the following steps:
obtaining the total capacitance of the geometric subsegment based on the sum of the first coupling capacitance and the second coupling capacitance of the geometric subsegment; wherein,
calculating a first coupling capacitance between the geometric subsegment and metal wires of different wiring layers based on the area of the convex quadrangle;
and obtaining a second coupling capacitance between the geometric subsegment and the adjacent network wire based on the equivalent distance between the geometric subsegment and the adjacent network wire in the same wiring layer.
According to a preferred embodiment, the method for calculating the grid width adjustment value of the geometric subsegment comprises the following steps:
calculating the weight of each inner edge in the area to be wired;
calculating and differentiating the capacitance of each geometric sub-segment;
and obtaining a reticle width adjustment value of the geometric subsegment according to the capacitance difference, the weight of the inner edge and the differential of the capacitance of each geometric subsegment.
According to a preferred embodiment, the method further comprises: and detecting the adjusted width value of the network cable and the distance between the adjacent network cables and selectively adjusting to enable the adjusted width value and the distance to meet the process parameters preset by a user.
According to a preferred embodiment, the method further comprises: and numbering each reticle and the divided geometric subsections thereof, and storing the capacitance value, reticle width and reticle width adjustment value of each geometric subsection and/or each reticle under the corresponding number.
The present invention also provides an equal-capacitance wiring device, comprising:
the area identification module is used for identifying geometric parameters of an area to be wired;
the dividing and wiring module is used for dividing the area to be wired into the serial geometric subsections based on the geometric parameters and generating initial wiring;
a calculation and analysis module for calculating at least one geometrical subsection and/or a capacitance value of each network wire; an adjustment output module for adaptively adjusting the geometric characteristics and/or positions of the respective geometric subsections and/or network wires based on a comparison of the capacitance value with a preset capacitance value.
The invention has the beneficial effects that:
1. the capacitance values of the network cables from the starting port to the ending port are equal or approximately equal without increasing the length of the network cables, so that the brightness of the display pixels corresponding to each network cable on the liquid crystal panel is equal.
2. The capacitance value of each network cable is reduced as much as possible without increasing the capacitance value of the network cable, and the attenuation interference of transmission signals is reduced.
3. Under the condition of meeting the process design, the reduction of the width and the length of the network cable reduces the space occupied by the flat integrated circuit and improves the integration performance.
Drawings
FIG. 1 is a process flow diagram of an equal capacitance routing method of the present invention;
FIG. 2 is a schematic structural view of a capacitor wiring device according to the present invention;
FIG. 3 is a schematic diagram of the division of the area to be wired according to the present invention;
FIG. 4 is another schematic diagram of the division of the area to be wired according to the present invention;
FIG. 5 is a schematic diagram of the calculation of the convex quadrilateral capacitance of the present invention; and
fig. 6 is a schematic diagram of the calculation of geometric subsegment differentials of the present invention.
List of reference numerals
10: the area identification module 20: the divided wiring module 30: calculation analysis module
40: the data storage module 50: the adjustment output module 501: comparison module
502: detection module
Detailed Description
The following detailed description is made with reference to the accompanying drawings.
The "inner side" referred to in the present invention refers to a side added by dividing a region to be wired, such as L2R2 and L1R1 in fig. 3.
The "start edge" referred to herein has an edge of the network cable start port PIN, such as L0R 0; "terminating edge" refers to an edge having a network cable terminating port PIN, such as L3R 3.
The term "outer side" as used herein means that the sides other than the starting and ending sides of the boundary of the region are referred to as outer sides, such as L2L1, R0R3, L3L2, and L1L 0.
The term "geometrical subsection" as used herein refers to a convex quadrilateral and/or a triangle.
The term "convex quadrangle" as used herein refers to a quadrangle having an angle of not more than 180 degrees at each corner. The term "geometric feature" as used herein refers to the width and shape of the geometric subsegment and/or the mesh wire. The term "process parameter" as used herein refers to a minimum line width value and a minimum pitch value.
The invention provides an equal-capacitance wiring method which is combined with the existing wiring software and can realize that the capacitance value of each network wire in a region to be wired is equal and the capacitance value is as small as possible under the condition of meeting the process.
The equal-capacitance wiring method mainly comprises the steps of identifying geometric parameters of a region to be wired, dividing the region to be wired into serial geometric subsections based on the geometric parameters and generating initial wiring. Calculating a capacitance value of at least one geometrical subsection and/or each wire. The geometric characteristics and/or the position of the respective geometric subsegment and/or reticle are adaptively adjusted based on a comparison of the capacitance value with a preset capacitance value.
Example one
FIG. 1 is a process flow diagram of an equivalent capacitance routing method of the present invention. Taking fig. 1 as an example, the equal capacitance wiring method of the present invention specifically includes the following steps:
s01: and reading in information of the wiring area and the port to be wired, including the number and the positions of the starting port and the ending port, and the size, the position and/or the shape of the wiring area.
S02: and after the division, all the network wires distributed in the wiring area are also divided into the geometrical subsections in series. And numbering each reticle and the divided geometric subsections of the reticle, and storing the calculated capacitance value, reticle width and reticle width adjustment value under the corresponding numbers.
S03: the initial routing is generated in a uniform width manner, i.e., the width of each initial net line is the same. Further, whether the initially wired network cables are completely positioned in the area to be wired and/or whether all the network cables are in the same metal wiring layer is detected; and detecting the shape of the geometric subsegment after each reticle segmentation, and performing secondary segmentation on the geometric subsegment under the condition that the geometric subsegment is not a convex quadrangle and/or a triangle so as to meet the condition that all the geometric subsegments are convex quadrangles and/or triangles.
S04: the current capacitance value of each wire/geometric subsection is estimated. The method comprises the steps of firstly calculating the capacitance value of each geometric subsegment, then storing the capacitance value of each geometric subsegment in a number corresponding to each geometric subsegment, obtaining the capacitance value of each network wire in a wiring area according to the capacitance value of the geometric subsegment included in each network wire, summing the capacitance values of all the network wires after the capacitance value calculation of each network wire is completed, and then dividing the sum by the number of the network wires in the wiring area to obtain the average capacitance value of all the network wires. And calculating the difference between the capacitance value of each grid line and the average capacitance value and recording the difference as a capacitance difference value.
S05: and judging whether the capacitance difference value is smaller than a preset capacitance value or not, and outputting a current wiring result if the capacitance difference value of each network cable in the area to be wired is smaller than the preset capacitance value. If the capacitance difference of at least one network cable is greater than the preset capacitance value, the step S06 is performed.
S06: and calculating the net wire width adjustment value of each geometric subsection according to the differential of the net wire capacitance value and the current capacitance difference value of each net wire.
S07: the shape and position of the geometric subsegment are adjusted by the reticle width adjustment value. And after obtaining the width adjustment value of the mesh wire, adjusting the width, the shape and/or the position of the corresponding geometric subsection, thereby realizing the adjustment of the width, the shape and/or the position of each mesh wire. And detecting the adjusted width value of the network cable and the distance between the adjacent network cables and selectively adjusting to enable the adjusted width value and the distance to meet the process parameters preset by a user.
And then, the step S04 is entered, and the capacitance of the adjusted geometric subsegment and/or the mesh wire is calculated and compared with the preset capacitance to selectively adjust again. And outputting the current wiring result until the capacitance difference values of all the network cables are smaller than the standard capacitance value.
The above steps can be adjusted according to actual conditions and needs.
Example two
The invention also provides equal-capacitance wiring devices applying the equal-capacitance wiring method, and the equal-capacitance wiring devices can be connected with wiring software. FIG. 2 is a schematic structural view of a capacitor wiring device according to the present invention. As shown in fig. 2, the capacitor wiring device includes a region identification module 10, a divided wiring module 20, a calculation analysis module 30, and an adjustment output module 50.
And the area identification module is used for identifying the geometric parameters of the area to be wired. The geometric parameters may be the shape, size, location of the area to be wired, and port information to be wired. The information of the ports to be wired is the number and the positions of the initial and/or the terminal ports. The user can select the size of the area to be wired through a mouse, touch and sliding mode, and reads the information of the starting port and the ending port through mouse/touch selection or clicking.
The region identification module 10 outputs the identified geometric parameters to the split routing module 20 for splitting the region to be routed into a series of geometric subsections based on the geometric parameters and generating initial routing. The dividing wiring module 20 automatically divides the region to be wired into convex quadrilateral or triangular geometric subsections according to the size and shape of the region to be wired and the information of the port to be wired. The split routing module 20 then initially routes the area to be routed, so that the initially routed mesh is also split into serial geometric subsections. Wherein the initial wiring is generated with an equal net line width.
In a specific embodiment, the adjustment output module 50 further includes a detection module 502, configured to detect whether the geometric sub-segment after the to-be-wired region is divided is a convex quadrilateral or a triangle. If it is detected that some geometric subsections are not convex quadrangles or triangles, the division wiring module 20 performs secondary division on the region until all geometric subsections are convex quadrangles or triangles. The calculation and analysis module 30 is facilitated to calculate the capacitance value of each geometric sub-section. The detection module 502 further detects whether the initially wired net wires are completely located inside the area to be wired and/or whether all net wires are on the same metal wiring layer. Whether the current wiring is completely positioned in the region to be wired or not is detected to avoid the current network cable from entering other wiring regions to influence the wiring order of the other regions.
The calculation and analysis module 30 is configured to calculate a capacitance value of at least one geometric sub-section and/or each wire. The calculation and analysis module 30 calculates a capacitance value for each geometric sub-segment and each wire mesh based on the initial routing and the divided geometric sub-segments generated by the division and routing module 20. The capacitance value includes at least: the capacitance value of each network wire, the capacitance value of each geometric subsection, and the average capacitance value and the capacitance difference value of all network wires in the area to be wired, wherein the capacitance difference value is the difference between the capacitance value and the average capacitance value of each network wire, namely, each network wire has one capacitance difference value. The calculation and analysis module 30 calculates the capacitance value of each network wire according to the capacitance values of the geometric subsections.
The adjustment output module 50 is configured to adaptively adjust the geometric characteristics and/or positions of the corresponding geometric subsections and/or grids based on the comparison of the capacitance values with the preset capacitance values. The adjustment output module includes a comparison module 501, the comparison module 501 is configured to compare the capacitance difference with a preset capacitance value, when the capacitance difference is greater than the preset capacitance value, the comparison module 501 outputs a determination signal to the calculation and analysis module 30, and the calculation and analysis module 30 calculates a reticle width adjustment value of each geometric sub-section corresponding to the reticle based on the determination signal and feeds the reticle width adjustment value back to the adjustment output module 50. The adjustment output module 50 adjusts the shape, width and position of the geometric subsections based on the reticle width adjustment value, so that the shape, width and position of the whole reticle are adjusted.
According to a preferred embodiment, in the adjusting process, the detecting module 502 detects whether the adjusted net line width value satisfies the minimum line width value and whether the space between the adjacent net lines satisfies the minimum space value. The adjusted network line width can meet the minimum line width value and the minimum spacing value of the process requirement, and therefore signal transmission is not affected. The adjacent network lines meet the minimum spacing value so that the electromagnetic interference between the adjacent network lines is kept within an acceptable range, and therefore normal communication between signals is not interfered. The user may enter a minimum line width value and a minimum pitch value in advance between performing equal capacitance wiring.
When the capacitance difference values of all the network cables are smaller than the preset capacitance value, the adjustment output module 50 outputs the current wiring result.
The capacitor wiring device such as a capacitor further comprises a data storage module 40, and the calculation and analysis module 30 stores the number of the network cable and the number of the corresponding geometric subsegment in the data storage module. After the calculation and analysis module 30 calculates the capacitance values of the geometric subsections, the capacitance values are correspondingly stored in the corresponding numbers, so that the capacitance values of each network cable can be obtained conveniently in the following process. The data storage module 40 is further configured to store a preset capacitance value, a minimum line width value, and a minimum distance value, and is further configured to store a net line width adjustment value, a net line width value after net line adjustment, and a position.
EXAMPLE III
The following describes in detail a method for dividing a region to be wired, a method for calculating resistance and capacitance of a geometric subsection, and a method for calculating a grid line width adjustment value according to the present invention, with reference to the accompanying drawings.
The method for dividing the area to be wired comprises the following steps:
FIG. 3 is a schematic diagram of the division of the area to be wired according to the present invention. As shown in fig. 3, the region surrounded by the solid line in the figure is the region to be wired. As can be seen from fig. 3, the region to be wired is divided into three irregular convex quadrangles in series after being divided.
FIG. 4 is another schematic diagram of the division of the area to be wired according to the present invention. As shown in fig. 4, after the area to be wired is divided by the divided wiring module 20, the area to be wired is divided into a series of a triangle and two convex quadrangles.
In fig. 3 and 4, the four small squares on the L0R0 and L3R3 sides represent the network port PINs, and the PIN numbers of the starting side L0R0 and the terminating side L3R3 are determined according to actual conditions.
After the division of the division and wiring module 20, each wire in the area to be wired is also divided into a plurality of geometric subsections, the calculation and analysis module 30 calculates the capacitance value of each geometric subsection of each wire, and the capacitance values of the geometric subsections of each wire are accumulated to obtain the capacitance value of the corresponding wire. Specifically, before the division of the to-be-wired region by the division wiring module 20, the calculation and analysis module 30 numbers each mesh of the to-be-wired region, such as N1, N2, N3 … … Nn. After each wire is divided into a plurality of small geometric subsections, the calculation and analysis module 20 numbers each geometric subsection of each wire correspondingly. Each geometric sub-segment like N1 is labeled N10, N11, N12 … … N1m, and each geometric sub-segment of N1 is labeled N20, N21, N22 … … N2m, where N ≧ 1, and m ≧ 1. And after the capacitance value of each geometric subsection is calculated, accumulating according to the number of the geometric subsections to obtain the capacitance value of the corresponding network cable.
Specifically, the split wiring module 20 splits the area to be wired by the following three methods.
the first method is that corresponding inner edges are made according to the condition that an angle bisector firstly intersects with one of an outer edge, other angle bisectors, a starting edge and a terminating edge, so that a region to be wired is divided into convex quadrangles and/or triangles, and ∠ L1R1 and ∠ L2R2 in fig. 3 and fig. 4 are angle bisectors of ∠ L0 ∠ L1 ∠ L2 and ∠ L1 ∠ L2 ∠ L3 respectively.
Specifically, a vertex which is not located on the starting edge L0R0 and/or the ending edge L3R3 is found, and an angle formed by the vertexes is used as an angular bisector of the to-be-wired area;
if the bisector first intersects an opposing outer edge, as shown in fig. 3, the vertex may be defined as an inner edge between the intersection points, such as L2R2 and L1R1 in fig. 3. The region to be wired L0R 1R2R3L 2L1 is divided into three geometrical subsections, namely a convex quadrangle L2L3R 2, a convex quadrangle L1L2R1 and a convex quadrangle L0L1R 0.
As shown in fig. 4, if a bisector first intersects another bisector, the vertex corresponding to the two intersecting bisectors is connected as the inner edge, as shown by L1R1 and L2R2 in fig. 4, the region to be wired is divided into a convex quadrangle L2L3R 1, a triangle L1L2R1 and a convex quadrangle L0L1R 0.
If the angle bisector intersects with one of the starting edge and/or the ending edge, the vertex is connected with any vertex on the starting edge and/or the ending edge to be used as the inner edge. For example, if L2R2 and L0R0 in fig. 3 intersect, the vertex L2 and the vertex R0 are connected to form the inner edge L2R0, respectively. When R0R3 is a straight line, the region to be wired is divided into a triangle L0L1R0 and a trapezoid R0L2L3R 3.
If the divided quadrilateral segment is not a convex quadrilateral or a triangle, the quadrilateral segment is divided again to meet the requirement of the convex quadrilateral or the triangle.
The second method comprises the following steps:
1 suppose that the set of left and right vertices is L ═ L, respectively0、L1、……Lp}，R＝{R0、R1、……RqIn which L is0R0Is a starting edge, LpRqIs a terminating edge;
2 noteWherein | LiL0L represents LiAnd L0The distance between them. Also, i.e.Obviously, 0 < xi，yi＜1；
3 in general, 0 < x1＜x2...＜xp-1，0＜y1＜y2…yq-1If i is present, x isi+l＜xiThen L is removediOr Li+1At any point of (i.e. L)iAnd Li+1The two points are combined into one point;
4 for xiIf there is yjSo that xi＝yjThen L isiRjAs the inner edge of the fragment, otherwise, find yj＜xi＜yj+1At the outer edge RjRj+11Of'jSo that
LiR′jAs the inner edge of the segment. Same pair of yjCarrying out the same operation;
5 finding R 'by iteration method due to nonlinearity'jThe coordinates of (a): first, find the line segment RjRj+1R of (A) toj 1So thatThen judging R'jIs in the position of Rj 1RjOr Rj 1Rj+1The above step (1); r can be obtained in a similar mannerj 2，Rj 3Up to Rj kThe same as the rounded coordinates.
The third method comprises the following steps: the vertices other than the vertices on the starting and ending edges are connected to the nearest vertex. Specifically, except for the vertices on the starting edge and the terminating edge, all other vertices are connected to the nearest vertex opposite thereto, and the area to be wired is divided into triangles or quadrangles. Furthermore, the user can manually select the number of the segments for dividing the wiring area according to the size of the area to be wired and the number of the starting ports and the ending ports. Therefore, the calculation analysis module can calculate the resistance and the capacitance value conveniently, the calculation complexity is reduced, and the wiring efficiency is improved.
The resistance calculation method of the geometric subsections comprises the following steps: if the geometric subsegment is an isosceles trapezoid, the method for calculating the resistance of the geometric subsegment is as follows:
the widths of the upper and lower bottoms of the isosceles trapezoid are respectively w0And w1And L is higher. An isosceles trapezoid can be seen as a series of numerous small isosceles trapezoids, each of which has a length Δ L. The width of the small trapezoid from the base x isThe resistance of which isThe resistance of the whole ladder is
When the geometric subsegment is an arbitrary convex quadrangle, the method for calculating the resistance of the geometric subsegment is as follows:
any geometric subsegment after the reticle is divided can be regarded as a quadrangle, so that the equivalent upper and lower bottom widths and the equivalent height of the quadrangle need to be found.
FIG. 5 is a diagram illustrating the calculation of the resistance of an arbitrary convex quadrilateral. As shown in fig. 5, the resistance values from L1R1 to L2R2 are estimated, the midpoint between two opposite sides L1R1 and L2R2 connecting the convex quadrilateral is found out as the equivalent height of the convex quadrilateral, C1 and C2 are the midpoint between L1R1 and L2R2, the equivalent height of the quadrilateral is C1C2, and there are two methods for estimating the equivalent upper and lower bottom widths of the quadrilateral.
the method comprises the steps of obtaining the equivalent upper bottom width and the equivalent lower bottom width of a quadrangle according to the included angle between the connecting line of two middle points and two opposite sides, specifically, setting the included angle between C1C2 and L1R1 is α the width of the bottom side corresponding to L1R1 as | L1R1| sin alpha, and calculating the width of the bottom side corresponding to L2R2 by using a similar method.
The second method comprises the following steps: and obtaining the equivalent upper bottom width and the equivalent lower bottom width according to the distance from the four vertexes of the convex quadrangle to the connecting line of the two midpoints. Specifically, let L1 and L2 be d1 and d2 respectively from C1C2, and it is clear that R1 and R2 are also d1 and d2 respectively from C1C 2. The two equivalent base widths of the quadrilateral are then 2 x d1 and 2 x d 2.
The resistance value of any convex quadrangle can be obtained by applying an isosceles trapezoid resistance integral formula according to the equivalent upper and lower bottom widths and the equivalent height.
Similarly, when the geometric subsegment is a triangle, the resistance value of the triangle can be obtained by referring to the resistance calculation method for calculating the convex quadrilateral, for example, the equivalent height and the equivalent base width are obtained, which is not described herein.
Capacitance calculation method of geometric subsegment:
the total capacitance of the geometric subsegment can be divided into two parts, namely the coupling capacitance between the geometric subsegment and the substrate and other layers of conductors and the coupling capacitance between the geometric subsegment and the adjacent network wires on the same layer.
The coupling capacitance between the geometrical subsection and the substrate and other layer conductors is in direct proportion to the area of the geometrical subsection, and the calculation formula is CAγ · a, wherein CACoupling capacitance between the geometrical subsection and the substrate and other layer conductors; gamma is a constant related to the process only, and can be given before the wiring is started when the process is determined; a is the area of the geometric subsection.
When the geometric subsegments are isosceles trapezoids, the widths of the upper bottom and the lower bottom of the isosceles trapezoids are respectively w0And W1High is L, thenNamely, it isIf the geometric subsegment is any quadrangle, the equivalent height L and the equivalent upper and lower bottom widths w of the geometric subsegment can be obtained by a method similar to that in resistance calculation0And w1。
The coupling capacitance between the geometrical subsection and the adjacent network wires at the left and right sides of the same layer can be estimated asWhere γ is a constant related to the process only, and is given before the process is determined and wiring is started, L0And L1 are the lengths of the left and right sides of the geometric sub-section,andrespectively, the average distance between the geometric subsection and the adjacent net lines on the left and right sides of the geometric subsection.
The total capacitance of the geometrical subsections is
The calculation method of the network cable width adjustment value comprises the following steps:
if n network cables are provided, after passing through the dividing and wiring module 20, the n network cables are divided into m sections, and the j section and the j +1 section are separated by an inner edge LjRjAnd (4) separating. The midpoint of the net line i on the inner edge j is CijTwo boundary points thereof are EijAnd Fij，Ei-1jAnd FijLet us denote H as the midpoint ofij. Obviously, E0jAre the region boundary points. Starting from 0, Fn-1jIs the region boundary point Rj。
Specifically, the step of calculating the reticle width adjustment value is as follows:
s1: and calculating the difference between the capacitance value of each network wire and the average capacitance value and storing the difference as a capacitance difference value. Specifically, the capacitance value of each network cable from the initial port to the terminal port is calculated, the average capacitance value of all network cables in the area to be wired is obtained based on the capacitance value of each network cable and is a target capacitance value, and the difference between the capacitance of each network cable and the target capacitance value is recorded and stored as a capacitance difference value delta epsiloni。
S2: and calculating the weight of each inner edge in the area to be wired. Specifically, it is assumed that the wiring region is divided into m segments, and the length of the midpoint connecting line between the inner edges of the j-th segment is denoted as SjAnd the relative weight of each inner edge is recorded as
S3: the capacitance of each geometric subsection is calculated and differentiated. The differential of the capacitance of each grid line to each geometric subsection is calculated.
fig. 6 is a schematic diagram for calculating the differential resistance of the geometric sub-section, and as shown in fig. 6, assuming that the included angles between the connecting line of the port midpoints and L1R1 and L2R2 are α and β, respectively, the equivalent widths of the two bases of the quadrangle are estimated as | L1R1 |. sin α and | L2R2 |. sin β, and the resistance is obtained by applying the isosceles trapezoid resistance calculation formulaThe derivative of | L1R1| is obtained by taking the resistance R
Similarly, by applying the capacitance calculation formula, the geometric sub-segment capacitance can be obtained as
The derivative of | L1R1| is obtained by taking the derivative of the capacitance c
when R1 moves from L1R1 to R1' in a small range along the inner edge of L1R1, L2R2 is not changed, the length C1C2 of the middle point connecting line of the quadrangle, namely the change of the equivalent length of the quadrangle, the included angles α and β, is a second-order small quantity, and can also be considered as the same, then the change of the resistance can be approximated to the change of the resistance at the momentThe change in capacitance at this time can be approximated asThis relationship is smallThe range is linear.
S4: for each inner edge, the sum of the target capacitance adjustment quantities of the two adjacent segments can be obtainedFrom the relationship obtained in step S03,
at Δ wijThe smaller the error of the equation. According toAnd Δ w can be foundijI.e. the amount of adjustment required per section of wire width.
After the adjustment amount of the width of each section of the net line is calculated according to the steps, for each inner edge j, the current position H is based onijAnd Δ w obtained in step S04ijThe new position H 'of inner edge j can be obtained'ij. Namely, it is
The inner edge j is marked by HijMove to New position H'ijsine sin α ═ min (sin sin (∠ H ]) according to the angle between the twoij-1HijLj)，sin sin(∠Hij+1HijLj) Smin) to estimate new Fij，Ei+1jAnd HijSo that a distance therebetween is
Thus obtaining all new EjjAnd Fij。
According to EijAnd FijCan ensureThe shape and position of each geometric sub-section of each wire is determined, thereby determining the shape and position of each wire.
Example four
The present embodiment specifically describes a method of wiring a capacitor.
Firstly, the information of a wiring area and a port to be wired is read, wherein the information comprises the number and the position of a starting port and a terminating port, and the size, the position and/or the shape of the wiring area. The area to be wired is divided into a series of geometric subsections. For example, the area to be wired is divided into a series geometry subsection of a triangle and two convex quadrilaterals. After the division, all the network wires distributed in the wiring area are also divided into the series of geometric subsections. And numbering each reticle and the divided geometric subsections of the reticle, and storing the calculated capacitance value, reticle width and reticle width adjustment value under the corresponding numbers.
The initial routing is started in a uniform width manner. The width of each initial wire is the same. Further, whether the initially wired network cable is completely located in the area to be wired and/or whether all the network cables are in the same metal wiring layer is detected. And detecting the shape of the geometric subsegment after each mesh wire is divided. And under the condition that the geometric subsections are not convex quadrangles and/or triangles, performing secondary segmentation on the geometric subsections so as to meet the condition that all the geometric subsections are convex quadrangles and/or triangles. For example, the vertices of the non-starting edge and the terminating edge are connected to the nearest vertex opposite thereto, thereby dividing the area to be wired into triangles or quadrilaterals.
The current capacitance value of each wire/geometric subsection is estimated. Firstly, calculating the capacitance value of each geometric sub-section and then storing the capacitance value to the number corresponding to each geometric sub-section. And calculating the capacitance value of the geometric subsection according to the equivalent height and the equivalent upper and lower bottom widths of the convex quadrangle.
The convex quadrangle is L1R1L2R2, and the distances from L1 and L2 to C1C2 are d1 and d2 respectively, and the distances from R1 and R2 to C1C2 are d1 and d2 respectively. The two equivalent base widths of the quadrilateral are then 2 x d1 and 2 x d 2. Capacitance values were calculated from 2 × d1 and 2 × d2 and C1C 2. The capacitance value of each wire in the geometric subsegment included in each wire is obtained to obtain the capacitance value of each wire in the wiring area. And after the capacitance value of each network wire is calculated, summing the capacitance values of all network wires and dividing the sum by the number of the network wires in the wiring area to obtain the average capacitance value of all network wires. And calculating the difference between the capacitance value of each grid line and the average capacitance value and recording the difference as a capacitance difference value.
And judging whether the capacitance difference value is smaller than a preset capacitance value. And if the capacitance difference value of each network wire in the area to be wired is smaller than the preset capacitance value, outputting the current wiring result. And if the capacitance difference value of at least one network wire is larger than the preset capacitance value, calculating the network wire width adjustment value of each geometric subsection according to the capacitance value and the capacitance difference value of each network wire. Assuming that n network cables are provided, after passing through the dividing and routing module 20, the n network cables are divided into m segments, and the definition of the inner edge between the jth segment and the jth +1 segment shows the solution L of the problem 10 about the segmentationjRjAnd (4) separating. The midpoint of the net line i on the inner edge j is CijTwo boundary points thereof are EijAnd Fij，Ei-1jAnd FijLet us denote H as the midpoint ofij. Obviously, E0jThat is, the region boundary points we begin counting with O, Fn-1jIs the region boundary point Rj。
And adjusting the shape and the position of the geometric subsegment according to the calculated reticle width adjustment value. And after obtaining the width adjustment value of the mesh wire, adjusting the width, the shape and/or the position of the corresponding geometric subsection, thereby realizing the adjustment of the width, the shape and/or the position of each mesh wire. And detecting the adjusted width value of the network cable and the distance between the adjacent network cables and selectively adjusting to enable the adjusted width value and the distance to meet the process parameters preset by a user. After readjusting the width, shape and/or position of the wires, the capacitance values of the adjusted geometric subsections and/or wires are recalculated. The capacitance value is compared with the preset capacitance value to selectively adjust again. And outputting the current wiring result until the capacitance difference values of all the network cables are smaller than the standard capacitance value.
It should be noted that the above-mentioned embodiments are exemplary, and that those skilled in the art, having benefit of the present disclosure, may devise various arrangements that are within the scope of the present disclosure and that fall within the scope of the invention. It should be understood by those skilled in the art that the present specification and figures are illustrative only and are not limiting upon the claims. The scope of the invention is defined by the claims and their equivalents.
Claims (9)
1. A method of equal capacitance routing, the method comprising at least:
identifying geometric parameters of a region to be wired and dividing the region to be wired into geometric subsections with a string with a unique number based on the geometric parameters;
generating initial wiring in an equal-width mode, and detecting and secondarily cutting the geometric subsections which do not meet standard conditions;
adaptively adjusting the geometric characteristics and/or positions of the corresponding geometric subsegments and/or net lines based on the comparison result of the calculated capacitance difference value of at least one geometric subsegment and/or each net line and a preset capacitance value;
the capacitance calculation method with the geometrical subsections being convex quadrangles at least comprises the following steps:
obtaining the total capacitance of the geometric subsegment based on the sum of the first coupling capacitance and the second coupling capacitance of the geometric subsegment; wherein,
calculating a first coupling capacitance between the geometric subsegment and metal wires of different wiring layers based on the area of the convex quadrangle;
and calculating a second coupling capacitance between the geometric subsegment and the adjacent network wire based on the equivalent distance between the geometric subsegment and the adjacent network wire in the same wiring layer.
2. The capacitance wiring method according to claim 1, wherein, in case the capacitance difference is larger than a preset capacitance value, a mesh width adjustment value of the corresponding geometric sub-section and/or mesh line is calculated and the geometric characteristics and/or positions of the corresponding geometric sub-section and/or mesh line are adjusted.
3. The capacitive routing method of claim 2, further comprising: and adjusting the geometric characteristics and/or positions of the corresponding geometric subsections and/or network lines again based on the comparison result of the capacitance difference values of the adjusted geometric subsections and/or network lines and the preset capacitance values.
4. The capacitor wiring method as defined in claim 1, wherein the method of dividing the area to be wired at least comprises:
finding a vertex which is not positioned on the starting edge (LORO) and/or the ending edge (L3R3), and drawing a first angle bisector (L2R2) in the to-be-routed area by the angle formed by the vertex;
and making a corresponding inner edge according to the condition that the first angle bisector (L2R2) firstly intersects one of the outer edge, the second angle bisector, the starting edge (LORO) and the ending edge (L3R3), thereby dividing the region to be wired into a convex quadrangle and/or a triangle.
5. The capacitor wiring method as defined in claim 1, wherein the method of dividing the area to be wired at least comprises:
and connecting the vertexes of the non-starting edge and the non-ending edge with at least one vertex in the opposite direction, thereby dividing the area to be wired into a triangle and/or a quadrangle.
6. The capacitance routing method of claim 2, wherein the method of calculating the grid width adjustment value for the geometry subsegment comprises:
calculating the weight of each inner edge in the area to be wired;
calculating and differentiating the capacitance of each geometric sub-segment;
and obtaining a reticle width adjustment value of the geometric subsegment according to the capacitance difference, the weight of the inner edge and the differential of the capacitance of each geometric subsegment.
7. The capacitive routing method of claim 2, further comprising: and detecting the adjusted width value of the network cable and the distance between the adjacent network cables and selectively adjusting to enable the adjusted width value and the distance to meet the process parameters preset by a user.
8. The capacitor wiring method of claim 7, further comprising: and numbering each reticle and the divided geometric subsections thereof, and storing the capacitance value, reticle width and reticle width adjustment value of each geometric subsection and/or each reticle under the corresponding number.
9. An isocapacitance wiring device, comprising:
a region identification module (10) for identifying geometric parameters of a region to be wired;
a dividing wiring module (20) for dividing the area to be wired into geometrical subsections of the string based on the geometrical parameters and generating initial wiring;
a calculation and analysis module (30) for calculating at least one geometrical subsection and/or a capacitance value per network wire;
an adjustment output module (50) for adaptively adjusting the geometrical characteristics and/or the position of the respective geometrical subsections and/or network wires based on a comparison of the capacitance value with a preset capacitance value;
the capacitance calculation method with the geometrical subsections being convex quadrangles at least comprises the following steps:
obtaining the total capacitance of the geometric subsegment based on the sum of the first coupling capacitance and the second coupling capacitance of the geometric subsegment; wherein,
calculating a first coupling capacitance between the geometric subsegment and metal wires of different wiring layers based on the area of the convex quadrangle;
and calculating a second coupling capacitance between the geometric subsegment and the adjacent network wire based on the equivalent distance between the geometric subsegment and the adjacent network wire in the same wiring layer.
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| CN104217046A (en) * | 2013-06-03 | 2014-12-17 | 绩达特软件(北京）有限公司 | Wiring method and device |
| CN105160107A (en) * | 2015-09-07 | 2015-12-16 | 成都锐开云科技有限公司 | Equal-resistance wiring method and device especially used for flat panel display |
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| CN101639867A (en) * | 2008-08-01 | 2010-02-03 | 英业达股份有限公司 | Wiring method for circuit layout and method for recording network cable names of circuit layout |
| CN104217046A (en) * | 2013-06-03 | 2014-12-17 | 绩达特软件(北京）有限公司 | Wiring method and device |
| CN105160107A (en) * | 2015-09-07 | 2015-12-16 | 成都锐开云科技有限公司 | Equal-resistance wiring method and device especially used for flat panel display |
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