CN113645161B - Direct media interface bandwidth distributor and server - Google Patents
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- CN113645161B CN113645161B CN202110853721.7A CN202110853721A CN113645161B CN 113645161 B CN113645161 B CN 113645161B CN 202110853721 A CN202110853721 A CN 202110853721A CN 113645161 B CN113645161 B CN 113645161B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/52—Queue scheduling by attributing bandwidth to queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention discloses a direct media interface bandwidth distributor and a server, comprising: a multiplexer configured to selectively turn on the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal; the central processing unit is connected to the first gating end through four paths of direct media interfaces; the platform controller concentrator is connected to the central processing unit through four direct media interfaces and is connected to the connecting end through four variable interfaces; the hard disk back plate is connected to the second gating end through four hard disk interfaces and comprises a field replaceable unit stored with the configuration of the hard disk back plate; and the substrate management controller is connected to the field replaceable unit to acquire the configuration of the hard disk backplane, and is connected to the control terminal to switch the channels conducted by the multiplexer according to the configuration of the hard disk backplane. The invention can switch DMI bandwidth based on different identified configurations, thereby improving flexibility and reducing hardware cost.
Description
Technical Field
The present invention relates to the field of data transmission, and more particularly, to a direct media interface bandwidth allocator and a server.
Background
With the rapid development of internet technology, the demand of each internet company for servers is sharply increased, and the demand of corresponding servers with high computing density and high computing efficiency is increased, but the high-density computing is often mutually limited with high bandwidth, and part of the reason is that the communication bandwidth between a CPU (central processing unit) and a PCH (platform controller hub) is low. With the advent of new generation of CPUs, the CPU on Eagle Stream platform can support at most x8 DMI (direct media interface), and can configure the register corresponding to HSIO (high speed input output interface) through BIOS (basic input output system), so as to configure the DMI bandwidth as x4 or x8.
The design scheme in the prior art can be divided into an x4 bandwidth and an x8 bandwidth, and in most designs, in order to fully improve the calculation density of the server, a design mode of the x4 bandwidth is adopted, so that the spare high 4 bits can be configured as a PCIe (peripheral equipment interconnection standard extension) or SATA (serial advanced technology attachment) interface, and the spare high 4 bits are designed as an external hard disk interface to realize that the server carries more hard disks, so that the calculation density of the whole server is improved; however, when there are many hard disk devices hanging on the PCH, the bandwidth is limited by the DMI bandwidth between the CPU and the PCH, so that the actual operation bandwidth of each hard disk also has a bottleneck, and in order to increase the hard disk allocation bandwidth, the efficiency of data operation can be increased by increasing the DMI bandwidth between the CPU and the PCH, that is, when the bandwidth is configured as the x8 bandwidth, the allocation bandwidth and the calculation capability of the hard disk hanging on the PCH can be effectively increased.
However, in the prior art, the DMI design of the server is fixed bandwidth, and cannot be automatically configured to be x4 or x8 according to the configuration, and if the configuration of different bandwidths is to be realized, two PCBs (printed circuit boards) are needed, and the board development is time-consuming and labor-consuming, and the flexibility is poor.
Aiming at the problems that DMI bandwidth configuration in the prior art is difficult to directly switch, poor in flexibility and high in hardware cost, no effective solution is available at present.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a direct media interface bandwidth allocator and a server, which can switch DMI bandwidths based on different identified configurations, thereby improving flexibility and reducing hardware cost.
In view of the above object, a first aspect of the embodiments of the present invention provides a direct media interface bandwidth allocator, including:
a multiplexer having a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal;
the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces;
the platform controller concentrator is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces;
the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit storing hard disk back plate configuration;
and the substrate management controller is connected to the field replaceable unit of the hard disk backboard to acquire the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard.
In some embodiments, the baseboard management controller is also connected to the platform controller hub to adjust an operational state of the platform controller hub according to the hard disk backplane configuration.
In some embodiments, the baseboard management controller is connected to the field replaceable unit of the hard disk backplane through an internal integrated circuit bus, connected to the control terminal of the multiplexer through a general purpose input output bus, and connected to the platform controller hub through an ESPI bus.
In some embodiments, the baseboard management controller is configured to configure registers of a high speed input output interface of the platform controller hub according to a hard disk backplane configuration.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to be four-way and configures the four-way variable interface of the platform controller hub to operate in the hard disk mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to eight-way and configures the four-way variable interface of the platform controller hub to operate in direct media mode in a register of the high-speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not functional.
In some embodiments, the baseboard management controller, while configuring the direct media interfaces of the platform controller hub to be eight-way, also causes the eight-way direct media interfaces to transmit data in parallel using their total bandwidth.
In some embodiments, the baseboard management controller signals the multiplexer to pass the first gating terminal to the connection terminal in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller signals the multiplexer to pass the second gating terminal to the connection terminal in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
A second aspect of an embodiment of the present invention provides a server, including:
a calculator;
a controller:
a memory;
a direct media interface bandwidth allocator, comprising:
a multiplexer having a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal;
the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces;
the platform controller concentrator is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces;
the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit stored with the hard disk back plate configuration;
and the substrate management controller is connected to the field replaceable unit of the hard disk backboard to obtain the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard.
In some embodiments, the baseboard management controller is also connected to the platform controller hub to adjust an operational state of the platform controller hub according to the hard disk backplane configuration.
In some embodiments, the baseboard management controller is connected to the field replaceable unit of the hard disk backplane through an internal integrated circuit bus, connected to the control terminal of the multiplexer through a general purpose input output bus, and connected to the platform controller hub through an ESPI bus.
In some embodiments, the baseboard management controller is configured to configure registers of the high-speed input output interface of the platform controller hub according to a hard disk backplane configuration.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to be four-way and configures the four-way variable interface of the platform controller hub to operate in the hard disk mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to eight-way and configures the four-way variable interface of the platform controller hub to operate in direct media mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller, while configuring the direct media interfaces of the platform controller hub to be eight-way, also causes the eight-way direct media interfaces to transmit data in parallel using their total bandwidth.
In some embodiments, the baseboard management controller signals the multiplexer to pass the first gating terminal to the connection terminal in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller signals the multiplexer to pass the second gate terminal to the connection terminal in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is valid.
The invention has the following beneficial technical effects: the direct media interface bandwidth allocator provided by the embodiment of the present invention, by using a multiplexer, has a first gating terminal, a second gating terminal, a connection terminal, and a control terminal, and is configured to selectively conduct the first gating terminal or the second gating terminal to the connection terminal based on an input signal of the control terminal; the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces; the platform controller concentrator is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces; the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit storing hard disk back plate configuration; the base plate management controller is connected to the field replaceable unit of the hard disk backboard to obtain the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard, the DMI bandwidth can be switched based on different identified configurations, the flexibility is improved, and the hardware cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a direct media interface bandwidth allocator according to the present invention;
fig. 2 is a connection diagram of the direct media interface bandwidth allocator according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a direct media interface bandwidth allocator that switches DMI bandwidths based on different identified configurations, thereby improving flexibility and reducing hardware cost. Fig. 1 is a schematic structural diagram of a first embodiment of a direct media interface bandwidth allocator provided in the present invention.
The direct media interface bandwidth allocator, as shown in fig. 1, includes:
a multiplexer having a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal;
the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces;
the platform controller hub is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces;
the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit stored with the hard disk back plate configuration;
and the substrate management controller is connected to the field replaceable unit of the hard disk backboard to obtain the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard.
The apparatuses and devices disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus and device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
In some embodiments, the baseboard management controller is also connected to the platform controller hub to adjust an operational state of the platform controller hub according to the hard disk backplane configuration.
In some embodiments, the baseboard management controller is connected to the field replaceable unit of the hard disk backplane through an internal integrated circuit bus, connected to the control terminal of the multiplexer through a general purpose input output bus, and connected to the platform controller hub through an ESPI bus.
In some embodiments, the baseboard management controller is configured to configure registers of the high-speed input output interface of the platform controller hub according to a hard disk backplane configuration.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to be four-way and configures the four-way variable interface of the platform controller hub to operate in the hard disk mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to eight-way and configures the four-way variable interface of the platform controller hub to operate in direct media mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller, while configuring the direct media interfaces of the platform controller hub to be eight-way, also causes the eight-way direct media interfaces to transmit data in parallel using their total bandwidth.
In some embodiments, the baseboard management controller signals the multiplexer to pass the first gating terminal to the connection terminal in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller signals the multiplexer to pass the second gating terminal to the connection terminal in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
The following further illustrates embodiments of the invention in accordance with the specific example shown in fig. 2.
Taking the specific configuration requirement shown in fig. 2 as an example, when a 4SATA backplane (i.e., a hard disk backplane) is supported, the DMI bandwidth needs to be configured as x4, and when the 4SATA backplane is not supported, the DMI bandwidth needs to be configured as x8. By adding PCIe MUX (multiplexer) on the PCH DMI bus, the MUX channel can be controlled according to the configuration identified by BMC (baseboard control manager), thereby realizing flexible configuration of DMI bandwidth under the condition of dual configuration.
The embodiment of the invention realizes the flexible configuration of the DMI bus bandwidth between the CPU and the PCH into x4 or x8 by adding the PCIe MUX circuit; when the 4SATA back plate is supported, the DMI bandwidth needs to be configured to be x4, and when the 4SATA back plate is not supported, the DMI bandwidth needs to be configured to be x8.
First, the back plane is designed with an FRU and stores related asset information such as back plane configuration. The BMC at the mainboard end supports communication with the backboard through an I2C bus and can normally read and analyze asset information stored in an FRU (field replaceable unit) of the backboard, so that board configuration is identified. The BMC supports ESPI communication with the PCH, identified board configuration information can be transmitted to the PCH, and the PCH can normally analyze and configure HSIO related registers. The PCIe MUX is designed on the PCH DMI bus. As shown in FIG. 2, the Y channel is connected to the PCH, the A channel is connected to the CPU, and the B channel is connected to the backplane. The MUX supports the highest Gen4 rate and has a Sel (control) pin, here controlled by the BMC.
When the BMC recognizes that the backboard is configured, the MUX is gated to Y = B, and the PCH is informed to perform register configuration through an ESPI bus, wherein the DMI bandwidth is configured to be x4; when the BMC identifies that no backplane configuration exists, the MUX is gated to Y = A, at this time, the PCH receives information transmitted by the ESPI bus and configures the HSIO register, the high 4 bits are configured to be in a DMI mode, namely, the DMI bandwidth is configured to be x8 at this time, and high-bandwidth communication between the CPU and the PCH is achieved. Therefore, the BMC reads FRUs of the back plate under specific configuration through the I2C bus and can identify different configurations, so that the MUX is controlled to switch channels through the GPIO, the communication with the PCH is realized through the ESPI bus, and the configuration of the PCH corresponding to the HSIO mode is realized through the BIOS.
As can be seen from the foregoing embodiments, the direct media interface bandwidth allocator according to the embodiments of the present invention, by using a multiplexer, has a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, and is configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal; the central processing unit is connected to a first gating end of the multiplexer through four paths of direct media interfaces; the platform controller concentrator is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces; the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit stored with the hard disk back plate configuration; the base plate management controller is connected to the field replaceable unit of the hard disk backboard to obtain the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard, the DMI bandwidth can be switched based on different identified configurations, the flexibility is improved, and the hardware cost is reduced.
In view of the foregoing, a second aspect of the embodiments of the present invention provides an embodiment of a server that switches DMI bandwidths based on different identified configurations, so as to improve flexibility and reduce hardware cost. The server includes:
a calculator;
a controller:
a memory;
a direct media interface bandwidth allocator, comprising:
a multiplexer having a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal;
the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces;
the platform controller hub is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces;
the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit storing hard disk back plate configuration;
and the substrate management controller is connected to the field replaceable unit of the hard disk backboard to acquire the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard.
In some embodiments, the baseboard management controller is also connected to the platform controller hub to adjust an operational state of the platform controller hub according to the hard disk backplane configuration.
In some embodiments, the baseboard management controller is connected to the field replaceable unit of the hard disk backplane through an internal integrated circuit bus, connected to the control terminal of the multiplexer through a general purpose input output bus, and connected to the platform controller hub through an ESPI bus.
In some embodiments, the baseboard management controller is configured to configure registers of a high speed input output interface of the platform controller hub according to a hard disk backplane configuration.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to four-way in a register of the high speed input output interface of the platform controller hub and configures the four-way variable interface of the platform controller hub to operate in hard disk mode in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
In some embodiments, the baseboard management controller configures the direct media interface of the platform controller hub to eight-way and configures the four-way variable interface of the platform controller hub to operate in direct media mode in a register of the high speed input output interface of the platform controller hub in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
In some embodiments, the baseboard management controller, while configuring the direct media interfaces of the platform controller hub to be eight-way, also causes the eight-way direct media interfaces to transmit data in parallel using their total bandwidth.
In some embodiments, the baseboard management controller signals the multiplexer to pass the first gating terminal to the connection terminal in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not functional.
In some embodiments, the baseboard management controller signals the multiplexer to pass the second gate terminal to the connection terminal in response to the configuration obtained from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is valid.
As can be seen from the foregoing embodiments, the server provided in the embodiments of the present invention, by using a multiplexer, has a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, and is configured to selectively conduct the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal; the central processing unit is connected to the first gating end of the multiplexer through four paths of direct media interfaces; the platform controller hub is connected to the central processing unit through four direct media interfaces and is connected to the connecting end of the multiplexer through four variable interfaces; the hard disk back plate is connected to a second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit storing hard disk back plate configuration; the base plate management controller is connected to the field replaceable unit of the hard disk backboard to obtain the configuration of the hard disk backboard, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backboard, the DMI bandwidth can be switched based on different identified configurations, the flexibility is improved, and the hardware cost is reduced.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A direct media interface bandwidth allocator, comprising:
a multiplexer having a first gate terminal, a second gate terminal, a connection terminal, and a control terminal, configured to selectively conduct either the first gate terminal or the second gate terminal to the connection terminal based on an input signal of the control terminal;
a central processor connected to the first gating terminal of the multiplexer through a four-way direct media interface;
a platform controller hub connected to the central processor through a four-way direct media interface and connected to the connection end of the multiplexer through a four-way variable interface;
the hard disk back plate is connected to the second gating end of the multiplexer through four hard disk interfaces and comprises a field replaceable unit storing hard disk back plate configuration;
and the substrate management controller is connected to the field replaceable unit of the hard disk backplane to acquire the configuration of the hard disk backplane, and is connected to the control end of the multiplexer to switch the channel conducted by the multiplexer according to the configuration of the hard disk backplane.
2. The dispenser of claim 1, wherein the baseboard management controller is further coupled to the platform controller hub to adjust an operational state of the platform controller hub according to the hard disk backplane configuration.
3. The dispenser of claim 2, wherein the baseboard management controller is coupled to the field replaceable unit of the hard disk backplane via an inter-integrated circuit bus, to the control terminal of the multiplexer via a general purpose input output bus, and to the platform controller hub via an ESPI bus.
4. The splitter of claim 2, wherein a baseboard management controller is configured to configure registers of a high speed input output interface of the platform controller hub according to the hard disk backplane configuration.
5. The dispenser of claim 4, wherein the baseboard management controller configures the direct media interface of the platform controller hub to be four-way in the register of the high speed input output interface of the platform controller hub and configures the four-way variable interface of the platform controller hub to operate in a hard disk mode in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
6. The dispenser of claim 4, wherein the baseboard management controller configures the direct media interface of the platform controller hub to eight ways in the register of the high speed input output interface of the platform controller hub and configures the four-way variable interface of the platform controller hub to operate in direct media mode in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not functional.
7. The splitter of claim 6, wherein the baseboard management controller is configured to configure the direct media interfaces of the platform controller hub to be eight-way while also having the eight-way direct media interfaces transmit data in parallel using their total bandwidth.
8. The dispenser of claim 1, wherein the baseboard management controller signals the multiplexer to pass the first gating terminal to the connection terminal in response to the configuration retrieved from the field replaceable unit of the hard disk backplane indicating that the hard disk backplane is not active.
9. The dispenser of claim 1, wherein the baseboard management controller signals the multiplexer to pass the second gating terminal to the connection terminal in response to the configuration retrieved from the field-replaceable unit of the hard disk backplane indicating that the hard disk backplane is active.
10. A server, comprising:
a calculator;
a controller;
a memory;
the direct media interface bandwidth allocator of any of claims 1-9.
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| CN202110853721.7A CN113645161B (en) | 2021-07-28 | 2021-07-28 | Direct media interface bandwidth distributor and server |
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| CN202110853721.7A CN113645161B (en) | 2021-07-28 | 2021-07-28 | Direct media interface bandwidth distributor and server |
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