CN214376439U

CN214376439U - Data processing system and server with built-in data processing system

Info

Publication number: CN214376439U
Application number: CN202122192512.0U
Authority: CN
Inventors: 魏茂强
Original assignee: Ziguang Hengyue Technology Co Ltd
Current assignee: Ziguang Hengyue Technology Co Ltd
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2021-10-08
Anticipated expiration: 2031-09-10

Abstract

The utility model provides a data processing system and built-in server of this system, data processing system includes CPU chip 1, CPU chip 2, CPLD logic device, PCIE Switch chip and BMC veneer, CPU chip 1 with CPLD logic device passes through GPIO bus connection, CPU chip 1 passes through FIT0 interface, FIT1 interface, FIT2 interface, FIT3 interface connection, CPU chip 1 pass through PCIE0X16 interface with PCIE Switch chip connects, CPU chip 1 is connected with the BMC veneer through PCIE0X1 interface, SI NC interface, the utility model discloses the server of writing has following advantage: the method has the advantages of high-performance calculation, large-capacity storage, low energy consumption, easy management, easy deployment and the like.

Description

Data processing system and server with built-in data processing system

Technical Field

The utility model belongs to data processing, concretely relates to data processing system and built-in this system's server.

Background

A server is one of computers that runs faster, is more heavily loaded, and is more expensive than a regular computer. The server provides calculation or application services for other clients (such as terminals like PC, smart phone, ATM and the like and even large equipment like train systems and the like) in the network. The server has high-speed CPU computing capability, long-time reliable operation, strong I/O external data throughput capability and better expansibility. Generally, a server has the capability of responding to a service request, supporting a service, and guaranteeing the service according to the service provided by the server. The server is used as an electronic device, and the internal structure of the server is very complex, but the difference with the internal structure of a common computer is not great, such as: cpu, hard disk, memory, system bus, etc.

The utility model provides a rack-mounted server has following characteristics: 1. best homemade IT infrastructure platform: aiming at the requirements of the fields of cloud computing, telecommunication, finance, enterprise users and the like on the server, the dual-path high-end server designed based on the domestic Feiteng server CPU has the advantages of stronger performance, stronger virtualization capability, superior expansion capability and higher cost performance; 2. outstanding performance, flexible design: the FT2500 CPU is configured, the configuration of double CPUs can reach 128 kernels and 16 DIMM slots, the maximum 10 PCIe slots and 1 OCP3.0 interface are supported, and excellent and flexible computing and interface expansion capability is provided for customers; 3. the storage configuration is rich: the method supports the scheme of the front-end hard disk and the rear-end hard disk, supports various hard disk configurations, provides rich storage configuration scheme selections for customers through brand-new flexible design, and meets the requirements of different storage capacities and upgrading requirements; 4. the whole solution is as follows: the system can provide full-integration management of cross-server, storage, network and virtualization, simplify deployment and installation, and optimize operation and maintenance management.

The utility model provides a server is the rack-mounted server based on FT2500 treater, and 2U height supports double-circuit CPU. The server faces the fields of cloud computing, big data, the Internet, telecommunication, enterprise business and the like, and has the advantages of high-performance computing, large-capacity storage, low energy consumption, easiness in management, easiness in deployment and the like.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a data computing system and built-in this data computing system's server aims at satisfying the demand in fields such as cloud computing, big data, internet, telecommunications, enterprise business.

In order to realize the above-mentioned purpose, the utility model provides a data processing system, data processing system includes CPU chip 1, CPU chip 2, CPLD logic device, PCIE Switch chip and BMC veneer, CPU chip 1 with CPLD logic device passes through GPIO bus connection, CPU chip 1 pass through LPC interface, UART interface, SPI0 interface with CPLD logic device connects, CPU chip 1 passes through FIT0 interface, FIT1 interface, FIT2 interface, FIT3 interface connection, CPU chip 1 pass through PCIE0X16 interface with PCIE Switch chip connects, CPU chip 1 passes through PCIE0X1 interface, NC interface and is connected with the veneer, the BMC veneer passes through the Lbus interface, LPC interface, SPI1 interface and is connected with CPLD logic device.

Further, the CPU chip 1 is provided with a memory controller, and the memory controller is connected to 8 DDR4 memory banks; the CPU chip 2 is provided with a memory controller, the memory controller is connected with 8 DDR4 memory banks, the CPU chip 1 is connected with a change-over switch through an I2_ C interface, and the change-over switch is connected with an RTC chip.

Further, the CPLD logic device is connected with the CPU chip 2 through an SPI0 interface; the CPLD logic device is connected with the ROM chip 0 and the ROM chip 1; the CPLD logic device is connected with the RJ45W network port.

Further, the BMC single board is connected with a switch through an I2_ C interface, and the switch is connected with the RTC chip; the BMC single board is connected with the trusted password module through an SPI2 interface; the BMC single board is connected with the DDR particles through an MMU interface; the BMC single board is connected with the ROM chip 3 through an SPI interface; the BMC single board is connected with the NAND storage medium through an eMMC interface; the BMC single board is connected with a selector switch through an eMMC interface, and the selector switch is connected with the NAND storage medium.

Further, the BMC board is connected to the EEPROM interface through an I2C interface, the BMC board is connected to the PHY chip 1 through an RGMII interface, the PHY chip 1 is connected to the management network port, the BMC board is connected to the switcher through a VGA interface, the switcher is connected to the front VGA interface and the rear VGA interface, and the BMC board is connected to the Type-c interface through a USB interface.

Further, the BMC board is connected to a USB controller through an NCSI interface, the USB controller is connected to a PCIE Switch chip, the USB controller is connected to a USB interface, the USB controller is connected to a USB HUB chip, and the USB HUB chip is connected to a USB interface.

Further, the BMC board is connected to a switch through an NCSI interface, and the switch is connected to the PHY chip 2 and the OCP interface.

Further, the PCIE Switch chip is connected to the PHY chip 2, the Pcle extended Riser1 card, and the Pcle extended Riser2 card, and the PHY chip 2 is connected to the gigabit interface.

Further, the CPU chip 2 is connected to 2 Slim SAS interfaces via PCIE0X16 interfaces, and the Slim SAS interfaces are connected to a Pcle expansion Riser3 card; the CPU chip 2 is connected with the SATA controller through a PCIE0X1 interface, and the SATA controller is connected with the SSD.

Further, the server comprises at least one data processing system as described above.

Compared with the prior art, the utility model discloses the server that records has following advantage: the method has the advantages of high-performance calculation, large-capacity storage, low energy consumption, easy management, easy deployment and the like.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a logic structure diagram of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides the logic structure diagram of the present invention.

The utility model provides a data processing system, it includes CPU chip 1, CPU chip 2, CPLD logic device, PCIE Switch chip and BMC veneer, CPU chip 1 with CPLD logic device passes through GPIO bus connection, CPU chip 1 pass through LPC interface, UART interface, SPI0 interface with CPLD logic device connects, CPU chip 1 passes through FIT0 interface, FIT1 interface, FIT2 interface, FIT3 interface connection, CPU chip 1 pass through PCIE0X16 interface with PCIE Switch chip connects, CPU chip 1 passes through PCIE0X1 interface, NC SI interface and veneer is connected, the BMC veneer passes through Lbus interface, LPC interface, SPI1 interface and is connected with CPLD logic device.

The CPU chip 1 and the CPU chip 2 adopt a Feiteng cloud S2500 CPU chip, the data processing system integrates two Feiteng cloud S2500 CPUs, the CPUs are directly connected through 4 groups of high-speed FIT buses, each group has 4 channels, and the maximum speed is 25 GT/S. The two CPUs work cooperatively to realize the functions of system management, high-speed operation and the like. A single CPU provides 8 DDR4 RDIMM memory interfaces, and the highest speed supports 3200 MT/s. In addition, each CPU also provides 1X 16PCIe interface and 1X 1 PCIe interface to provide service expansion capability for the system. The X16PCIe interface of the CPU0 is connected to a PCIe Switch chip, and the X1 PCIe interface is connected to the BMC for realizing VGA display. An X16PCIe interface of the CPU1 provides two SlimSAS interfaces on a mainboard, and an X1 PCIe interface is connected to the SATA controller chip 88SE9230 for externally providing 2 M.2 SATA interfaces.

The AST2500 circuit is used for a remote management module of a server BMC single board, realizes the functions of detecting the working state of the single board, controlling the operation of the single board and the like, and provides rich interfaces for the outside. The VGA interface is matched with an VGASWITCH chip to realize double VGA design and is respectively used for VGA display of front and rear panels of the server. The RGMII interface connects to the gigabit PHY chip 88E1512 to provide a dedicated management portal. The NCSI interface is matched with an I350 kilomega network port PHY chip to externally provide two sharing management network ports. The SPI is used for connecting the BMC and the BIOS Flash storage medium to realize the management and the upgrade of the system firmware. The I2C interface is connected with each sensor circuit of the single board and is used for detecting the working state of the single board. And the PWM interface is used for realizing the rotation speed control of the BMC on the system fan.

The CPLD logic device and the BMC are communicated through a Local Bus and are used for realizing the functions of power-on and power-off control, reset control, interrupt management, state query of the single board device and the like.

The PCIe Switch chip adopts PEX8796, and 96 signal channels are adopted in total, so that the PCIe expansion function is realized. The uplink 1 group X16 interface is connected with the CPU0, the downlink 2 group X32 interface is connected with the PCIe expansion Riser card, the 1 group X8 interface is connected with the OCP interface, and the rest PCIe signal interfaces are connected with the gigabit network port PHY chip and the USB controller.

A server is provided comprising at least the data processing system described above. And taking a circuit board inside the server as a carrier. The other hardware configuration of the server is not particularly limited. The utility model provides a server has the relevant necessary hardware structures such as shell, antenna that general server possessed.

The embodiments described above are only a part of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated herein and in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other changes or substitutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Claims

1. A data processing system is characterized by comprising a CPU chip 1, a CPU chip 2, a CPLD logic device, a PCIE Switch chip and a BMC single board, wherein the CPU chip 1 is connected with the CPLD logic device through a GPIO bus, the CPU chip 1 is connected with the CPLD logic device through an LPC interface, a UART interface and an SPI0 interface, the CPU chip 1 is connected with the PCLD logic device through an FIT0 interface, an FIT1 interface, an FIT2 interface and an FIT3 interface, the CPU chip 1 is connected with the PCIE Switch chip through a PCIE0X16 interface, the CPU chip 1 is connected with the BMC single board through a PCIE0X1 interface and an NC SI interface, and the single board is connected with the CPLD logic device through an Lbus interface, an LPC interface and an SPI1 interface.

2. The data processing system of claim 1, wherein the CPU chip 1 is provided with a memory controller, and the memory controller is connected with 8 DDR4 memory banks; the CPU chip 2 is provided with a memory controller, the memory controller is connected with 8 DDR4 memory banks, the CPU chip 1 is connected with a change-over switch through an I2_ C interface, and the change-over switch is connected with an RTC chip.

3. The data processing system according to claim 1 or 2, wherein the CPLD logic device is connected to the CPU chip 2 through an SPI0 interface; the CPLD logic device is connected with the ROM chip 0 and the ROM chip 1; the CPLD logic device is connected with the RJ45W network port.

4. The data processing system of claim 1, wherein the BMC board is connected to a switch through an I2_ C interface, and the switch is connected to an RTC chip; the BMC single board is connected with the trusted password module through an SPI2 interface; the BMC single board is connected with the DDR particles through an MMU interface; the BMC single board is connected with the ROM chip 3 through an SPI interface; the BMC single board is connected with the NAND storage medium through an eMMC interface; the BMC single board is connected with a selector switch through an eMMC interface, and the selector switch is connected with the NAND storage medium.

5. The data processing system of claim 1 or 4, wherein the BMC board is connected to the EEPROM interface through an I2C interface, the BMC board is connected to the PHY chip 1 through an RGMII interface, the PHY chip 1 is connected to the management network port, the BMC board is connected to the switch through a VGA interface, the switch is connected to the front VGA interface and the rear VGA interface, and the BMC board is connected to the Type-c interface through a USB interface.

6. The data processing system of claim 5, wherein the BMC board is connected to a USB controller via an NCSI interface, the USB controller is connected to a PCIE Switch chip, the USB controller is connected to a USB interface, the USB controller is connected to a USB HUB chip, and the USB HUB chip is connected to a USB interface.

7. The data processing system of claim 6, wherein the BMC board is connected to a switch via an NCSI interface, and the switch is connected to the PHY chip 2 and the OCP interface.

8. The data processing system of claim 7, wherein the PCIE Switch chip is connected to PHY chip 2, a Pcle extended Riser1 card, and a Pcle extended Riser2 card, and the PHY chip 2 is connected to a gigabit port.

9. The data processing system of claim 1 or 8, wherein the CPU chip 2 is connected to 2 Slim SAS interfaces via a PCIE0X16 interface, and the Slim SAS interfaces are connected to a Pcle expansion Riser3 card; the CPU chip 2 is connected with the SATA controller through a PCIE0X1 interface, and the SATA controller is connected with the SSD.

10. A server, characterized in that it comprises at least a data processing system according to any one of claims 1 to 9.