CN113644138A - Single layer MoS2-Si-based tunneling diode and preparation method thereof - Google Patents
Single layer MoS2-Si-based tunneling diode and preparation method thereof Download PDFInfo
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- CN113644138A CN113644138A CN202110686636.6A CN202110686636A CN113644138A CN 113644138 A CN113644138 A CN 113644138A CN 202110686636 A CN202110686636 A CN 202110686636A CN 113644138 A CN113644138 A CN 113644138A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
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Abstract
The invention discloses a single-layer MoS2A-Si-based tunneling diode and a preparation method thereof relate to the technical field of semiconductors, and the method comprises the following steps: providing a first substrate, and preparing SiO on one side surface of the first substrate2An isolation region to obtain a first substrate structure; obtaining a second substrate comprising a pre-grown single-layer MoS2(ii) a Single layer MoS using epitaxial layer transfer techniques2Transferring to a first surface; patterning the single-layer MoS2Forming a single layer of MoS2A channel layer; depositing a first electrode and a second electrode on the first surface to make the second electrode and SiO2Isolation region and single-layer MoS2The channel layer is in direct contact with the substrate to obtain a single-layer MoS2-a Si-based tunneling diode. The invention provides a single-layer MoS2The Si-based tunneling diode and the preparation method thereof can reduce the interface defect density, further inhibit trap-assisted tunneling and improve the subthreshold swing of the device from the process perspective.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a single-layer MoS2-Si-based tunneling diode and preparation method thereof.
Background
As the feature size of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device gradually reaches deep submicron, a short channel Effect appears, which causes a leakage current to rise, and further increases the power consumption of the device and reduces the reliability, so that an ultra-steep device needs to be pursued. However, the sub-threshold swing of the MOSFET cannot break through the limit of 60mV/dec at room temperature due to boltzmann tail effect, which is determined by the conduction mechanism of the MOSFET using hot electron transport, so that an ultra-steep device seeking a new mechanism is not slow.
In the related art, a new device TFET (Tunneling Field-Effect Transistor) has attracted much attention. The TFET works on the principle of band-to-band tunneling, so that the TFET can get rid of the influence of Boltzmann tailing effect, and has steeper subthreshold slew rate and excellent off-state characteristics. However, in material selection, the conventional Si-based TFET has low tunneling efficiency due to the properties of indirect bandgap and large forbidden bandwidth, and the bipolar effect is also significant for the homogeneous tunneling junction, which degrades the subthreshold swing rate and off-state characteristics. In addition, the heterojunction energy band structure forming the II-type energy band structure is the most ideal tunneling junction, but the heterojunction formed by the bulk material in the traditional sense has a series of problems of serious lattice mismatch, trap-assisted tunneling and the like, and further causes poor device performance.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a single-layered MoS2-Si-based tunneling diode and preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a single-layer MoS2A method of making a-Si based tunneling diode, comprising:
providing a first substrate, and preparing SiO on one side surface of the first substrate2An isolation region to obtain a first substrate structure; the first substrate structure comprises a first surface and a second surface which are oppositely arranged along a first direction, and the first direction is vertical to a plane where the first substrate structure is located;
obtaining a second substrate comprising a pre-grown single-layer MoS2；
Applying the single-layer MoS by epitaxial layer transfer printing technology2Transferring to the first surface;
patterning the single-layer MoS2Forming a single layer of MoS2A channel layer; the single-layer MoS2The orthographic projection of the channel layer in the first direction covers at least part of a first boundary, and the first boundary is the SiO2The orthographic projection of a contact surface of the isolation region and the first substrate on a plane where the first substrate structure is located is formed, wherein the contact surface is perpendicular to the plane where the first substrate structure is located;
depositing a first electrode and a second electrode on the first surface to make the second electrode and the SiO2Isolation region and single-layer MoS2The channel layer is in direct contact with the substrate to obtain a single-layer MoS2-a Si-based tunneling diode.
In one embodiment of the invention, the first substrate is provided, and SiO is prepared on one side surface of the first substrate2An isolation region, a step of obtaining a first substrate structure, comprising:
providing a first substrate;
etching a side surface of the first substrate to form a pattern area;
depositing SiO on the side surface etched with the pattern region2And depositing SiO2Polishing the first substrate to form SiO2And (5) isolating the region to obtain a first substrate structure.
In one embodiment of the inventionIn examples, the SiO2The thickness of the isolation region in the first direction is h, wherein the thickness is 1 μm<h<10μm。
In one embodiment of the present invention, the first substrate is a silicon substrate, and the second substrate is a sapphire substrate.
In one embodiment of the invention, the single-layer MoS is transferred by using an epitaxial layer transfer technology2A step of transferring to the first surface comprising:
in the pre-grown single layer MoS2Spin-coating a polymethyl methacrylate (PMMA) solution on the surface of one side far away from the second substrate, and baking by using a hot plate to solidify the polymethyl methacrylate solution;
with cured PMMA/single layer MoS2Immersing a second substrate of the film into deionized water, and preserving heat after heating to a preset temperature;
removing the cured PMMA/monolayer MoS from the deionized water2A second substrate of thin film, PMMA/single layer MoS by mechanical stripping2Separating the thin film from the second substrate and applying PMMA/monolayer MoS2Transferring the thin film to a first surface of the first substrate structure;
baking the PMMA/single layer MoS by a hot plate2Single layer MoS in thin films2Attaching to the first surface;
with cured PMMA/single layer MoS2Placing the first substrate structure of the film into an acetone solution, removing PMMA, and then soaking the PMMA with ethanol;
removal of MoS with monolayer from ethanol2And cleaning the first substrate structure by using deionized water.
In one embodiment of the present invention, the patterning the single layer MoS2Forming a single layer of MoS2A channel layer step, comprising:
in the single layer MoS2Spin-coating photoresist on the surface of one side far away from the first substrate structure, exposing and developing to leave a photoresist mask of a first preset area, and etching the single-layer MoS2Forming a single layer of MoS2And a channel layer.
In one embodiment of the invention, the first electrode and the second electrode are formed on the first surface by deposition, and the second electrode is connected with the SiO2Isolation region and single-layer MoS after patterning2Direct contact to obtain the finished single-layer MoS2-a step of Si-based tunneling diode, comprising:
spin-coating a photoresist on the first surface, and after exposure and development, leaving a photoresist mask in a second preset area;
depositing nickel/titanium/gold on the first surface by using electron beam evaporation, and stripping redundant nickel/titanium/gold in the range of the second preset area to form a first electrode and a second electrode to obtain the manufactured single-layer MoS2-a Si-based tunneling diode; wherein the second electrode and the single layer MoS2Channel layer and the SiO2The isolation regions are in direct contact.
In one embodiment of the invention, the thickness of nickel is 80nm, the thickness of titanium is 20nm and the thickness of gold is 50nm along the first direction.
In a second aspect, the present invention provides a single layer MoS2-a Si-based tunneling diode, made by the method of any one of the above first aspects.
Compared with the prior art, the invention has the beneficial effects that:
1. the single-layer MoS provided by the invention2In the preparation method of the-Si-based tunneling diode, a single-layer MoS is prepared on a first substrate by adopting an epitaxial layer transfer printing technology2The channel layer is used for forming a Van der Waals heterojunction, so that the mismatch of thermal expansion coefficients can be relieved to a certain extent, the interface defect density is reduced, the trap-assisted tunneling is further inhibited, and the subthreshold swing of the device is improved from the process angle.
2. The invention prepares single-layer MoS by epitaxial layer transfer printing technology2The channel layer is combined with the structure of the device, and the formed tunneling diode is of a planar structure, so that the alignment, electrode isolation and device interconnection of the triode device can be realized on the basis, and a high-performance heterogeneous integrated system can be realized.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a single-layer MoS according to an embodiment of the present invention2A schematic flow diagram of a method for manufacturing a Si-based tunneling diode;
FIG. 2 is a schematic diagram of the preparation of single-layer MoS according to an embodiment of the present invention2-a process schematic of a Si-based tunneling diode;
FIG. 3 is a schematic diagram of the preparation of single-layer MoS according to an embodiment of the present invention2-another process schematic of a Si-based tunneling diode;
FIG. 4 is a schematic diagram of the preparation of single-layer MoS according to an embodiment of the present invention2-another process schematic of a Si-based tunneling diode;
FIG. 5 is a schematic diagram of the preparation of single layer MoS according to an embodiment of the present invention2-another process schematic of a Si-based tunneling diode;
FIG. 6 is a schematic diagram of the preparation of single layer MoS according to an embodiment of the present invention2-another process schematic of a Si-based tunneling diode;
FIG. 7 is a single-layer MoS provided by an embodiment of the present invention2-a schematic structural diagram of a Si-based tunneling diode;
FIG. 8 is a single-layer MoS provided by an embodiment of the present invention2-top view of a Si-based tunneling diode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
FIG. 1 is a single-layer MoS according to an embodiment of the present invention2A schematic flow chart of a method for preparing a-Si-based tunneling diode, and fig. 2-6 are diagrams of a method for preparing a single-layer MoS according to an embodiment of the present invention2FIG. 7 is a schematic process diagram of a Si-based tunneling diode, and a single-layer MoS provided by an embodiment of the present invention2Schematic structural diagram of a Si-based tunneling diode. Referring to FIGS. 1-7, the present invention provides a single-layer MoS2A method of making a-Si based tunneling diode, comprising:
s1, providing a first substrate 101, and preparing SiO on one side surface of the first substrate 1012 Isolation region 102, getA substrate structure 10; wherein, along a first direction x, the first substrate structure 10 comprises a first surface s1 and a second surface s2 which are oppositely arranged, the first direction x is perpendicular to the plane of the first substrate structure 10;
s2, obtaining a second substrate 201, wherein the second substrate 201 comprises a single-layer MoS obtained through pre-growth2202；
S3, single-layer MoS by epitaxial layer transfer technology 2202 to the first surface s 1;
s4 patterned single-layer MoS 2202, forming a single layer of MoS2 A channel layer 103; single layer MoS2An orthographic projection of the channel layer 103 in the first direction x covers at least part of the first boundary L1, the first boundary L1 being SiO2An orthographic projection of a contact surface s3 of the isolation region 102 and the first substrate 101 on a plane where the first substrate structure 10 is located, wherein the contact surface s3 is perpendicular to the plane where the first substrate structure 10 is located;
s5, depositing a first electrode 1041 and a second electrode 1042 on the first surface S1, and contacting the second electrode 1042 with SiO2Isolation region 102 and single-layer MoS2The channel layer 103 is in direct contact to obtain a fabricated single-layer MoS2-a Si-based tunneling diode.
Illustratively, the first substrate 101 is a heavily P-doped Si substrate with a crystal orientation of<100>The doping concentration is 1 x 1020～1×1021cm-3. As shown in FIG. 2, SiO is prepared on one side surface of a first substrate 1012 Isolation regions 102 forming a first substrate structure 10, i.e. the first substrate structure 10 comprises a first substrate 101 and SiO2Isolation regions 102. Wherein the first substrate structure 10 comprises a first surface s1 and a second surface s2, SiO, oppositely arranged in the first direction x2The isolation region 102 is located at the side of the first surface s1 of the first substrate structure 10.
Referring to fig. 3, in step S2, the second substrate 201 is a sapphire substrate, and MoS may be deposited on the sapphire substrate by chemical vapor deposition2Thereby obtaining single-layer MoS with better quality 2202. Of course, in some other embodiments of the invention, a second substrate of other material may be selected, and the inventionThe invention is not limited in this regard.
Further, as shown in fig. 4 to 5, a single layer MoS grown in advance on the second substrate 201 is transferred by an epitaxial layer transfer technique2Transferred to the first surface s1 of the first substrate structure 10, a single layer MoS2An orthographic projection in a direction covers the first substrate structure 10; and then patterning the single-layer MoS2Forming a single layer of MoS2 A channel layer 103 of a single layer MoS in a top view as shown in FIG. 62An orthographic projection of the channel layer 103 in the first direction x covers at least part of the first boundary L1, the first boundary L1 being SiO2The orthographic projection of the contact surface s3 of the isolation region 102 and the first substrate 101 on the plane of the first substrate structure 10 is, and the contact surface s3 is perpendicular to the plane of the first substrate structure 10.
In this embodiment, a single-layer MoS may be used2The channel layer 103104 is etched to form a stripe shape, and the area of the stripe shape may be etched according to the area of the channel layer 103 required by the device, which is not limited in the present invention.
As shown in fig. 7-8, in the step S5, a first electrode 1041 and a second electrode 1042 are deposited on the first surface S1 of the first substrate structure 10, wherein the second electrode 1042 and the SiO layer are deposited thereon2 Isolation region 102 and single-layer MoS2The channel layers 103 are all in direct contact, resulting in a fabricated single-layer MoS2-a Si-based tunneling diode.
In one aspect, the embodiment employs an epitaxial layer transfer technique to prepare a single layer MoS on the first substrate 1012The channel layer 103, not only can avoid growing a single layer of MoS directly on the first substrate 1012Interface defects caused by the channel layer 103 to prevent single-layer MoS2The channel layer 103 has degraded film quality, and can also alleviate lattice mismatch to a certain extent, reduce interface defect density, thereby inhibiting trap-assisted tunneling and improving the subthreshold swing of the device from the process perspective. On the other hand, the preparation method provided in this embodiment is to prepare a planar tunneling diode by combining the structure of the tunneling device and the channel layer 103 prepared by the epitaxial layer transfer printing technology, and the planar structure is favorable for realizing a triode deviceAlignment, electrode isolation and device interconnection, thereby facilitating the implementation of high-performance heterogeneous integrated systems.
Alternatively, in the above step S1, the first substrate 101 is provided, and SiO is prepared on one side surface of the first substrate 1012The isolation region 102, the step of obtaining the first substrate structure 10, comprises:
providing a first substrate 101;
etching a side surface of the first substrate 101 to form a pattern region;
depositing SiO on the side surface etched with the pattern region2And depositing SiO2The first substrate 101 is polished to form SiO2 isolation regions 102, resulting in the first substrate structure 10.
Specifically, a pattern region is formed by etching on a side surface of the first substrate 101, and the pattern region is a groove recessed toward a side close to the second surface s2 of the first substrate structure 10, and optionally, an orthographic projection of the groove in a direction is a square with a dimension of 150 × 150 μm. Further, depositing an oxide layer, namely SiO on the surface of one side etched with the pattern area by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method at the temperature of 250-450 DEG C2. During the deposition process, SiO2Will overflow the pattern region and cover a part of the first substrate 101, so that a Chemical Mechanical Polishing (CMP) process is further used to polish the SiO2Thereby ensuring the SiO obtained by the preparation2The contact s3 between the isolation region 102 and the first substrate 101 is completely exposed.
It should be understood that SiO2The isolation region 102 functions to block a conductive path between the metal electrode and the first substrate 101, and is limited by the manufacturing process, i.e. SiO2Isolation region 102 cannot be made too thick, but if SiO2If the isolation region 102 is made too thin, SiO is present2The risk of breakdown. Therefore, as shown in FIG. 2, the thickness h of the SiO2 isolation region 102 in the first direction x is set to 1-10 μm in the present embodiment, for example, SiO2The thickness of the isolation region 102 in the first direction x is 5 μm, 6 μm or 8 μm, which not only makes it possible to form SiO2Isolation region 102 fully develops electricityThe isolation effect can also reduce the process difficulty and save the manufacturing cost.
Alternatively, in the above step S3, the single-layer MoS is transferred by an epitaxial layer transfer technique2A step of transfer to a first surface s1, comprising:
in the pre-grown monolayer MoS2Spin-coating a polymethyl methacrylate (PMMA) solution on the surface of one side far away from the second substrate 201, and baking by using a hot plate to solidify the polymethyl methacrylate solution;
with cured PMMA/single layer MoS2Immersing the second substrate 201 of the film in deionized water, and preserving heat after heating to a preset temperature;
removal of the solid PMMA/monolayer MoS from the deionized Water2Second substrate 201 of thin film, PMMA/single layer MoS by mechanical stripping2The thin film is separated from the second substrate 201 and PMMA/single layer MoS is formed2The film is transferred to the first surface s1 of the first substrate structure 10;
baking PMMA/single layer MoS by hot plate2Single layer MoS in thin films2To the first surface s 1;
with cured PMMA/single layer MoS2Placing the first substrate structure 10 of the film into an acetone solution, removing PMMA, and then soaking the PMMA with ethanol;
removal of MoS with monolayer from ethanol2And cleaning with deionized water.
In this example, first, a single layer of MoS was grown in advance2Coating a polymethyl methacrylate (PMMA) solution with the volume fraction of 8% on the surface of the side far away from the second substrate 201, for example, spin-coating for 30s at the speed of 1000r/min by using a spin coater, then heating to 100 ℃ by using a hot plate, and baking for 60s to cure the PMMA; with cured PMMA/single layer MoS2Placing the second substrate 201 of the film into a beaker filled with deionized water, heating to 80 ℃, keeping the temperature for 3 hours, and taking out the substrate with the cured PMMA/single-layer MoS from the deionized water2A second substrate 201 of thin film, PMMA/single layer MoS obtained by mechanical stripping2A film.
Further, peeling from the second substrate 201Separating to obtain PMMA/single-layer MoS2After film formation, PMMA/single layer MoS2MoS in thin films2One side of which is attached to the first surface s1 of the first substrate structure 10, followed by heating to 140 ℃ with a hot plate and baking for 30 minutes, a monolayer of MoS2Closely abutting the first surface s 1.
Alternatively, PMMA/single layer MoS transfer2After the film is applied to the first substrate structure 10, the substrate will be provided with the cured PMMA/single layer MoS2The first substrate structure 10 of the film is placed in an acetone solution to be soaked for 10 minutes, PMMA is removed, then the substrate structure is soaked in ethanol, and then the substrate structure with the single-layer MoS is placed in a water bath2Is fished out and rinsed with deionized water to obtain a substrate structure 10 with a single layer of MoS2A first substrate structure 10 of thin films.
Optionally, in the step S4, the single-layer MoS is patterned2Forming a single layer of MoS2 A channel layer 103, comprising:
in a single layer of MoS2Spin-coating photoresist on the surface of one side far away from the first substrate structure 10, exposing and developing to leave a photoresist mask of a first preset area, and etching the single-layer MoS2Forming a single layer of MoS2The channel layer 103.
In particular, with a single layer of MoS2Spin-coating 5214 photoresist 30s on the upper part (i.e. the side of the first surface s 1) of the first substrate structure 10 of the film at the speed of 4000r/min, aligning a mask plate to the first substrate structure 10 on which the photoresist is spin-coated by adopting an MA-6 stepping photoetching machine, leaving a photoresist mask of a first preset area after exposure and development, and etching a single-layer MoS by using an ion beam etching machine IBE2Forming a single layer of MoS2The channel layer 103.
In this embodiment, a first electrode 1041 and a second electrode 1042 are deposited on the first surface s1, such that the second electrode 1042 and the SiO are formed2 Isolation region 102 and the patterned single-layer MoS2Direct contact to obtain the finished single-layer MoS2-a step of Si-based tunneling diode, comprising:
spin-coating a photoresist on the first surface s1, and after exposure and development, leaving a photoresist mask of a second preset area;
depositing nickel/titanium/gold on the first surface by using electron beam evaporation, and stripping redundant nickel/titanium/gold in the range of the second preset area to form a first electrode and a second electrode to obtain the manufactured single-layer MoS2-a Si-based tunneling diode; wherein the second electrode and the single layer MoS2Channel layer and the SiO2The isolation regions are in direct contact.
Specifically, 5214 photoresist 30s is spin-coated on the first surface s1 of the first substrate structure 10 at a speed of 4000r/min, after exposure and development, and after a photoresist mask of a second predetermined region is left, nickel/titanium/gold is deposited on the first surface s1 of the first substrate structure 10 by using electron beam evaporation, and then the first substrate structure 10 is put into acetone to clean the photoresist, and the metal layer of the non-functional region (i.e., the nickel/titanium/gold within the range of the second predetermined region) is removed, so that the first electrode 1041 and the second electrode 1042 are formed, and the second electrode 1042 is in direct contact with the single-layer MoS2 channel layer 103 and the SiO2 isolation region 102.
Illustratively, in the first direction, the thickness of nickel in the first electrode 1041 and the second electrode 1042 is 80nm, the thickness of titanium is 20nm, and the thickness of gold is 50 nm. It should be noted that, in the actual manufacturing process, the thicknesses of nickel, titanium, and gold in the first electrode and the second electrode may be flexibly adjusted according to the process requirements, which is not limited in the present application.
As shown in fig. 7, an embodiment of the present invention further provides a single-layer MoS2A Si-based tunneling diode, which can adopt the single-layer MoS2The preparation method of the-Si-based tunneling diode is obtained.
The beneficial effects of the invention are that:
1. the single-layer MoS provided by the invention2In the preparation method of the-Si-based tunneling diode, a single-layer MoS is prepared on a first substrate by adopting an epitaxial layer transfer printing technology2The channel layer is used for forming a Van der Waals heterojunction, so that the mismatch of thermal expansion coefficients can be relieved to a certain extent, the interface defect density is reduced, the trap-assisted tunneling is further inhibited, and the subthreshold swing of the device is improved from the process angle.
2. The invention transfers the epitaxial layerTechnique for preparing monolayer MoS2The channel layer is combined with the structure of the device, and the formed tunneling diode is of a planar structure, so that the alignment, electrode isolation and device interconnection of the triode device can be realized on the basis, and a high-performance heterogeneous integrated system can be realized.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. Single-layer MoS2-a method of manufacturing a Si-based tunneling diode, comprising:
providing a first substrate, and preparing SiO on one side surface of the first substrate2An isolation region to obtain a first substrate structure; the first substrate structure comprises a first surface and a second surface which are oppositely arranged along a first direction, and the first direction is vertical to a plane where the first substrate structure is located;
obtaining a second substrate comprising a pre-grown single-layer MoS2；
Applying the single-layer MoS by epitaxial layer transfer printing technology2Transferring to the first surface;
patterning the single-layer MoS2Forming a single layer of MoS2A channel layer; the single-layer MoS2The orthographic projection of the channel layer in the first direction covers at least part of a first boundary, and the first boundary is the SiO2The orthographic projection of a contact surface of the isolation region and the first substrate on a plane where the first substrate structure is located is formed, wherein the contact surface is perpendicular to the plane where the first substrate structure is located;
depositing a first electrode and a second electrode on the first surface to make the second electrode and the SiO2Isolation region and single-layer MoS2The channel layer is in direct contact with the substrate to obtain a single-layer MoS2-a Si-based tunneling diode.
2. The single layer MoS of claim 12The preparation method of the-Si-based tunneling diode is characterized in that a first substrate is provided, and SiO is prepared on one side surface of the first substrate2An isolation region, a step of obtaining a first substrate structure, comprising:
providing a first substrate;
etching a side surface of the first substrate to form a pattern area;
depositing SiO on the side surface etched with the pattern region2And depositing SiO2Polishing the first substrate to form SiO2And (5) isolating the region to obtain a first substrate structure.
3. The single layer MoS of claim 22-Si-based tunneling diode, characterized in that the SiO2The thickness of the isolation region in the first direction is h, wherein the thickness is 1 μm<h<10μm。
4. The single layer MoS of claim 12The preparation method of the Si-based tunneling diode is characterized in that the first substrate is a silicon substrate, and the second substrate is a sapphire substrate.
5. The single layer MoS of claim 12-a method for preparing a Si-based tunneling diode, characterized in that said single layer MoS is transferred using an epitaxial layer transfer technique2A step of transferring to the first surface comprising:
in the pre-grown single layer MoS2Spin-coating a polymethyl methacrylate (PMMA) solution on the surface of one side far away from the second substrate, and baking by using a hot plate to solidify the polymethyl methacrylate solution;
with cured PMMA/single layer MoS2Immersing a second substrate of the film into deionized water, and preserving heat after heating to a preset temperature;
removing the cured PMMA/monolayer MoS from the deionized water2A second substrate of thin film, PMMA/single layer MoS by mechanical stripping2Separating the thin film from the second substrate and applying PMMA/monolayer MoS2Transferring the thin film to a first surface of the first substrate structure;
baking the PMMA/single layer MoS by a hot plate2Single layer MoS in thin films2Attaching to the first surface;
with cured PMMA/single layer MoS2Placing the first substrate structure of the film into an acetone solution, removing PMMA, and then soaking the PMMA with ethanol;
removal of MoS with monolayer from ethanol2And cleaning the first substrate structure by using deionized water.
6. The single layer MoS of claim 12-Si-based tunneling diode, characterized in that said patterning of said single MoS layer2Forming a single layer of MoS2A channel layer step, comprising:
in the single layer MoS2Spin-coating photoresist on the surface of one side far away from the first substrate structure, exposing and developing to leave a photoresist mask of a first preset area, and etching the single-layer MoS2Forming a single layer of MoS2And a channel layer.
7. The single layer MoS of claim 12The preparation method of the-Si-based tunneling diode is characterized in that a first electrode and a second electrode are formed on the first surface in a deposition mode, and the second electrode and the SiO are enabled to be connected2Isolation region and single-layer MoS after patterning2Direct contact to obtain the finished single-layer MoS2-a step of Si-based tunneling diode, comprising:
spin-coating a photoresist on the first surface, and after exposure and development, leaving a photoresist mask in a second preset area;
depositing nickel/titanium/gold on the first surface by using electron beam evaporation, and stripping redundant nickel/titanium/gold in the range of the second preset area to form a first electrode and a second electrode to obtain the manufactured single-layer MoS2-a Si-based tunneling diode; wherein the second electrode and the single layer MoS2Channel layer and the SiO2The isolation regions are in direct contact.
8. The single layer MoS of claim 72A preparation method of the-Si-based tunneling diode, which is characterized in thatIn the first direction, the thickness of nickel is 80nm, the thickness of titanium is 20nm, and the thickness of gold is 50 nm.
9. Single-layer MoS2-Si-based tunneling diode, characterized in that it is obtained by means of a method according to any one of claims 1 to 9.
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