CN113644122A - Silicon field effect transistor on insulator - Google Patents
Silicon field effect transistor on insulator Download PDFInfo
- Publication number
- CN113644122A CN113644122A CN202111189758.0A CN202111189758A CN113644122A CN 113644122 A CN113644122 A CN 113644122A CN 202111189758 A CN202111189758 A CN 202111189758A CN 113644122 A CN113644122 A CN 113644122A
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- polysilicon gate
- silicon
- field effect
- effect transistor
- active region
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- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 239000012212 insulator Substances 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 13
- 239000010703 silicon Substances 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 230000007423 decrease Effects 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
- H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a silicon field effect transistor on an insulator, which comprises: the semiconductor device comprises a semiconductor substrate, wherein an insulating layer is arranged on the surface of the semiconductor substrate, and a source region is arranged on the insulating layer; an insulated gate dielectric layer is arranged above the active region, a polysilicon gate is formed on the insulated gate dielectric layer, and the polysilicon gate is electrically insulated from the active region through the insulated gate dielectric layer; a drain electrode region and a source electrode region are arranged on the surface of the active region and distributed on two sides of the polysilicon gate; isolation layers are arranged on the semiconductor substrate and positioned on two sides of the active region; a base contact is arranged on the active region close to the end part with the longer width of the polysilicon gate; the width of the polysilicon gate decreases monotonically from the end near the base contact to the end remote from the base contact. The invention can reduce the density of the bulk hole charges at the edge of the gate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon field effect transistor on an insulator.
Background
Radio frequency silicon-on-insulator switches have penetrated the Radio Frequency Front End (RFFE) market with a market share of over 90%. Core performance metrics for the switch include on-state resistance, off-state capacitance, breakdown voltage, and harmonics. Of the four key criteria, on-state resistance, off-state capacitance, and breakdown voltage generally compete with one another during device optimization. For example, a smaller gate length will lower the on-state resistance at the expense of a lower breakdown voltage and higher off-state capacitance. For the same power withstand specification, a smaller gate length device would require more stacks, resulting in a larger device size.
The structure of the prior radio frequency silicon-on-insulator field effect transistor switching device is shown in the attached figures 1 and 2. As shown in fig. 1, the active region 100 is separated from the semiconductor substrate 105 by a buried silicon oxide layer 110, the active region 100 is separated from the other active regions 100 by an isolation layer 115, a polysilicon gate 120 forms a field effect device gate on an insulated gate dielectric layer 125, a silicon nitride layer 130 is etched by a reactive ion etching process to form spacers, and lightly doped extension regions 135, source regions 140 and drain regions 145 are created by implanting impurities into the semiconductor substrate 105 from the top. As shown in fig. 2, the polysilicon gate 120, the source region 140 and the drain region 145 are rectangular, and the switching FETs can form a back-to-back connection sharing either a source or drain contact, with the base contact 215 being located on the side of the polysilicon gate 120.
As shown in the conventional rf soi fet switch structure above, the base contact 215 is located on the side of the device and the channel is typically low-doped p-type silicon with high resistivity. The intermediate charge takes more time to reach the base contact and the charge generated during high frequency switching operation is not immediately eliminated. This phenomenon, together with other charge generation mechanisms, results in higher charge density (total charge compared to bulk doping) at the edges than in the middle, higher charge density results in lower harmonic inflection points, harmonics increase dramatically with switching FET power, and this uneven charge density problem is not addressed in conventional structures.
Disclosure of Invention
The invention aims to provide a silicon-on-insulator field effect transistor, which aims to solve the problem that the charge of the existing silicon-on-insulator field effect transistor is concentrated at the edge of a grid electrode.
In order to solve the above technical problem, the present invention provides a silicon-on-insulator field effect transistor, including: a semiconductor substrate having a plurality of semiconductor chips formed thereon,
an insulating layer is arranged on the surface of the semiconductor substrate, and a source region is arranged on the insulating layer; isolation layers are arranged on the semiconductor substrate and positioned on two sides of the active region;
an insulated gate dielectric layer is arranged above the active region, a polysilicon gate is formed on the insulated gate dielectric layer, and the polysilicon gate is electrically insulated from the active region through the insulated gate dielectric layer;
a drain electrode region and a source electrode region are arranged on the surface of the active region and distributed on two sides of the polysilicon gate;
a base contact is arranged at the position, closest to the end part with longer width of the polysilicon gate, of the active region;
the width of the polysilicon gate monotonically decreases from the end closest to the base contact to the end location away from the base contact.
Further, the polysilicon gate is trapezoidal.
Still further, the trapezoid is a right trapezoid or an isosceles trapezoid.
Further, in the above technical solution, the side of the polysilicon gate is arc-shaped.
In a second aspect, the present invention provides a silicon-on-insulator field effect transistor comprising: the semiconductor device comprises a semiconductor substrate, wherein an insulating layer is arranged on the surface of the semiconductor substrate, and a source region is arranged on the insulating layer; isolation layers are arranged on the semiconductor substrate and positioned on two sides of the active region;
an insulated gate dielectric layer is arranged above the active region, a polysilicon gate is formed on the insulated gate dielectric layer, and the polysilicon gate is electrically insulated from the active region through the insulated gate dielectric layer;
a drain electrode region and a source electrode region are arranged on the surface of the active region and distributed on two sides of the polysilicon gate;
the lengths of the two end parts of the polysilicon grid are longer than the length of the middle part; base contacts are respectively arranged at the positions, closest to the two ends of the polycrystalline silicon grid, on the active region;
the width of the polysilicon gate is monotonically decreased from two end parts nearest to the base contact to the middle part.
Further, the optimal ratio of the width L2 of the end portion of the polysilicon gate to the width L1 of the middle portion of the gate is expressed by the following formula:
Whereinf(d),h(t),y(w) Respectively the bulk doping concentrationdSilicon thickness on bodytAnd gate widthwA is an adjustment parameter set according to different application requirements.
Still further, the shape of the polysilicon gate is composed of two symmetrical patterns.
Further, the pattern is trapezoidal.
Further, in the above technical solution, the side of the polysilicon gate is arc-shaped.
Compared with the prior art, the silicon-on-insulator field effect transistor provided by the invention has the following beneficial effects: as the body current flows to the base contact, the hole charges are accumulated along the width direction of the field effect transistor, and as drain leakage current is generated in the whole width direction of the transistor, more hole charges are accumulated at the edge of the transistor; in addition, because the bulk charge density accumulated in the middle of the polysilicon gate is low, the length of the middle of the gate can be narrower than near the bulk contact (i.e., the base contact).
Drawings
FIG. 1 illustrates a cross-sectional view of a prior art silicon field effect transistor switching device;
FIG. 2 illustrates a top view of a prior art silicon field effect transistor switching device;
fig. 3 is a top view of a silicon-on-insulator field effect transistor provided in embodiment 1 of the present invention;
fig. 4 is a top view of a silicon-on-insulator field effect transistor provided in embodiment 2 of the present invention;
FIG. 5 illustrates a cross-sectional view of a silicon-on-insulator field effect transistor provided by an embodiment of the present invention;
wherein the reference numbers in figures 1 and 2: 100-an active region; 105-a semiconductor substrate; 110-a silicon oxide layer; 115-a barrier layer; 120-polysilicon gate; 125-an insulated gate dielectric layer; 130-a silicon nitride layer; 135-extension area; 140-a source region; 145-drain region; 215-base contact;
reference numbers in fig. 3, 4 and 5: 400-an active region; 405-a semiconductor substrate; 410-an insulating layer; 415-an isolation layer; 420-polysilicon gate; 425-insulating gate dielectric layer; 430-a spacer; 440-source region; 445-a drain region; 315-base contact.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
As shown in fig. 3 and 5, embodiment 1: the present embodiment provides a silicon-on-insulator field effect transistor including: a semiconductor substrate 405, wherein an insulating layer 410 is arranged on the surface of the semiconductor substrate 405, and the insulating layer 410 is provided with a source region 400;
an insulated gate dielectric layer 425 is arranged above the active region 400, and a polysilicon gate 420 is formed on the insulated gate dielectric layer 425; the polysilicon gate 420 is electrically insulated from the active region 400 by an insulated gate dielectric layer 425;
an isolation layer 415 is disposed on the semiconductor substrate 405 on both sides of the active region 400;
a drain region 445 and a source region 440 are arranged on the surface of the active region 400, and the drain region 445 and the source region 440 are distributed on two sides of the polysilicon gate 420;
a base contact 315 is arranged on the active region 400 at a position closest to the end of the polysilicon gate 420 with a longer width;
the width of the polysilicon gate 420 monotonically decreases from the end closest to the base contact 315 to the end location away from the base contact 315.
In this embodiment, at least one polysilicon gate 420 is formed over the insulated gate dielectric layer 425. The polysilicon gate 420 includes a first bottom side and a second bottom side, the first bottom side and the second bottom side are respectively located at two ends of the polysilicon gate 420, and the width of the first bottom side is longer than that of the second bottom side.
Optionally, the polysilicon gate is a trapezoid, preferably, the trapezoid is a right-angle trapezoid or an isosceles trapezoid.
Optionally, the side edge of the polysilicon gate is not limited to a straight line, and an arc shape or the like can be selected as long as the requirement that the width of the end part close to the base contact on the polysilicon gate is monotonically decreased towards the part far away from the base contact is met.
As the body current flows to the base contact, the hole charges are accumulated along the width direction of the field effect transistor, and the drain leakage current is generated in the whole width direction of the field effect transistor, so that more hole charges can be accumulated on the edge of the field effect transistor; in addition, since the density of the bulk charge accumulated in the middle of the gate is low, the length of the middle of the gate can be narrower than near the bulk contact.
Example 2: as shown in fig. 4 and fig. 5, the present embodiment provides a silicon-on-insulator field effect transistor, which includes a semiconductor substrate 405, an insulating layer 410 on the surface of the semiconductor substrate 405, and a source region 400 disposed on the insulating layer 410;
An insulated gate dielectric layer 425 is arranged above the active region 400, and a polysilicon gate 420 is formed on the insulated gate dielectric layer 425; the polysilicon gate 420 is electrically insulated from the active region 400 by an insulated gate dielectric layer 425; an isolation layer 415 is disposed on the semiconductor substrate 405 on both sides of the active region 400;
a drain region 445 and a source region 440 are arranged on the surface of the active region 400, and the drain region 445 and the source region 440 are distributed on two sides of the polysilicon gate 420;
the lengths of the two end parts of the polysilicon gate 420 are longer than the length of the middle part, and base contacts 315 are respectively arranged at the positions, closest to the two end parts of the polysilicon gate 420, on the active region 400;
the width of the polysilicon gate 420 monotonically decreases from the two end portions nearest the base contact 315 toward the middle portion.
Referring to fig. 4, the length of the middle portion of the polysilicon gate 420 structure of the present invention is narrow compared to the edges, and the narrow middle portion may be implemented using various other shapes, not limited to a straight line.
The source region 440 and the drain region 445 are disposed on either side of the polysilicon gate 420, the base contact 315 is located on the active region 400 near the end of the polysilicon gate 420, and the polysilicon gate 420 defines a channel of the transistor device, so that the base contact 315 can connect the channel to an external port.
Referring to fig. 4, an active region 400 is separated from a semiconductor substrate 405 by an insulating layer 410 formed of a buried silicon oxide layer, the active region 400 is separated from other active regions by an isolation layer 415, the isolation layer 415 typically being shallow trench isolation, and a polysilicon gate 420 forming a field effect device gate on an insulated gate dielectric layer 425. The insulated gate dielectric layer 425 is typically thermally reacted silicon dioxide. Lightly doped extension regions are created by implanting impurities into the semiconductor substrate from the top. A silicon nitride layer is deposited using a low pressure chemical vapor deposition process and then etched by a reactive ion etching process to form spacers 430. The source region 440 and the drain region 445 are typically doped with impurities by an ion implantation process.
Referring to fig. 4, the shape of the gate is formed by two symmetrical trapezoids, that is, the shorter base of the two symmetrical trapezoids is shared, and the longer bases of the two trapezoids become the ends of the gate respectively. The shape of the trapezoid may be a right trapezoid, an isosceles trapezoid or a conventional trapezoid, wherein the preferred shape is an isosceles trapezoid.
In the specification, the source region and the drain region are respectively located at two sides of the gate, and it is not limited whether the source region and the drain region are respectively located at the left side or the right side of the gate, and they may be designed according to actual requirements, which is the prior art and will not be described in detail.
The applicant has found in long-term research that in the off-state the switching device has a mechanism similar to a bipolar transistor. Bipolar devices are formed by the source/body junction of the fet, i.e., the base contact/drain, respectively mapped to the emitter/base/collector. Typically, the switching gate will be negatively biased during the off state to suppress the barrier lowering effect induced by the drain (electric field). This causes the device to enter accumulation mode and creates a surface path for hole charges. When drain to gate high bias causes drain leakage current, hole charges move towards the source, the built-in barrier between the p-body and the source does not allow hole charges to pass through except by recombination, and the body charges eventually flow to the base contact. The drain leakage current increases with drain bias and eventually the body current can create enough bias to overcome the base/source (base/emitter) junction to establish direct conduction between the drain and source with the result that the device can no longer sustain the drain voltage, which manifests as device breakdown. Hole charges accumulate along the width of the device as a result of the body current flowing to the base contact. The SOI field effect transistor provided by the invention can effectively reduce the density of the bulk hole charges at the edge part of the grid electrode because the width of the end part close to a body connection point (namely a base contact) on the polysilicon grid electrode monotonically decreases towards the width far away from the base contact part (the length L2 of the end part of the grid electrode is greater than the length L1 of the middle part of the grid electrode in the embodiment), and relatively, the length of the middle part of the grid electrode far away from the base contact part is designed to be smaller because the density of the bulk charges accumulated at the middle part of the grid electrode is lower.
The optimum ratio of the width L2 of the end portion of the polysilicon gate to the width L1 of the middle portion of the polysilicon gate is determined by a number of physical characteristics including the body doping concentration, the silicon thickness on the body, the gate width and the gate polysilicon thickness. The basic formula can be expressed as follows:
whereinf(d),h(t),y(w) Respectively the bulk doping concentrationdSilicon thickness on bodytAnd gate widthwA monotonically rising function of (a). The monotone increasing function described herein includes a linear monotone increasing function, a second-order monotone increasing function, and an exponential function.aAre adjustment parameters corresponding to different applications. For the application condition of requiring high pressure-bearing capacity of the switch, the pressure-bearing capacity of the switch can be properly improveda. For applications requiring a smaller product of on-resistance and off-capacitance,athere is an optimum value.
By introducing the formula, the bulk hole charge density of the edge part of the grid electrode can be effectively reduced, and meanwhile, the application range of the silicon field effect transistor on the insulator is wider.
Typically, to increase the pressure capacity of the switch, the length of the passage is increased. Since the channel resistance under the gate accounts for most of the switch resistance, increasing the channel length directly results in an increase in on-resistance. In the invention, because the length of the grid electrode is increased along the direction of the base electrode contact point, the middle part of the field effect transistor provided by the invention uses a smaller length of the grid electrode, and the increase of the on-resistance can be reduced. The turn-off capacitor is hardly influenced by the invention, so that the pressure bearing capacity is improved, and compared with the traditional solution, the increase of the on-resistance of the switch is reduced. The invention can improve the bearing capacity, the silicon MOSFET radio frequency switch tube on the insulator can be made wider, and the layout area required by the radio frequency switch with the same performance is reduced.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120313173A1 (en) * | 2011-06-07 | 2012-12-13 | Rf Micro Devices, Inc. | Method for isolating rf functional blocks on silicon-on-insulator (soi) substrates |
| US20150348825A1 (en) * | 2014-05-30 | 2015-12-03 | Magnachip Semiconductor, Ltd. | Semiconductor device with voids within silicon-on-insulator (soi) structure and method of forming the semiconductor device |
| CN105789189A (en) * | 2016-05-09 | 2016-07-20 | 中国科学院上海微系统与信息技术研究所 | Radio frequency inductor element based on silicon substrate on insulator, and preparation method for radio frequency inductor element |
| CN112349782A (en) * | 2020-11-05 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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- 2021-10-13 CN CN202111189758.0A patent/CN113644122B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120313173A1 (en) * | 2011-06-07 | 2012-12-13 | Rf Micro Devices, Inc. | Method for isolating rf functional blocks on silicon-on-insulator (soi) substrates |
| US20150348825A1 (en) * | 2014-05-30 | 2015-12-03 | Magnachip Semiconductor, Ltd. | Semiconductor device with voids within silicon-on-insulator (soi) structure and method of forming the semiconductor device |
| CN105789189A (en) * | 2016-05-09 | 2016-07-20 | 中国科学院上海微系统与信息技术研究所 | Radio frequency inductor element based on silicon substrate on insulator, and preparation method for radio frequency inductor element |
| CN112349782A (en) * | 2020-11-05 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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Denomination of invention: A silicon on insulator field-effect transistor Granted publication date: 20220128 Pledgee: Nanjing Bank Co.,Ltd. Nanjing Financial City Branch Pledgor: Nanjing yuanluoxin Technology Co.,Ltd. Registration number: Y2024980039216 |