CN113626977A

CN113626977A - High-frequency interconnection method for 25G DFB laser

Info

Publication number: CN113626977A
Application number: CN202110690920.0A
Authority: CN
Inventors: 张耐
Original assignee: Nanjing Guangtong Photoelectric Technology Co ltd
Current assignee: Nanjing Guangtong Photoelectric Technology Co ltd
Priority date: 2021-06-22
Filing date: 2021-06-22
Publication date: 2021-11-09
Anticipated expiration: 2041-06-22
Also published as: CN113626977B

Abstract

The invention discloses a high-frequency interconnection method of 25G DFB lasers, which comprises the following steps: (1) designing one or more of the shape and size of the ceramic substrate microstrip line, the mounting position of the DFB laser diode chip, the geometric shape and size of the bonding alloy wire, and the impedance values of a driving source and a load terminal; (2) establishing a high-frequency 3D structure HFSS simulation model of the DFB laser diode chip, verifying one or more designs in the step (1) through the simulation model, and then optimizing design parameters. The optimized DFB laser high-frequency interconnection design has the advantages of reducing the high-frequency return loss of a 25G DFB laser, improving the yield of devices and modules and reducing the cost through the verification of a simulation model, and the high-frequency return loss of the optimized TO5625G TO tube DFB laser high-frequency interconnection design is suppressed TO be about-15 dB.

Description

High-frequency interconnection method for 25G DFB laser

Technical Field

The invention relates to the technical field of optical fiber communication, in particular to a high-frequency interconnection method of 25G DFB lasers.

Background

With the advent of the global 5G era, 25G 12-wave WDM technology has become a popular choice for 5G base stations, and thus has brought about an explosion in market demand for 25G high-speed optical modules. As part of the core of high-speed optical modules, 25G DFB lasers are more of great interest in the industry. In consideration of low cost, 25G DFB lasers are multi-packaged in the form of TO tubes in optical module applications. High-frequency connections TO the inside and outside of the tubes of the TO tubes have hitherto been based on the construction of a glass bead, i.e. a high-frequency lead wire is insulated and hermetically sintered on the TO tube base using special glass materials, the high-frequency construction of which is similar TO that of a high-frequency coaxial line. However, due TO the limitations of the dielectric constant of the special glass materials used for sealing and insulation and the diameter and linearity allowed by the glass beads and the high-frequency lead on the TO header, the characteristic impedance of the common TO tubes, such as the coaxial structures of the glass beads of TO56 and TO38, is difficult TO achieve 50 ohms at high frequencies. The characteristic impedance of the microglass coaxial structure for the TO tube of a 25G DFB laser is generally designed TO be as close TO 25 ohms as possible. Correspondingly, the internal resistance of the drive source of the 25G DFB laser is also typically 25 ohms. The high-frequency wiring on the carrier-high-frequency ceramic substrate carrying the 25G DFB laser chip in the TO tube is designed into a microstrip line with the middle broken and the characteristic impedance of 25 ohms. And the 25G DFB laser chip is attached to the left edge of the disconnected microstrip line, and the laser chip is connected with the right side of the disconnected microstrip line by using a bonding gold wire. The high-frequency interconnection mode of the 25G DFB laser seems TO be simple and clear, but because the series resistance of the most commonly used 25G DFB laser chip in the market is generally 9-12 ohms, when the DFB chip with the series resistance is inserted into a two-section disconnected 25-ohm microstrip line by the method, high-frequency reflection is caused by impedance discontinuity, and the high-frequency design of the existing 25G TO DFB does not have effective measures for relieving the adverse effect, so that the high-frequency reflection of interconnection is high, and the eye pattern is often degraded.

To date, there has been no reasonable high frequency simulation analysis for such high frequency interconnects, nor even 3D high frequency models for 25G DFB chips, let alone simulation and design optimization on this basis. In practical application, when the eye pattern is degraded due to excessive high-frequency reflection, only an expensive laser can be replaced, thereby causing great economic loss.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a high-frequency interconnection method of 25G DFB lasers, which solves the problem of eye pattern degradation caused by high return loss of the high-frequency interconnection of the 25G DFB lasers.

The technical scheme is as follows: the DFB laser high-frequency interconnection method comprises the following steps:

(1) designing one or more of the shape and size of the ceramic substrate microstrip line, the mounting position of the DFB laser diode chip, the geometric shape and size of the bonding alloy wire, and the impedance values of a driving source and a load terminal;

(2) establishing an HFSS simulation model of the high frequency 3D structure of the 25G DFB laser diode, verifying the design or designs of the step (1) through the simulation model, and then optimizing design parameters on the basis of the verification.

The ceramic substrate microstrip line in the step (1) comprises a left microstrip line and a right microstrip line which are designed asymmetrically, the left edge of a gap at the break of the left microstrip line and the right microstrip line is positioned on the right side of the symmetric center line of the ceramic substrate, and the chamfer angle at the 90-degree corner of the left microstrip line is greater than the chamfer angle at the 90-degree corner of the right microstrip line; the inlets of the left microstrip line and the right microstrip line are widened.

In the step (1), the DFB laser diode chip is attached to the left microstrip line, the center line of the light-emitting strip of the DFB laser diode chip is aligned with the symmetrical center line of the ceramic substrate, and the edge of the right side of the DFB laser diode chip enters the gap between the left microstrip line and the right microstrip line.

In the step (1), two bonding alloy wires are connected to the right microstrip line from the anode routing disc of the DFB laser diode chip, and an included angle is formed between the two bonding alloy wires.

And (1) in order to overcome the adverse effect caused by the series resistance of the DFB laser, the impedance value of the driving source and the impedance value of the load terminal are increased.

And (2) in the step (1), the gap position of the break-off position of the left microstrip line and the right microstrip line on the ceramic substrate ensures that the center line of the luminous strip of the DFB laser diode chip is positioned on the central axis of the tube seat after the DFB laser diode chip is mounted, and the mounting position is determined according to the optimal return loss of high-frequency interconnection of the laser diode chip after mounting.

In the step (1), in order TO reduce the manufacturing cost of the TO tube seat, the chamfer angle caused by punch forming at the joint of the ceramic substrate bearing base and the tube seat surface is not processed, and the parasitic inductive reactance caused by a large gap between the high-frequency ceramic substrate and the tube seat surface due TO the chamfer angle is compensated by adjusting the geometric shape at the inlet of the microstrip line of the high-frequency ceramic substrate.

The simulation model in the step (2) has the actual appearance and size of the 25G DFB laser diode chip and summarizes the layer structure of the laser diode chip; the device comprises an upper electrode gold-plating layer 21, a BCB passivation layer 25, a SiO2 passivation layer 26, a p + -GaInAs ohmic contact layer 23, a p-InP cladding layer 24, a grating layer 27, an MQW28, an n-type substrate layer 29 and a lower electrode gold-plating layer 22; the p + -GaInAsAs ohmic contact layer 23 and the p-InP cladding layer 24 form a ridge-shaped boss and are embedded in a BCB passivation layer 25 and an SiO2 passivation layer 26.

Simplifying the simulation model in the step (2) into an insulation region, an MQW region, a conductive region above the MQW region and a conductive region below the MQW region; the insulating region comprises a BCB passivation layer and a SiO2 passivation layer, the conductive region above the MQW region comprises a ridge boss and a grating layer, and the conductive region below the MQW region comprises a substrate layer; the conductivity of the conductive region above and below the MQW region determines the resistance of the 25G DFB laser diode chip.

Has the advantages that: compared with the prior art, the invention has the remarkable advantages that: 1. the design of optimizing the high-frequency interconnection of the 25G DFB laser reduces the high-frequency return loss of the DFB laser, improves the yield of devices and modules, reduces the cost, and inhibits the high-frequency return loss of the optimized TO5625G TO tube DFB laser high-frequency interconnection design TO be about-15 dB. 2. And a simulation model is established, and design parameters are verified and optimized.

Drawings

FIG. 1 is a diagram of an exemplary ridge 25G DFB laser diode chip;

FIG. 2 is a schematic diagram of an exemplary internal multi-layer structure of a 25G DFB laser diode chip;

FIG. 3 is a schematic diagram of an HFSS model layer structure of a 25G DFB laser diode chip according to the present invention;

FIG. 4 is an engineering drawing of the TO56 header of the 25G DFB;

FIG. 5 is a design diagram of a microstrip line of the high-frequency ceramic substrate according to the present invention;

FIG. 6 is an overall assembly diagram of the high frequency interconnect of the present invention;

FIG. 7 is a diagram of a high frequency interconnect simulation result of the present invention;

FIG. 8 is a prior art high frequency interconnect assembly diagram of a 25G TO DFB;

fig. 9 is a diagram of a simulation result of frequency interconnect in the prior art.

Detailed Description

The technical scheme of the invention is further explained by using a TO56 case in combination with the attached drawings, and the technical scheme is also applicable TO the TO 38.

In view of the characteristics of the materials used for 25G DFB TO tube sockets and the cost of opening the TO tube sockets, the 25G DFB TO tube sockets used in the invention still continue TO be used today in the industry more commonly used and more typical 25G TO DFB TO tube sockets.

The high-frequency interconnection method of the 25G DFB laser comprises the following steps

1. And (3) executing one or more designs in the steps (1) - (5).

(1) And designing the shape and size of the ceramic substrate microstrip line. The ceramic substrate microstrip line comprises a left microstrip line and a right microstrip line which are designed asymmetrically, the left edge of a gap at a break point of the left microstrip line and the right microstrip line is positioned on the right side of the symmetric center line of the ceramic substrate, and the chamfer angle at the 90-degree corner of the left microstrip line is greater than the chamfer angle at the 90-degree corner of the right microstrip line; the inlets of the left microstrip line and the right microstrip line are widened. The gap position of the break-off position of the left microstrip line and the right microstrip line on the high-frequency ceramic substrate ensures that the center line of the luminous strip of the DFB laser diode chip is positioned on the central axis of the tube seat after the DFB laser diode chip is mounted, and the mounting position of the laser diode chip is determined according to the optimal return loss of high-frequency interconnection of the laser diode chip after the laser diode chip is mounted.

In the invention, the theoretical basis of the design of the left and right asymmetric chamfers is as follows: firstly, the characteristic impedance Z0 of the microstrip line has the following characteristics after the dielectric constant and the thickness of the ceramic substrate are determined: the characteristic impedance Z0 increases as the line width W becomes narrower, and decreases as the line width W becomes wider; the value of Z0 becomes larger when the copper foil thickness becomes thinner, and conversely, the value of Z0 becomes smaller. The microstrip line on the ceramic substrate is divided into a left microstrip line and a right microstrip line, and each part is provided with a 90-degree right-angle turn. For the 90-degree right-angle turn of the microstrip line, in order to keep the impedance Z0 of the original microstrip line unchanged, a chamfer mitigator treatment is performed at the right-angle turn to eliminate the additional parasitic capacitance contribution caused by the cut-off part. The left side and the right side of the microstrip line are interconnected by a bonding gold wire. The introduction of the bond wire introduces inductance. In order to compensate for this inductance, it is common to introduce appropriate capacitors at both ends of the gold wires to compensate for the inductance caused by the gold wires. In microstrip circuits, no separate capacitor needs to be introduced to achieve this compensation. In this design, the right microstrip line is cut out with a small number of chamfers to introduce some capacitors. As for the left side of the microstrip line, since the laser diode chip is attached thereto, the introduction of the chip substantially causes an increase in the thickness of the left microstrip line in the vicinity of the division of the microstrip line. This increased thickness reduces the impedance of the microstrip line at that point, which reduces the impedance and introduces a capacitance. The capacitor can play a role of compensating the inductance of the gold wire. As such, the chamfer at the right angle of the left microstrip line is cut off more than the chamfer at the right side.

(2) And designing a mounting position of the DFB laser diode chip. The DFB laser diode chip is attached to the left microstrip line, and the center line of the light-emitting strip of the DFB laser diode chip is aligned to the symmetrical center line of the ceramic substrate. When the 25G DFB semiconductor laser chip is mounted, the right edge of the chip extends out of the right microstrip line to enter a gap between the left microstrip line and the right microstrip line, so that return loss in high-frequency interconnection can be restrained, and the optimal extending distance is about 10 micrometers.

The invention discloses a basis of a mounting position of a DFB laser diode chip: the mounting position of the DFB laser diode chip, the length of the gold wire and the angle between the two gold wires are in close relation. The closer the chip position is to the central line of the microstrip line, the greater the degree of freedom of the angle value between the two gold threads is. However, if the chip is too close to the center line of the gold microstrip line, the edge of the emitted light touches the ceramic substrate because the chip has a large divergence angle in the vertical direction. In consideration of this limitation, the present invention designs the distance between the light-emitting surface of the chip and the edge of the ceramic substrate to be 150 μm. This enables the emitted light of the laser chip to be closest to the center line of the microstrip line without touching the ceramic substrate. In addition, the chip is properly moved to the left side between the gaps of the left and right microstrip lines, so that the length of the bonding alloy line can be reduced, and the increase of the equivalent thickness of the microstrip line at the chip mounting position of the left microstrip line caused by the fact that the laser chip is mounted on the left microstrip line can be reduced. Because the electromagnetic field of the microstrip line is basically sealed in the ceramic plate below the microstrip line, the electromagnetic field at the transition position of the gap surrounds the gold wire, and the laser chip slightly moves to the right of the gap, for example, about 10um, so that the interference to the original electromagnetic field can not occur.

(3) And designing the geometric dimension of the bonding alloy wire. And the two bonding alloy wires are connected to the right microstrip line from the anode routing disc of the DFB chip, and an included angle is formed between the two bonding alloy wires.

The geometric shape and the size of the bonding alloy wire are theoretically as follows: the bond wire-induced inductance, although compensated by properly introducing capacitance across the gold wire, has some limitations. It is also important how to reduce the inductance of the gold wire. In order to reduce the inductance of the gold wire itself, there are generally the following approaches: (1) shortening the length of the gold thread; (2) increasing the number of gold wires; (3) the multiple gold wires reduce mutual shrinkage between the wires. The number of gold wires is limited by the size of the semiconductor laser chip routing disc. In order to ensure the bandwidth of the semiconductor laser chip, the size of the bonding pad is preferably smaller, and the bonding pad allows 2 gold wires to be bonded at most in the present case. The present invention seeks to reduce the mutual inductance of the two gold wires to reduce the total inductance caused by the gold wires. Mutual inductance is caused by parallel gold wires. When two gold wires form a certain angle, the mutual inductance can be greatly reduced. However, if two gold wires form a certain angle, the length of the gold wire may be increased, and there is a problem of overall balance. The angle between the two wires is reasonable between 35-45 degrees. In addition, the design of the angle between the gold wires is closely related to the mounting position of the laser chip.

(4) The driving source and load termination impedance values are designed. In order to overcome the adverse effect caused by the series resistance of the 25G DFB laser, the internal resistance of the driving source and the load termination impedance value can be properly increased.

When the DFB laser diode chip is connected in series on the microstrip line, the impedance of the equivalent load seen from the driving side becomes large due to the series resistance of the chip. The larger the series resistance of the DFB laser diode chip is, the larger the impedance of the equivalent load deviates from the original impedance, and the larger the impedance mismatch is, the larger the high-frequency reflection is. If the internal resistance of the driving source and the load termination impedance are appropriately increased, the relative deviation value becomes smaller, which is beneficial to reduce the reflection, although the deviation of the equivalent load impedance caused by the series resistance of the laser chip from the original termination impedance still exists. However, the characteristic impedance of the coaxial micro-bead glass of the TO tube is still about 25 ohms, so that the negative effect can be caused by excessively improving the impedance of a driving source and a load terminal. To achieve the overall balance, the driving source and load termination impedances are increased by 3 ohms during design.

(5) The geometric shape of the inlet of the microstrip line of the high-frequency ceramic substrate is adjusted to widen the line width of the microstrip line. In order TO reduce the manufacturing cost of the TO tube seat, the TO tube seat adopted by the invention does not process the chamfer angle of the joint of the bearing base of the high-frequency ceramic substrate and the tube seat surface caused by punch forming. However, the chamfer causes a large gap between the high-frequency ceramic substrate and the stem surface, which is generally 0.15 mm. The chamfer is processed by more and more typical 25G TO tube seats in the industry, and the gap between the high-frequency ceramic substrate and the tube seat surface is 0.05mm after processing, but the processing cost is quite high. With the TO stem without the chamfer, when the lead wire of the micro bead glass reaches the high frequency ceramic substrate through the gap of 0.15mm, parasitic inductive reactance is caused because the bare lead wire of 0.15mm is suspended in the gap. The characteristic impedance at the inlet of the microstrip line of the high-frequency ceramic substrate is reduced by widening the line width of the microstrip line, and the parasitic inductive reactance can be compensated by introducing equivalent capacitance.

2. Establishing an HFSS simulation model of a high-frequency 3D structure of the DFB laser diode chip, verifying one or more designs in the steps (1) to (5) through the simulation model, and then optimizing design parameters.

In this embodiment, an HFSS high-frequency simulation model is established based on the physical structure of the 25G ridge DFB laser diode chip.

In addition, along with the improvement of the P-surface passivation technology of Ridge (Ridge) lasers in recent years, the Ridge structure has smaller parasitic capacitance compared with a buried BH structure, thereby achieving higher bandwidth.

Fig. 1 is an external view of a typical ridge-type 25G DFB laser diode chip, in which the left side of fig. 1 is a 3D perspective view thereof and the right side of fig. 1 is a side view thereof. The basic size of the chip is typically 150um (L), 360um (W), 88um (H). Due to the limitation of the wafer cleavage process, the 25G DFB laser diode chip generally has a width greater than a length, and the shorter length is to achieve a high relaxation oscillation frequency of the 25G DFB laser diode. The top p surface of the 25G DFB laser diode chip is provided with a small gold-plated layer with the thickness of about 0.6 micrometer, the gold-plated layer is composed of a p-surface electrode with the thickness of 20um (W) x 150um (L) and a wire bonding disc connected with the p-surface electrode and the wire bonding disc with the diameter of about 95um, the bottom surface of the chip is an n-surface, the gold-plated layer with the thickness of 0.3 micrometer serving as a cathode surface is plated, and the gold-plated layer is provided with pull back with the thickness of about 30 micrometers at two side edges. The dotted line in the right side of fig. 1 is the position of the center of the light-emitting point of the laser chip, and the distance from the center of the light-emitting point to the edge of the laser chip, that is, the distance from the center line of the p-surface electrode of the chip to the right edge of the laser chip is 230 um. The series resistance of 25G DFB laser diode chips is not small, and the index of the series resistance of commercially available 25G DFB laser diode chips is generally 9-12 ohms, and also 9-15 ohms. Considering that the 25G DFB laser diode chip is mounted on the left microstrip line and connected TO the right microstrip line through gold wire bonding, because the chip has a large series resistance, the maximum value of the chip is about half of the impedance value of the microstrip line, and the chip also has a certain parasitic capacitance and a certain space form, when the microstrip line of the TO tube seat high-frequency substrate is designed, the influence of the 25G DFB laser diode chip mounted on the left microstrip line and connected TO the right microstrip line through the bonding gold wire on high-frequency transmission needs TO be evaluated, and the design of the 25G TO tube seat high-frequency substrate can be optimized on the basis. Specific evaluations are generally available with the HFSS simulation software of Ansoft. Therefore, an HFSS model of the DFB laser diode chip is necessary for simulation and further design optimization.

In this embodiment, the model of the built internal structure of the ridge-type DFB laser diode chip is shown in fig. 2, and as can be seen from fig. 2, the model includes an upper electrode gold-plating layer 21, a BCB passivation layer 25, an SiO2 passivation layer 26, a p-indium gallium arsenic phosphide (GaInAsP) grating layer 27, an MQW (multiple quantum well) layer 28, an n-indium phosphide (InP) substrate layer 29, and a lower electrode gold-plating layer 22; the p + -GaInAsAs ohmic contact layer 23 and the p-InP cladding layer 24 form a ridge-shaped boss and are embedded in the BCB passivation layer 25 and the SiO2 passivation layer 26.

The upper electrode gold-plating layer 21 has a thickness of 0.6 μm, and the lower electrode gold-plating layer 22 has a thickness of 0.3 μm. The p + -GaInAs ohmic contact layer 23 is a very thin layer of p + GaInAs, and the ohmic contact layer 23 and the p-InP cladding layer 24 form a boss, the total height of which is generally about 1.6 microns. Layer 27 is a grating layer and includes, for simplicity, a first etch stop layer, a Spacer layer and a second etch stop layer, typically 0.175 microns thick. The MQW layer 28 also includes, for simplicity, an SCH layer, typically 0.285 microns thick; the n-type InP substrate layer 29 also comprises an n-InP Buffer (Buffer) thin layer for simplifying the layer, and the layer thickness is generally about 85 micrometers; a SiO2 passivation layer 26, typically 80 nm thick; the BCB passivation layer 25 is a BCB polymer passivation layer for planarizing the p-side of the laser chip having the ridge type configuration, and its thickness is generally 1.52 μm. The thicknesses of the layers and the ridge-type mesas in fig. 2 are not drawn to scale in order to clearly show the interrelationship between the various levels of the chip structure.

Fig. 2 shows the ridge 25G DFB laser diode chip series resistance and parasitic capacitance formation. The parasitic capacitance of the ridge-type DFB laser diode chip is composed of a p-side electrode, a bonding pad connected with the p-side electrode, a parasitic capacitance to the ground and a MQW layer PN junction capacitance. Since the MQW layer PN junction capacitance is very small, the parasitic capacitance is mainly contributed by the parasitic capacitance of the p-side electrode and its associated bond pad to ground. The dielectric constant and thickness of the BCB passivation layer 25, the SiO2 passivation layer 26 are critical factors in determining the size of the capacitor. The dielectric constant of SiO2 is 3.9, the dielectric constant of BCB is 2.50-2.65, and the parasitic capacitance formed by the thickness of SiO2 and BCB and the area of the top electrode and the bonding pad of the laser is small enough to make the ridge type 25G DFB laser diode chip work at 25Gb/s with enough bandwidth.

The series resistance of the ridge-type 25G DFB laser diode chip is composed of a resistance R1 of a cladding layer and a grating layer on the MQW layer, and a resistance R2 of a substrate layer under the MQW layer. It can be deduced from the n-type carrier concentration and n-type carrier mobility of an n-InP substrate that R2 is much smaller than R1. If an effective conductance σ 1 is used to represent the average conductance of the regions of the ohmic contact layer 23, the cladding layer 24 and the grating layer 27 in fig. 2. And the average conductivity in the region of substrate layer 29 in fig. 2 is represented by an effective conductance σ 2, the series resistance of R1 and R2 and the ridge DFB laser diode chip can be derived from σ 1 and σ 2. A simplified model of the HFSS model of a ridge 25G DFB laser diode chip is obtained by combining FIGS. 1 and 3. Fig. 3 is not drawn to scale in order to clearly show the interrelationship between the various levels of the chip structure, the thickness of the various layers, and the ridge-type lands. The model not only embodies the space geometry of the ridge-type DFB laser diode chip, but also gives the parasitic capacitance and the series resistance value of the ridge-type DFB laser diode chip. By adjusting σ 1 and σ 2, primarily σ 1, the series resistance of the ridge DFB laser diode chip model can be adjusted by changing σ 1, since the main contribution to the series resistance of the ridge DFB laser diode chip comes from σ 1.

FIG. 4 is an engineering drawing of a 25G TO56 header that is currently more commonly used in the industry, more typical and has the least high frequency return loss. FIG. 4(a), FIG. 4(b) and FIG. 4(c) are a front view and two side views, respectively, of the TO header. The high-frequency wiring of the TO header high-frequency ceramic board can be seen from FIG. 4(a), the high-frequency microstrip line is a ╔ ╗ type microstrip line with characteristic impedance of 25 ohm, the width of the microstrip line is 0.65mm, the thickness of the high-frequency ceramic board is 0.19mm, a 0.09mm wide fracture gap is arranged at the right side of 0.2mm away from the symmetry line of the microstrip line, the microstrip line is provided with 0.05mm pull back at the peripheral edge of the ceramic substrate, and the two 90-degree corners of the microstrip line are respectively chamfered by 0.74 mm. As can be seen from FIG. 4(c), a half-moon shaped boss is protruded from the TO header plane, and the high frequency ceramic substrate is soldered on the boss with a gap of only 0.05mm from the TO header plane at its edge. In order TO reduce the gap TO 0.05m, the chamfer formed by press forming at the joint of the high-frequency ceramic substrate bearing base and the tube seat surface of the TO tube seat needs special processing treatment, and the processing cost is quite high. If the chamfer is not processed, the chamfer can make the gap between the high-frequency ceramic substrate welded on the boss and the TO tube seat plane reach 0.15 mm. The diameter of the micro bead glass is 0.7mm, wherein the diameter of the high-frequency lead is 0.25mm, the dielectric constant of the glass material is about 6.7, and the micro bead glass is a coaxial structure, and the characteristic impedance of the micro bead glass is close to 24 ohms. Since the dielectric of the material is usually unchanged, the characteristic impedance of the coaxial structure of the glass bead is improved only by increasing the diameter of the glass bead and reducing the diameter of the central lead. Both of these approaches are difficult to implement in practice due to excessive cost or reliability concerns. Unlike the micro glass, the high frequency ceramic substrate is a part attached TO the TO stem, so that there is much freedom in design. The present embodiment continues TO use the more typical 25G TO DFB TO header now used in the industry, but simplifies its manufacture TO reduce cost.

When the DFB laser diode chip is attached to the left part of the gap of the microstrip line of the high-frequency ceramic substrate by gold-tin solder, the characteristic impedance of the microstrip line on the left side of the gap changes towards the direction of reduction due to the influence of the space distribution of chip materials. When the wire bonding disc of the chip electrode is connected with the microstrip line on the right side of the gap by gold wire bonding, a resistor and an inductor are connected in series between the microstrip lines on the left side and the right side, the resistance value is the series resistance of the laser chip, the inductance value is mainly the inductance value caused by the gold wire, and in addition, the space form of the laser chip also contributes to the laser chip. As the series resistance of the laser chip is increased and the inductance value of the gold wire is increased, the impedance of the entire microstrip line loop is deviated by 25 ohms, and the high-frequency transmission effect is deteriorated.

Therefore, the design of the shape and the size of the high-frequency ceramic substrate microstrip line is verified through simulation based on the established HFSS model of the ridge type DFB laser diode chip; designing a mounting position of a DFB chip; designing the geometric shape and size of the bonding alloy wire; design of driving source and load termination impedances.

Fig. 5 is a design diagram of a microstrip line of the high-frequency ceramic substrate thereof. The ceramic substrate is made of aluminum nitride, has a dielectric constant of 8.8 and a thickness of 0.2mm, which is one of the standard thicknesses available in the market. The line width of the microstrip line is 0.67 mm, and the characteristic impedance of the microstrip line corresponding to the line width is 25.26 ohms. The gap at the break of the left and right microstrip lines is 0.1 mm, and the distance between the edge at the left end of the gap and the symmetrical center line of the ceramic substrate is 0.22 mm. The chamfer angle at the right angle corner of the left microstrip line is 0.7mm, and the chamfer angle at the right angle corner of the right microstrip line is 0.68 mm. The inlets of the left microstrip line and the right microstrip line are widened, the width of the microstrip line is widened by 0.2mm, and the length of the widened part is 0.15 mm. The microstrip line is formed by a pull back at the periphery of the ceramic substrate, the pull back at the inlet is 0.03 mm, the microstrip line is 0.05mm at two sides, and the end edge of the top is 0.05 mm.

FIG. 6 is a top view of the assembly of the ceramic substrate of FIG. 5 on the TO header base, with the mounting locations of the 25G DFB laser diode chip and the configuration of the gold bond wires indexed on the ceramic substrate. The outer dimensions of the DFB laser diode chip, and the shapes and thicknesses of the upper and lower electrodes are the same as those in fig. 1, and the internal structure is the same as that in fig. 3. The gap between the ceramic substrate and the TO tube seat surface is 0.15mm, so that a section of 0.15mm of inner lead of the TO tube base micro-bead glass is suspended in the air before being connected TO the ceramic substrate, and the parasitic inductive reactance caused by the section of lead is compensated by the widening of the inlets of the left and right microstrip lines. The DFB chip is attached TO the left microstrip line, and the central line of the luminous strip is aligned TO the symmetrical central line of the TO tube of the ceramic plate, so that the laser diode chip protrudes 10 microns into the gap at the break of the left microstrip line and the right microstrip line. And a pull back of 0.1 mm is arranged on the upper side of the right microstrip line on the light-emitting end face, so that the distance between the light-emitting end face of the chip and the upper edge of the ceramic substrate is 0.15 mm. The semi-divergence angle of the 25G DFB laser diode chip in the vertical direction is 22.5 degrees, and the height of the light-emitting center from the surface of the ceramic substrate is more than 70 microns, so that the light beam emitted from the DFB chip does not touch the ceramic substrate. An included angle of 36 degrees is formed between two bonding alloy wires which are connected to the right microstrip line through the anode routing disc on the p surface of the DFB laser diode chip, the length of each gold wire is 470 microns, and the length is enough to ensure that the DFB chip is connected to the right microstrip line. The invention adopts the scheme that the mounting position of a 25G DFB semiconductor laser chip on a TO tube seat on a microstrip line on the left side of a high-frequency ceramic substrate is changed TO improve the high-frequency return loss in high-frequency interconnection. Furthermore, when the 25G DFB semiconductor laser chip is mounted, the right edge of the chip properly extends out of the right microstrip line to enter a gap between the left microstrip line and the right microstrip line, so that the return loss in high-frequency interconnection can be restrained, and the optimal extending distance is about 10 micrometers.

The P1 and P2 labeled at the lead-out of the TO header bead glass in FIG. 6 are the locations of the ports for input and output in the HFSS simulation.

The design parameters of the present embodiment are optimized through repeated simulation by HFSS software. The simulation was performed using the Ansoft HFSS simulator. Fig. 7 shows the simulation result of the frequency-dependent return loss S11 of the high-frequency interconnection of 25G TO tube DFB semiconductor lasers when the series resistance of the 25G DFB laser diode is set TO 10.3 ohms under the above design parameters. As mentioned above, the minimum value of the series resistance of the most commonly used 25G DFB laser chips on the market today is 9 ohms, while the maximum value is 12 ohms. The simulation takes that the series resistance of a 25G DFB laser chip is 10.3 ohms and is close to the middle value of the series resistance, so the set value of the series resistance has good typicality. The conductivities σ 1 and σ 2 in the present 25G DFB laser chip model corresponding to a series resistance of 10.3 ohms were 950S/m and 8.46x10^4S/m, respectively. The internal resistance of the optimized drive source for the simulation, i.e., the driver output impedance and the load termination impedance values, was 28 ohms. It can be seen from FIG. 7 that the return loss of the 25G TO tube DFB laser of embodiments of the present invention is less than-15.13 dB over the frequency range of 0-19 GHz.

In the above simulation, when the series resistance of the 25G DFB laser chip was set to 9 ohms and 12 ohms, respectively, the return loss was about 0.3dB lower for 9 ohms than for 10.3 ohms, and about 0.5dB higher for 12 ohms than for 10.3 ohms. This result is consistent with previous analysis.

In contrast, the high frequency interconnect of the TO56 model 25GDFB laser, which is currently more commonly used in the industry, more typical and has the least high frequency return loss, was also simulated by Ansoft HFSS. The high frequency interconnection comprises a TO56 tube seat of 25G TO DFB provided with a high frequency ceramic substrate and shown in figure 4, and a 25G DFB laser diode chip model of the invention, the chip mounting position and the connection geometric configuration of a key alloy wire are the conventional rules used in the industry at present, and the internal resistance of a driving source, namely the output impedance and the load termination impedance value are also set TO be 25 ohms conventionally. Fig. 8 is an overall assembly diagram of the high frequency interconnect. The series resistance of the 25G DFB laser diode chip was also set to 10.3 ohms. Fig. 9 is the high frequency simulation result of Ansoft HFSS thereof. It can be seen from FIG. 9 that the return loss is less than or equal to about-10.99 dB in the frequency range of 0-19 GHz.

For the case of the industry where a 2.5G TO header was modified TO use a 25G DFB TO laser, by contrast, the 25G DFB chip model of the present invention was also used TO simulate the Ansoft HFSS for high frequency interconnects. The result is: the return loss is higher than or equal to about-6 dB in the frequency range of 0-17 GHz.

Claims

1. A high-frequency interconnection method of 25G DFB lasers is characterized in that: the method comprises the following steps:

(2) establishing a high-frequency 3D structure HFSS simulation model of the DFB laser diode chip, verifying one or more designs in the step (1) through the simulation model, and then optimizing design parameters.

2. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: the ceramic substrate microstrip line in the step (1) comprises a left microstrip line and a right microstrip line which are designed asymmetrically, the left edge of a gap at a break is positioned on the right side of the symmetric center line of the ceramic substrate, and the chamfer angle at the 90-degree corner of the left microstrip line is larger than the chamfer angle at the 90-degree corner of the right microstrip line; the inlets of the left microstrip line and the right microstrip line are widened.

3. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: in the step (1), the DFB laser diode chip is attached to the left microstrip line, the center line of the light-emitting strip of the DFB laser diode chip is aligned with the symmetrical center line of the ceramic substrate, and the edge of the right side of the DFB laser diode chip enters the gap between the left microstrip line and the right microstrip line.

4. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: in the step (1), two bonding alloy wires are connected to the right microstrip line from the anode routing disc of the DFB laser diode chip, and an included angle is formed between the two bonding alloy wires.

5. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: and (1) increasing the impedance value of the driving source and the impedance value of the load terminal, and reducing the impedance deviation value of the equivalent load.

6. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: and (2) in the step (1), the gap position of the break-off position of the left microstrip line and the right microstrip line on the ceramic substrate enables the center line of the luminous strip of the DFB laser diode chip to be positioned on the central axis of the tube seat after the DFB laser diode chip is mounted, and the mounting position is determined according to the optimal return loss of the laser diode chip which enables high-frequency interconnection after mounting.

7. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: and (1) compensating parasitic inductive reactance caused by a gap between the ceramic substrate and the tube seat surface due to the chamfer angle at the joint of the ceramic substrate bearing base and the tube seat surface by adjusting the geometric shape at the inlet of the microstrip line of the high-frequency ceramic substrate.

8. The method for high frequency interconnection of 25G DFB lasers as claimed in claim 1, wherein: the simulation model in the step (2) has the actual appearance and size of a 25G DFB laser diode chip and summarizes the layer structure of the laser diode chip; the device comprises an upper electrode gold-plating layer (21), a BCB passivation layer (25), a SiO2 passivation layer (26), a p + -gallium indium arsenic ohmic contact layer (23), a p-indium phosphorus cladding layer (24), a grating layer (27), an MQW layer (28), an n-type substrate layer (29) and a lower electrode gold-plating layer (22); the p + -GaInAsAs ohmic contact layer (23), the p-InP cladding layer (24) form ridge-shaped bosses which are buried in a BCB passivation layer (25) and an SiO2 passivation layer (26).

9. The method of claim 8 for high frequency interconnection of 25G DFB lasers, wherein: simplifying the simulation model in the step (2) into an insulation region, a MQW region, a conductive region above the MQW region and a conductive region below the MQW region; the insulating region comprises a BCB passivation layer (25) and a SiO2 passivation layer (26), the conductive region above the MQW region comprises a ridge boss and a grating layer (27), and the conductive region below the MQW region comprises a substrate layer (29); the conductivity of the conductive region above and below the MQW region determines the resistance of the 25G DFB laser diode chip.