CN113612373B - Simple pulse complementary PWM generating circuit and method - Google Patents
Simple pulse complementary PWM generating circuit and method Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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Abstract
The invention discloses a simple pulse complementary PWM generating circuit and a method, comprising the following steps: the device comprises a pulse generating device, a controlled switching module, a first signal sending module and a second signal sending module; the first level signal and the second level signal which are alternately generated by the pulse generating device are continuously conducted and closed by the controlled switching module to alternately start the first signal sending module and the second signal sending module, so that the first test signal and the second test signal are alternately output, and the first test signal and the second test signal are complementary. The first test signal and the second test signal are input into the power module to be tested, and then the power module to be tested can be tested. Because the output signals of the invention are completely complementary and no dead time exists, the test result of the dead time of the power module to be tested is the real dead time of the power module to be tested.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a simple pulse complementary PWM generating circuit and a simple pulse complementary PWM generating method.
Background
In a certain power module of the inverter bridge, in order to avoid overheating caused by direct connection of the power module, and even damage to the inverter caused by loss of the power module, dead time is generally added into the power module, and the applied dead time is different due to different working conditions such as temperature and the like; each manufacturer also has different dead time settings for power devices according to the technical characteristics of the manufacturer; and when the power device is used for a long time, the built-in dead time of the power device can also change along with the loss of the module. Since the inverter output voltage and output current can be distorted with the addition of dead time, if the power module dead time is too large, the system becomes unstable for the case of an induction motor and can cause serious consequences of a series of breakdowns. Only when the dead time of the power module under different working conditions is accurately tested, the optimal dead time can be correctly adjusted through a control program in the use process, the normal work of the power module is ensured, and the distortion of output voltage and current is avoided to the maximum extent, so that the dead time test of the power module is necessary.
In the prior art, a resonant circuit is mostly adopted as a square wave generating device, and different numbers of inverters are used to enable PWM1 and PWM2 to form opposite phases. Since the PWM1 is generated by the original signal through one inverter and the PWM2 is generated by two inverters, the action time of the PWM2 is slower than that of the PWM1, and the time is a fixed value and cannot be eliminated. And since the original signal is generated by the resonant circuit whose frequency range is limited by the operational amplifier selected, the frequency is limited by the slew rate of the operational amplifier when high and the bias current and noise of the operational amplifier when low. And because a non-electrical isolation system is adopted, the inverter is used for driving the back stage, the output current is small, and the high-voltage high-current circuit is difficult to adapt to the condition of high voltage and high current. The PWM generating circuit based on the FPGA needs a special hardware programming language, the development difficulty is high, and the FPGA has the requirements of multiple voltage power supplies, so that a plurality of peripheral circuits are provided, the cost is high, the requirement on development and debugging personnel is high, and the operation is difficult.
Disclosure of Invention
The present invention provides a simple pulse complementary PWM generating circuit and method to overcome the above technical problems.
In order to realize the purpose, the technical scheme of the invention is as follows:
a simple pulse complementary PWM generating circuit, comprising: the device comprises a pulse generating device, a controlled switching module, a first signal sending module and a second signal sending module;
the input end VCC of the pulse generating device is connected with a first power supply VCC1, and the output end OUT of the pulse generating device is connected with a sixth resistor R6; one end of the seventh resistor R7 is connected with the sixth resistor R6, and the other end of the seventh resistor R7 is grounded;
the first signal sending module comprises a first signal sending device and a first resistor R1 which are connected in series; the second signal sending module comprises a second signal sending device and a second resistor R2 which are connected in series; one end of the first signal sending module is connected to the connection position of the controlled switching module and the first power supply VCC1; the other end of the first signal sending module and the second signal sending module are connected to the circuit interface A; the other end of the second signal sending module is grounded;
one end of the controlled switching module is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the other end is connected with the circuit interface A;
one end of a third capacitor C3 is connected with the circuit interface A, and the other end of the third capacitor C3 is connected to the ground connection position of the controlled switching module; the other end of the first power supply VCC1 is grounded.
Further, the pulse generating device adopts a 555 timer.
Further, the circuit also comprises a fourth resistor R4, a fifth resistor R5, a second capacitor C2 and a first capacitor C1; one end of the fourth resistor R4 is connected with the RST interface of the 555 timer, and the other end of the fourth resistor R4 is connected with the DIS interface of the 555 timer; the fourth resistor R4 is connected with the first power supply VCC1; one end of the fifth resistor R5 is connected to the connection position of the fourth resistor R4 and the DIS interface, and the other end of the fifth resistor R5 is connected to the first capacitor C1; the other end of the first capacitor C1 is grounded; the THR interface of the 555 timer is connected to the connection position of the fifth resistor R5 and the first capacitor C1; the TRI interface of the 555 timer is connected to the junction of the fifth resistor R5 and the THR interface of the 555 timer; a CON interface of the 555 timer is connected with the second capacitor C2; the other end of the second capacitor C2 is grounded.
Further, the controlled switching module comprises an MOS transistor Q and a third resistor R3; the grid G of the MOS tube Q is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the drain electrode D of the MOS tube Q is connected with a third resistor R3; the circuit interface A is connected with a drain electrode D of the MOS tube Q; the connection part of the source S of the MOS tube Q and the second signal sending module is grounded; the other end of the third resistor R3 is connected to the first power source VCC1.
Further, the controlled switching module is a logic device U3; one end of the logic device U3 is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the other end is connected to the circuit interface A.
Further, the first signal transmission device is a first optical fiber transmission module KP1, and the second signal transmission device is a second optical fiber transmission module KP2.
Further, the first signal transmitting device is a first passive optical coupler U1, and the second signal transmitting device is a second passive optical coupler U2.
Further, one end of a secondary side of a first secondary side of the first passive optocoupler U1 is grounded, and the other end of the secondary side of the first passive optocoupler U1 is connected with an eighth resistor R8; the other end of the eighth resistor R8 is connected with a second power supply VCC2, and the other end of the second power supply VCC2 is grounded;
the secondary side one end ground connection of second passive opto-coupler U2, the other end is connected with ninth resistance R9, ninth resistance R9's the other end and second power VCC2 are connected.
Further, the TLP627 is adopted by both the first passive optical coupler U1 and the second passive optical coupler U2.
A simple pulse complementary PWM generation method comprises the following steps:
s101: connecting a power supply to an input end VCC of the pulse generating device, wherein the pulse generating device alternately outputs a first level signal and a second level signal;
s102: when the level of the pulse square wave signal output by the pulse generating device is changed from a first level signal level to a second level signal level, the controlled switching device is switched on, and the voltage of a point A of the circuit interface is equal to a first voltage value;
s103: starting a first signal sending module and outputting a first test signal;
s104: when the pulse square wave signal output by the pulse generating device is changed from the level of a second level signal to a first level signal, the controlled switching device is not conducted, and the voltage of the A point of the circuit interface is equal to a second voltage value;
s105: starting a second signal sending module and outputting a second test signal;
a106: cycling the steps 102 to 105 to alternately output a first test signal and a second test signal; the first test signal and the second test signal are complementary.
Has the beneficial effects that: according to the simple pulse complementary PWM generating circuit and the method, the first level signal and the second level signal which are alternately generated by the pulse generating device are used for continuously conducting and closing the controlled switching module so as to alternately start the first signal sending module and the second signal sending module, and then the first test signal and the second test signal are alternately output and are complementary. The first test signal and the second test signal are input into the power module to be tested, and then the power module to be tested can be tested. Because the output signals of the invention are completely complementary and no dead time exists, the test result of the dead time of the power module to be tested is the real dead time of the power module to be tested.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit diagram of an optical signal output by a signal transmitting module according to the present invention;
FIG. 2 is a circuit diagram of the signal transmitting module outputting an electrical signal according to the present invention;
FIG. 3 is a circuit diagram of the simulation of the optical signal output by the signal transmitting module according to the present invention;
FIG. 4 is a circuit diagram of the present invention showing the simulation of the signal transmission module outputting an electrical signal;
FIG. 5 is a flow chart of a PWM generation circuit method of the present invention;
fig. 6 is a circuit diagram of another embodiment of a controlled switching module according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present embodiment provides a simple pulse complementary PWM generating circuit, as shown in fig. 1 and 2, including: the device comprises a pulse generating device, a controlled switching module, a first signal sending module and a second signal sending module;
the input end VCC of the pulse generating device is connected with a first power supply VCC1, and the output end OUT of the pulse generating device is connected with a sixth resistor R6; one end of the seventh resistor R7 is connected with the sixth resistor R6, and the other end of the seventh resistor R7 is grounded;
the first signal sending module comprises a first signal sending device and a first resistor R1 which are connected in series; the second signal sending module comprises a second signal sending device and a second resistor R2 which are connected in series; one end of the first signal sending module is connected to the connection position of the controlled switching module and the first power supply VCC1; the other end of the first signal sending module and the second signal sending module are connected to the circuit interface A; the other end of the second signal sending module is grounded;
one end of a third capacitor C3 is connected with the circuit interface A, and the other end of the third capacitor C3 is connected with the controlled switching module and is connected out in a grounding mode; the other end of the first power supply VCC1 is grounded.
One end of the controlled switching module is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the other end of the controlled switching module is connected to the circuit interface A;
in one embodiment, the controlled switching module comprises a MOS transistor Q and a third resistor R3; the grid G of the MOS tube Q is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the drain electrode D of the MOS tube Q is connected with a third resistor R3; the circuit interface A is connected with a drain electrode D of the MOS tube Q; the circuit interface between the third resistor R3 and the first resistor R1 is connected to a first power supply VCC1; the joint of the controlled switching module and the second signal sending module is grounded; the other end of the first power supply VCC1 is grounded.
Specifically, in the controlled switching module in this embodiment, the MOS transistor Q is adopted to convert the first level signal and the second level signal alternately output from the pulse generating device into the complementary first test signal and second test signal, and output the complementary first test signal and second test signal, so as to provide the input signal for the power module to be tested.
The grid G of the MOS tube Q is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the drain electrode D of the MOS tube Q is connected with a third resistor R3; the first signal sending module and a circuit interface A of the second resistor R2 are connected to a drain electrode D of the MOS tube Q; the other end of the second signal sending module is connected with a source electrode S of the MOS tube Q; the source electrode S of the MOS tube Q is grounded; the third resistor R3 and the first resistor R1 are connected to a first power supply VCC1 through circuit interfaces. Specifically, the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 change along with the value change of the first power VCC, in this embodiment, the first resistor R1 is equal to the second resistor R2, and the resistance value of the third resistor R3 is far smaller than the resistance value of the first resistor R1 which is equal to the second resistor R2. One end of the third capacitor C3 is connected with the circuit interface A, and the other end of the third capacitor C3 is grounded; the third capacitor C3 can prevent the level overvoltage and burrs when the MOS transistor Q is switched on and off. The capacitance of the third capacitor C3 should not be too large, and is indispensable.
Preferably, the pulse generator used in this embodiment is a 555 timer, and the generator is simple and easy to obtain, and is convenient to operate. The PWM generating circuit of this embodiment further includes a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a first capacitor C1; one end of the fourth resistor R4 is connected with an RST interface of the 555 timer, and the other end of the fourth resistor R4 is connected with a DIS interface of the 555 timer; the fourth resistor R4 is connected with the first power supply VCC1; one end of the fifth resistor R5 is connected to the connection position of the fourth resistor R4 and the DIS interface, and the other end of the fifth resistor R5 is connected to the first capacitor C1; the other end of the first capacitor C1 is grounded; the THR interface of the 555 timer is connected to the connection position of the fifth resistor R5 and the first capacitor C1; the TRI interface of the 555 timer is connected to the junction of the fifth resistor R5 and the THR interface of the 555 timer; a CON interface of the 555 timer is connected with the second capacitor C2; the other end of the second capacitor C2 is grounded. Specifically, the second capacitor C2 can remove interference of a high-frequency signal, and plays a role of filtering, and the capacitance value thereof is 10nf.
Specifically, the 555 timer can freely select the frequency and the duty ratio of the generated pulse square wave signal according to the difference of the values of the fourth resistor R4, the fifth resistor R5 and the first capacitor C1. Wherein, the turn-on threshold voltage of the MOS transistor Q is V GS The output end OUT of the 555 timer is still a pulse square wave signal after being subjected to voltage division by the sixth resistor R6 and the seventh resistor R7, the frequency and the duty ratio are not changed, the frequency and the duty ratio are the same as those of the output end OUT, and the voltage value of the second level signal is [ (VCC R7)/(R7 + R6) at the moment]The resistance values of the sixth resistor R6 and the seventh resistor R7 are adjusted to enable the turn-on threshold voltage of the second level signal to be greater than or equal to the turn-on threshold voltage of the MOS transistor Q to be V GS 。
In one embodiment of the present invention, the first signal transmission device is a first optical fiber transmission device KP1, and the second signal transmission device is a second optical fiber transmission device KP2; the first optical fiber transmission device KP1 and the second optical fiber transmission device KP2 both adopt a HighH-HFBR 1521. When the square wave signal generated by the 555 timer is changed from the first level signal to the second level signal, the MOS tube Q is switched on. At the moment, the voltage of the point A is sharply reduced from VCC to be close to 0V, at the moment, the two ends of KP1 generate voltage difference, the inside generates current, KP1 sends out an optical signal, at the moment, the two ends of KP2 have no voltage difference, and KP2 does not send out the optical signal; after the square wave signal that 555 timer produced becomes first level signal by the second level signal, MOS pipe Q disconnection, the A point voltage rises to first power VCC by being close to 0V rapidly this moment, when A point voltage is for being close VCC, KP2 both ends produce the pressure differential, and there is the electric current inside, KP2 sends optical signal, and no pressure differential at KP1 both ends this moment, KP1 does not send optical signal. The square wave signal of the 555 timer is continuously output, the output signal of the 555 timer is continuously changed from the first level signal to the second level signal and then changed from the second level signal to the first level signal, so that the MOS tube Q is alternately switched on and off, the KP1 and the KP2 alternately send out optical signals, and the KP1 and the KP2 cannot simultaneously generate optical signals, so that the output signal of the embodiment has no dead time.
In another embodiment of the present invention, the first signal sending device is a first passive optical coupler U1, and the second signal sending device is a second passive optical coupler U2. The TLP627 is adopted by the first passive optocoupler U1 and the second passive optocoupler U2.
One end of a first secondary side of the first passive optocoupler U1 is grounded, and the other end of the first secondary side of the first passive optocoupler U1 is connected with an eighth resistor R8; the other end of the eighth resistor R8 is connected with a second power supply VCC2, and the other end of the second power supply VCC2 is grounded; and one end of a second secondary side of the second passive optocoupler U2 is grounded, the other end of the second secondary side of the second passive optocoupler U2 is connected with a ninth resistor R9, and the other end of the ninth resistor R9 is connected with a second power supply VCC2.
When the square wave signal generated by the 555 timer is changed into a second level signal, the MOS tube Q is conducted. At this time, the voltage of the point A is sharply reduced from VCC to be close to 0V, when the voltage of the point A is 0V, the primary side of the U1 generates a voltage difference, the inside of the primary side of the U1 has current, the secondary side of the U1 is conducted, the voltage of the point B to the GND2 is 0, the primary side of the U2 has no voltage, the secondary side of the U2 is not conducted, and the voltage of the point C to the GND2 is VCC2.
After the square wave signal that the 555 timer produced becomes first level signal by the second level signal, MOS pipe Q disconnection, the A point voltage rose to be close VCC by 0V rapidly this moment, when A point voltage is VCC, U2 primary side once inclines and produces the pressure differential, and inside has the electric current, and U2 secondary side switches on, and the C point is 0 to GND 2's voltage, and U1 primary side once inclines no pressure differential this moment, and U1 secondary side does not switch on, and B point to GND 2's voltage is VCC2.
The square wave signal of the 555 timer is continuously output, the output signal of the 555 timer is continuously changed into a second level signal from a first level signal and then is changed into the first level signal from the second level signal, so that the MOS tube Q is alternately switched on and off, the primary side and the primary side of the U1 and the primary side of the U2 alternately generate pressure difference, the secondary side and the secondary side are alternately switched on, and the secondary sides of the U1 and the U2 cannot be simultaneously switched on. The PWM square wave voltage signal appearing at the point B to the ground GND2 is completely complementary to the PWM square wave voltage signal appearing at the point C to the ground GND2, so that the dead time does not exist in the output signal of the present embodiment as well.
In a simulation experiment of the present invention, as shown in fig. 3 and fig. 4, two LED lamps are used to replace an optical fiber transmitting module or a passive optical coupler in a first signal transmitting module and a second signal transmitting module, and when the LED lamps are on, a signal is transmitted from the optical fiber transmitting module and the secondary side of the passive optical coupler is conducted; when the LED lamp is turned off, the optical fiber sending module is turned off and the secondary side of the passive optocoupler is not conducted. The period of the output pin of the 555 timer out is calculated as T =0.693 (R4 +2 R5) C1; the frequency is: f =1/T; duty ratio: d = (R5/(R4 +2 × R5)), during the test, the on/off switching of the LED lamps was performed simultaneously due to the continuous state of the circuit, indicating that the signals generated by the transmitting module in this test are complementary and there is no dead time.
In a third embodiment of the present invention, the controlled switching module employs a logic device U3, which selects one inverter, as shown in fig. 6, in which a high-low threshold voltage V1 is output. The output OUT of the 555 timer passes through a resistor R6, after the voltage is divided by the resistor R7, the frequency and the duty ratio of the output OUT are the same as those of the output OUT, and the high level is [ (VCC R7)/(R7 + R6) ]. Through the resistance of adjustment R7, R6, make [ (VCC R7)/(R7 + R6) ] more than or equal to V1, 555 timer production square wave signal like this and after the signal becomes second level signal by first level signal, the voltage of point A descends by VCC to be close 0V, when waiting for A point to be 0V, KP1 both ends produced the pressure differential, and inside has the electric current, KP1 sends light signal. At this time, no pressure difference exists between two ends of KP2, no current exists inside KP2, and KP2 does not send out optical signals.
The 555 timer generates a square wave signal, and after the signal is changed from the second level signal to the first level signal, the voltage of the point A is increased from 0V to be close to VCC. When the voltage of the point A is equal to VCC, the two ends of KP2 generate voltage difference, the inside of KP2 has current, and KP2 sends out light signals. At this time, no pressure difference exists between two ends of KP1, no current exists inside, and KP1 does not send out optical signals.
Therefore, the square wave signal accompanied with the 555 timer is continuously output. Namely, the square wave signal of the 555 timer is changed into the first level signal from the second level signal continuously, and then is changed into the second level signal from the first level signal. The output state of the U3 is continuously changed, and the first level signal and the second level signal alternately appear. Eventually causing KP1 and KP2 to alternately emit optical signals. And KP1 and KP2 cannot have optical signals at the same time.
The invention also discloses a simple pulse complementary PWM generation method, which comprises the following steps as shown in the attached figure 5:
s101: connecting a power supply to an input end VCC of the pulse generating device, wherein the pulse generating device alternately outputs a first level signal and a second level signal;
s102: when the level of the pulse square wave signal output by the pulse generating device is changed from a first level signal level to a second level signal level, the controlled switching device is switched on, and the voltage of a point A of the circuit interface is equal to a first voltage value;
s103: starting a first signal sending module and outputting a first test signal;
s104: when the pulse square wave signal output by the pulse generating device is changed from the level of a second level signal to a first level signal, the controlled switching device is not conducted, and the voltage of the A point of the circuit interface is equal to a second voltage value;
s105: starting a second signal sending module and outputting a second test signal;
a106: cycling the steps 102 to 105 to alternately output a first test signal and a second test signal; the first test signal and the second test signal are complementary.
The first test signal and the second test signal generated by the embodiment are input into the power module to be tested, and the power module to be tested is tested.
Specifically, in this embodiment, a 555 timer alternately outputs a first level signal and a second level signal, when a pulse square wave signal output by the pulse generating device changes from a first level signal level to a second level signal level, the controlled switching device is turned on, a voltage at a point a of the circuit interface is equal to a first voltage value, and the first voltage value in this embodiment is close to 0V; starting a first signal sending module at the moment, and outputting a first test signal; when the pulse square wave signal output by the pulse generating device is changed from the second level signal level to the first level signal level, the controlled switching device is not switched on, the voltage of the point A of the circuit interface is equal to a second voltage value, and the second voltage value in the embodiment is close to the voltage value of the first power supply VCC1; starting a second signal sending module at the moment, and outputting a second test signal; and repeating the steps, namely, alternately outputting a first test signal and a second test signal, wherein the first test signal and the second test signal are complementary. The first test signal and the second test signal are input into the power module to be tested, and the power module to be tested can be tested.
In the embodiment, a certain upper bridge arm and lower bridge arm pulse test of the inverter bridge is taken as an example, in order to avoid overheating, IGBT loss and even damage of the inverter caused by direct connection of IGBT bridge arms, dead time is generally added to the IGBT in working, because the output voltage and the output current of the inverter are distorted along with the addition of the dead time, if the dead time of the IGBT is too large, a system becomes unstable under the condition of an induction motor, and a series of serious consequences of breakdown can be caused.
And the first test signal and the second test signal are input to the IGBT drive board to test the IGBT drive board. Because the first test signal and the second test signal output by the invention are completely complementary, and no dead time exists, the dead time test of the power module to be tested is not interfered, and the test result is accurate.
The invention has the following beneficial effects:
1. the current flowing through the first signal transmitting module and the second signal transmitting module by the PWM generating circuit of the present invention may be changed according to the specific models of the first signal transmitting device and the second signal transmitting device. The current can be adjusted by changing the resistance values of the resistor R1 and the resistor R2. Therefore, the invention can convert the light pulse output into the electric pulse output by changing the output device in the main circuit, namely changing the optical fiber output module into the passive optical coupler, thereby greatly expanding the application scene of the invention. Not only has high engineering application value, but also has wide market application prospect.
2. The frequency and the duty ratio of the whole complementary output PWM signal can be configured by adjusting the parameters of the resistor R4, the resistor R5 and the first capacitor C1, and an operator can finish the complementary output PWM signal without complex operation. Low cost and simple and convenient operation.
3. The voltage dividing operation is performed using the resistor R6 and the resistor R7. The resistance values of R6 and R7 can be modified according to the selected controlled switching module, so that the square wave signal subjected to voltage division can be switched on the controlled switching module in the high-level period, and the controlled switching module is switched off in the low-level period. The voltage division operation is realized, and the selection and the replacement of the controlled switching module are flexible.
4. The output signals of the invention are completely complementary, and no dead time exists, so that the dead time of the power module to be tested can be accurately tested.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A simple pulse complementary PWM generating circuit, comprising: the device comprises a pulse generating device, a controlled switching module, a first signal sending module and a second signal sending module;
the input end VCC of the pulse generating device is connected with a first power supply VCC1, and the output end OUT of the pulse generating device is connected with a sixth resistor R6; one end of the seventh resistor R7 is connected with the sixth resistor R6, and the other end of the seventh resistor R7 is grounded;
the first signal sending module comprises a first signal sending device and a first resistor R1 which are connected in series; the second signal sending module comprises a second signal sending device and a second resistor R2 which are connected in series; one end of the first signal sending module is connected to the connection position of the controlled switching module and the first power supply VCC1; the other end of the first signal sending module and the second signal sending module are connected to the circuit interface A; the other end of the second signal sending module is grounded;
one end of the controlled switching module is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the other end is connected with the circuit interface A;
one end of a third capacitor C3 is connected with the circuit interface A, and the other end of the third capacitor C3 is connected to the ground connection position of the controlled switching module; the other end of the first power supply VCC1 is grounded;
the pulse generating device includes:
the circuit also comprises a fourth resistor R4, a fifth resistor R5, a second capacitor C2 and a first capacitor C1; one end of the fourth resistor R4 is connected with an RST interface of the 555 timer, and the other end of the fourth resistor R4 is connected with a DIS interface of the 555 timer; the fourth resistor R4 is connected to the first power supply VCC1; one end of the fifth resistor R5 is connected to the connection position of the fourth resistor R4 and the DIS interface, and the other end of the fifth resistor R5 is connected to the first capacitor C1; the other end of the first capacitor C1 is grounded; the THR interface of the 555 timer is connected to the connection position of the fifth resistor R5 and the first capacitor C1; the TRI interface of the 555 timer is connected to the junction of the fifth resistor R5 and the THR interface of the 555 timer; a CON interface of the 555 timer is connected with the second capacitor C2; the other end of the second capacitor C2 is grounded.
2. The simple pulse complementary PWM generating circuit as claimed in claim 1, wherein said pulse generating device uses 555 timer.
3. The simple pulse complementary PWM generating circuit according to claim 1, wherein said controlled switching module comprises a MOS transistor Q and a third resistor R3; the grid G of the MOS tube Q is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the drain electrode D of the MOS tube Q is connected with a third resistor R3; the circuit interface A is connected with a drain electrode D of the MOS tube Q; the connection part of the source S of the MOS tube Q and the second signal sending module is grounded; the other end of the third resistor R3 is connected to the first power VCC1.
4. The simple pulse-complementary PWM generating circuit according to claim 1, wherein said controlled switching module is a logic device U3; one end of the logic device U3 is connected to the connection position of the sixth resistor R6 and the seventh resistor R7; the other end is connected to the circuit interface A.
5. The simple pulse-complementary PWM generating circuit according to claim 1, wherein said first signal transmission device is a first fiber transmission module KP1, and said second signal transmission device is a second fiber transmission module KP2.
6. The simple pulse complementary PWM generating circuit according to claim 1, wherein said first signal transmitting means is a first passive optocoupler U1, and said second signal transmitting means is a second passive optocoupler U2.
7. The simple pulse complementary PWM generating circuit according to claim 6, wherein one end of a secondary side of a first secondary side of the first passive optocoupler U1 is grounded, and the other end of the first secondary side of the first passive optocoupler U1 is connected with an eighth resistor R8; the other end of the eighth resistor R8 is connected with a second power supply VCC2, and the other end of the second power supply VCC2 is grounded;
and one end of a second secondary side of the second passive optocoupler U2 is grounded, the other end of the second secondary side of the second passive optocoupler U2 is connected with a ninth resistor R9, and the other end of the ninth resistor R9 is connected with a second power supply VCC2.
8. The simple pulse complementary PWM generating circuit as claimed in claim 6, wherein said first passive optocoupler U1 and said second passive optocoupler U2 both use TLP627.
9. A method according to claim 1, wherein the method comprises the steps of:
s101: connecting a power supply to an input end VCC of the pulse generating device, wherein the pulse generating device alternately outputs a first level signal and a second level signal;
s102: when the pulse square wave signal output by the pulse generating device is changed from a first level signal level to a second level signal level, the controlled switching device is switched on, and the voltage of a point A of the circuit interface is equal to a first voltage value;
s103: starting a first signal sending module and outputting a first test signal;
s104: when the pulse square wave signal output by the pulse generating device is changed from the level of a second level signal to a first level signal, the controlled switching device is not conducted, and the voltage of the A point of the circuit interface is equal to a second voltage value;
s105: starting a second signal sending module and outputting a second test signal;
a106: the steps 102 to 105 are circulated, and a first test signal and a second test signal are alternately output; the first test signal and the second test signal are complementary.
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