CN218102943U - Cycle-by-cycle peak control circuit - Google Patents

Abstract

The utility model relates to a cycle-by-cycle peak control circuit, it includes PWM signal unit, the comparison unit, logic unit and pulse width modulation unit, PWM signal unit is used for inputing and outputting the PWM signal after the processing, the comparison unit is used for acquireing and comparing spike voltage signal and preset voltage signal and output comparison signal, logic unit is used for carrying out logical operation and output switch control signal with PWM input signal and comparison signal, the input of pulse width modulation unit is connected to logic unit, the output of pulse width modulation unit is connected between the input of PWM signal unit and output, pulse width modulation unit is based on switch control signal output pulse width modulation signal to the PWM modulation signal pulse width of control PWM signal output. According to the method and the device, the PWM modulation signal is adopted for frequency modulation and width modulation, and compared with the mode of frequency-fixed and width modulation for controlling the periodic peak voltage, the method and the device are more flexible.

Description

Cycle-by-cycle peak control circuit

Technical Field

The present application relates to the field of control circuits, and more particularly, to a cycle-by-cycle peak control circuit.

Background

At present, the equipment driving circuit using alternating voltage is easily affected by unstable voltage under the condition of dynamic characteristic output, if the equipment driving circuit receives the impact of spike voltage, the transient high voltage can cause overlarge current to appear, so that a large amount of heat can be generated, the service life of the equipment is shortened, and even the equipment is damaged, so that the danger of overcurrent caused by the spike voltage is avoided, the current periodic peak value control is usually performed by using a fixed frequency mode, for example, a power supply control IC: the UC3846, UC3845 and the like, all use a fixed frequency and width modulation mode to control the current magnitude under the peak voltage cycle by cycle, so as to protect the circuit from being damaged by overcurrent.

However, peak control using UC3846, UC3845, or the like, employs a fixed frequency bandwidth, and does not have the flexibility required by the control circuit.

In view of the above situation, the present application provides a cycle-by-cycle peak control circuit for improving the flexibility of cycle-by-cycle peak control.

SUMMERY OF THE UTILITY MODEL

In order to improve the flexibility of cycle-by-cycle peak control, the application provides a cycle-by-cycle peak control circuit

The application provides a cycle-by-cycle peak control circuit adopts following technical scheme:

a cycle-by-cycle peak control circuit comprising:

a PWM signal unit, one end of which is used for inputting a PWM input signal and the other end of which is used for outputting a PWM output signal;

the comparison unit is used for acquiring and comparing the PEAK voltage signal PEAK with a preset voltage signal VREF, and outputting a comparison signal based on a comparison result;

the input end of the logic unit is connected with the PWM signal unit and the comparison unit, and the logic unit is used for carrying out logic operation on a PWM input signal and a comparison signal and outputting a PWM switch control signal;

the input end of the pulse width modulation unit is connected with the logic unit, a switch control point is formed between the input end of the PWM signal unit and the output end of the PWM signal unit, the output end of the pulse width modulation unit is connected with the switch control point, the pulse width modulation unit outputs a pulse width modulation signal to the switch control point based on the PWM switch control signal, and the switch control point controls the pulse width of a PWM output signal output by the PWM signal output end based on the pulse width modulation signal.

By adopting the technical scheme, the PWM signal unit can input the pulse width modulation signal, and a user can adjust the pulse width of the input PWM input signal according to actual working conditions under different working scenes so as to meet different operation requirements.

The comparison unit can acquire a PEAK voltage signal PEAK and a preset voltage signal VREF, compare the acquired PEAK voltage signal PEAK with the preset voltage signal VREF, and transmit a comparison signal to the logic unit based on a comparison result, and the logic unit can acquire the comparison signal output by the comparison unit, perform logical operation on the comparison signal and a PWM modulation signal output by the PWM signal unit, and output a PWM switch control signal.

When the comparison result shows that the peak voltage exceeds the preset voltage, the comparison signal output by the comparison unit can output a high-level PWM (pulse width modulation) switch control signal to the pulse width modulation unit after the operation of the logic unit, and correspondingly, when the comparison result shows that the peak voltage does not exceed the preset voltage, the comparison signal output by the comparison unit can output a low-level PWM switch control signal to the pulse width modulation unit after the operation of the logic unit.

Subsequently, the pulse width modulation unit will generate a pulse width modulation signal after receiving the PWM switching control signal of high level, so that the switching control point outputs high level, and correspondingly, the pulse width modulation unit will generate a pulse width modulation signal after receiving the PWM switching control signal of low level, so that the switching control point outputs low level.

Optionally, the PWM signal unit includes a phase shift unit, the PWM signal input by the PWM signal unit includes a PWM1 signal and a PWM2 signal, the frequency of the PWM2 signal is one half of the frequency of the PWM1 signal, the phase shift unit is connected between the input end of the PWM signal unit and the switch control point, the phase shift unit is configured to modulate the input PWM1 signal and the input PWM2 signal, and output a PWM3A signal and a PWM4A signal with a phase difference of 180 degrees after modulation, and the dead time of the PWM3A signal and the PWM4A signal is the off time of the PWM1 signal.

By adopting the technical scheme, because the complementary modulation signals with the phase difference of 180 degrees are required to be used as the signal source of the inversion driving in the driving work of the equipment needing voltage inversion, two paths of PWM signals, namely PWM1 signals and PWM2 signals, are input by the PWM signal source, and the two paths of input signals are subjected to phase shifting into PWM3A signals and PWM4A signals with the phase difference of 180 degrees by adopting the phase shifting unit.

Optionally, the duty ratio of the PWM1 signal is 95%, the duty ratio of the PWM2 signal is 50%, and the PWM3A and the PWM4A have a phase difference of 180 degrees with a complementary waveform and a dead time of 5%.

Optionally, the phase shift unit includes:

the first waveform shaping element T1 is connected to the input end of the PWM1 signal;

a first two-input AND gate AND1, one input end of which is connected to the output end of the first waveform shaping element T1, AND the other input end of which inputs the PWM2 signal;

the second wave shaping element T2 is connected to the input end of the PWM2 signal;

a second input AND gate AND2, one input terminal of which is connected to the output terminal of said first waveform shaping element T1, AND the other input terminal of which is connected to the output terminal of said second waveform shaping element T2;

the third waveform shaping element T3 is connected to the output end of the second input AND gate AND2 AND outputs the PWM3A signal;

AND a fourth waveform shaping element T4 connected to the output terminal of the first two-input AND gate AND1 AND outputting the PWM4A signal.

By adopting the technical scheme, the waveform shaping element can shape the waveform into a square waveform which can be processed by a digital circuit, AND the anti-interference capability is strong, the PWM1 signal AND the PWM2 signal are subjected to logical AND operation when passing through the first two-input AND gate AND1 to output a PWM4A signal, the PWM1 signal AND the PWM2 signal are subjected to logical AND operation when passing through the second two-input AND gate AND2 to output a PWM3A signal, the PWM3A signal AND the PWM4A signal are complementary signals with the phase difference of 180 degrees, AND the dead time of the PWM3A signal AND the PWM4A signal is the PWM1 closing time.

Optionally, the first waveform shaping element T1, the second waveform shaping element T2, the third waveform shaping element T3, and the fourth waveform shaping element T4 are all schmitt triggers.

By adopting the technical scheme, as the Schmitt trigger, if the input voltage is higher than the forward threshold voltage, the output is high; if the input voltage is lower than the negative threshold voltage, the output is low; when the input voltage is between the positive and negative threshold voltages, the output is unchanged, that is, the output is turned from the high level to the low level, or from the low level to the high level, the corresponding threshold voltages are different, and only when the input voltage is changed enough, the output is changed, and the hysteresis phenomenon exists. Therefore, the Schmitt trigger can be used as a waveform shaping element, and the hysteresis characteristic of the Schmitt trigger enables the anti-interference capability to be strong.

Optionally, the comparing unit includes:

the PEAK voltage branch circuit is used for inputting a PEAK voltage signal PEAK;

the preset voltage branch is used for inputting a preset voltage signal VREF;

and a non-inverting input end of the comparator U1C is connected to the preset voltage branch, an inverting input end of the comparator U1C is connected to the peak voltage branch, a negative feedback resistor R4 is connected between an output end and the non-inverting input end of the comparator U1C, and an output end of the comparator U1C outputs a comparison signal.

By adopting the technical scheme, the preset voltage signal VREF is input into the non-inverting input end of the comparator U1C, the PEAK voltage signal PEAK is input into the inverting input end of the comparator U1C, when the PEAK voltage is greater than the preset voltage, the output end of the comparator U1C outputs a low-level comparison signal, and when the PEAK voltage is less than the preset voltage, the output end of the comparator U1C outputs a high-level comparison signal.

Optionally, the preset voltage branch includes a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series between a power supply and a ground, a preset voltage point is formed between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the preset voltage point is connected to the non-inverting input end of the comparator U1C and is used for inputting the preset voltage signal VREF.

By adopting the above technical scheme, the voltage at the preset voltage point is the result of voltage division of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the voltage at the preset voltage point is input to the non-inverting input terminal of the comparator U1C as the preset voltage.

Optionally, the pulse width modulation unit includes:

the grid electrode of the NMOS switch tube Q1 is connected with the output end of the logic unit, the source electrode of the NMOS switch tube Q1 is connected with the ground wire, the drain electrode of the NMOS switch tube Q1 is connected with the switch control point, and the NMOS switch tube Q1 is used for generating a pulse width modulation signal;

and the first resistor R3, wherein the first resistor R3 is connected between the grid electrode and the source electrode of the NMOS switch tube Q1.

By adopting the technical scheme, the voltage at two ends of the first resistor R3 is equal to the voltage between the grid electrode and the source electrode of the NMOS switch tube Q1, and because the source electrode of the NMOS switch tube Q1 is connected with the ground wire, when the PWM switch control signal output by the logic unit is in a low level, the grid-source voltage of the NMOS switch tube Q1 is smaller than the turn-on voltage of the NMOS switch tube Q1, namely Vgs < Vt, the NMOS switch tube Q1 is in a cut-off state, namely id =0; correspondingly, when the PWM switch control signal outputted from the logic unit is at a high level, the gate-source voltage of the NMOS switch Q1 is greater than the turn-on voltage of the NMOS switch Q1, i.e., vgs > Vt, and therefore, the NMOS switch Q1 is in a conducting state.

Optionally, the switch control points include a PWM3A signal switch control point located on the PWM3A signal output branch and a PWM4A signal switch control point located on the PWM4A signal output branch,

the pulse width modulation unit further includes:

the input end of the first diode D1 is connected to the PWM3A signal switch control point, and the output end of the first diode D1 is connected to the drain electrode of the NMOS switch tube Q1;

and the input end of the second diode D2 is connected to the PWM4A signal switch control point, and the output end of the second diode D2 is connected to the drain electrode of the NMOS switch tube Q1.

By adopting the technical scheme, the PWM3A signal switch control point and the PWM4A signal switch control point are connected to the drain electrode of the NMOS switch tube Q1, when the NMOS switch tube Q1 is conducted, the PWM3A signal switch control point and the PWM4A signal switch control point can be connected with the ground wire through the NMOS switch tube Q1, therefore, the PWM3A signal output branch and the PWM4A signal output branch are both in a low level state, when the NMOS switch tube Q1 is turned off, the PWM3A signal switch control point and the PWM4A signal switch control point can not be connected with the ground wire through the NMOS switch tube Q1, therefore, the PWM3A signal output branch and the PWM4A signal output branch are both in a high level state, and therefore the PWM output signal controlled by the pulse width modulation unit can be output.

In summary, the present application includes at least one of the following beneficial technical effects:

1. the PWM input signal is adopted for frequency modulation and width modulation, and the PWM switch control signal generated by the comparison unit and the logic unit controls the output pulse width of the PWM output signal, so that the method is more flexible compared with the method for controlling the cycle-by-cycle peak voltage in a mode of frequency modulation and width modulation.

2. The Schmitt trigger is used as a waveform shaping element, and the hysteresis characteristic of the Schmitt trigger enables the anti-interference capability to be stronger.

Drawings

Fig. 1 is a logic block diagram of a cycle-by-cycle peak control circuit in an embodiment of the present application.

Fig. 2 is a circuit diagram of a cycle-by-cycle peak control circuit in an embodiment of the present application.

Fig. 3 is a waveform diagram of a cycle-by-cycle signal of a cycle-by-cycle peak control circuit according to an embodiment of the present application.

Description of the reference numerals:

1. a PWM signal unit; 11. a phase shift unit; 2. a comparison unit; 21. a peak voltage branch; 22. presetting a voltage branch; 3. a logic unit; 4. and a pulse width modulation unit.

Detailed Description

The present application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the inventive concepts. As part of this description, some of the drawings of the present disclosure represent structures and devices in block diagram form in order to avoid complicating the disclosed principles. In the interest of clarity, not all features of an actual implementation are described in this specification. Reference in the present disclosure to "one implementation" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation, and references to "one implementation" or "an implementation" are not to be understood as necessarily all referring to the same implementation.

The terms "a," "an," and "the" are not intended to refer to a singular entity, unless specifically limited, but rather include the general class of which a specific example may be used for illustration. Thus, use of the terms "a" or "an" can mean any number of at least one, including "a," one or more, "" at least one, "and" one or more than one. The term "or" means any of the alternatives and any combination of alternatives, including all alternatives, unless alternatives are explicitly indicated as mutually exclusive. The phrase "at least one of," when combined with a list of items, refers to a single item in the list or any combination of items in the list. The phrase does not require all of the listed items unless explicitly so limited.

The embodiment of the application discloses a cycle-by-cycle peak control circuit. Referring to fig. 1, a cycle-by-cycle peak control circuit includes a PWM signal unit 1, a comparison unit 2, a logic unit 3, and a pulse width modulation unit 4, specifically, one end of the PWM signal unit 1 is used for inputting a PWM input signal, and the other end is used for outputting a PWM output signal, so that a user can adjust the pulse width of the input PWM output signal according to actual working conditions in different working scenes to meet different operation requirements.

The comparison unit 2 is used for obtaining and comparing the PEAK voltage signal PEAK with a preset voltage signal VREF, and outputting a comparison signal based on a comparison result, the input end of the logic unit 3 is connected to the PWM signal unit 1 and the comparison unit 2, the logic unit 3 is used for performing logic operation on the PWM input signal and the comparison signal and outputting a PWM switching control signal, when the comparison result shows that the PEAK voltage exceeds the preset voltage, the comparison signal output by the comparison unit 2 can output a PWM switching control signal with a high level to the pulse width modulation unit 4 after the operation of the logic unit 3, and correspondingly, when the comparison result shows that the PEAK voltage does not exceed the preset voltage, the comparison signal output by the comparison unit 2 can output a PWM switching control signal with a low level to the pulse width modulation unit 4 after the operation of the logic unit 3.

Referring to fig. 1 and2, in various embodiments, the preset voltage may be generated in various manners, and as an example, the preset voltage branch 22 includes a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series between the power supply and the ground, a preset voltage point is formed between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the preset voltage point is connected to the comparing unit 2 for inputting the preset voltage signal VREF. The voltage at the predetermined voltage point is a result of voltage division by the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the voltage at the predetermined voltage point is input to the comparing unit 2 as the predetermined voltage.

The input end of the pulse width modulation unit 4 is connected with the logic unit 3, a switch control point is formed between the input end of the PWM signal unit 1 and the output end of the PWM signal unit 1, the output end of the pulse width modulation unit 4 is connected with the switch control point, the pulse width modulation unit 4 outputs a pulse width modulation signal to the switch control point based on the PWM switch control signal, and the switch control point controls the pulse width of the PWM signal output by the PWM signal output end based on the pulse width modulation signal. The pulse width modulation unit generates a pulse width modulation signal after receiving the high-level PWM switch control signal, so that the switch control point outputs a high level, and correspondingly, the pulse width modulation unit generates a pulse width modulation signal after receiving the low-level PWM switch control signal, so that the switch control point outputs a low level.

Referring to fig. 3, since the driving operation of the device requiring voltage inversion requires that complementary modulation signals with a phase difference of 180 degrees be used as the signal source of the inversion driving, the present application specifically but not limited to provide a scheme for providing complementary modulation signals with a phase difference of 180 degrees, as follows: the PWM input signal input by the PWM signal unit 1 comprises a PWM1 signal and a PWM2 signal by adopting a phase shifting unit 11, the frequency of the PWM2 signal is half of the frequency of the PWM1 signal, the phase shifting unit 11 is connected between the input end of the PWM signal unit 1 and a switch control point, the phase shifting unit 11 is used for modulating the input PWM1 signal and the input PWM2 signal and outputting a PWM3A signal and a PWM4A signal with the phase difference of 180 degrees after modulation, and the dead time of the PWM3A signal and the PWM4A signal is the closing time of the PWM1 signal.

With continued reference to fig. 3, in various embodiments, the PWM1 signal and the PWM2 signal may be at different frequencies that may be adjusted by the user depending on the application, for example, the PWM1 signal may have a duty cycle of 95%, the PWM2 signal may have a duty cycle of 50%, the PWM3A and the PWM4A may have complementary waveforms that are 180 degrees out of phase with a dead time of 5%. Shown in the figure, PWM1 and PWM2 are PWM input signal waveforms, PWM3A and PWM4A are complementary waveforms with a phase shift of 180 degrees, PEAK and VREF are spike voltage signals and preset voltage signals, and PWM3B and PWM4B are PWM output signal waveforms after comparison and modulation.

In different embodiments, the phase shift unit 11 may be composed of different elements, and the present application provides a solution specifically but not limited to: the phase shift unit 11 includes a first waveform shaping element T1, a second waveform shaping element T2, a third waveform shaping element T3, a fourth waveform shaping element T4, a first two-input AND gate AND1, AND a second two-input AND gate AND2, AND specifically, the first waveform shaping element T1 is connected to an input terminal of the PWM1 signal, one input terminal of the first two-input AND gate AND1 is connected to an output terminal of the first waveform shaping element T1, the other input terminal thereof is input with the PWM2 signal, the second waveform shaping element T2 is connected to an input terminal of the PWM2 signal, one input terminal of the second two-input AND gate AND2 is connected to an output terminal of the first waveform shaping element T1, the other input terminal thereof is connected to an output terminal of the second waveform shaping element T2, the third waveform shaping element T3 is connected to an output terminal of the second two-input AND gate AND2 AND outputs the PWM3A signal, AND the fourth waveform shaping element T4 is connected to an output terminal of the first two-input AND gate AND1 AND outputs the PWM4A signal.

Specifically, in different embodiments, the waveform shaping element may be composed of different elements, but it is sufficient if the waveform shaping capability is provided, and the input waveform can be shaped into a square waveform, and the first waveform shaping element T1, the second waveform shaping element T2, the third waveform shaping element T3, and the fourth waveform shaping element T4 are schmitt triggers as examples. Schmitt triggers have the following characteristics: the output is high if the input voltage is higher than the forward threshold voltage; if the input voltage is lower than the negative threshold voltage, the output is low; when the input voltage is between the positive and negative threshold voltages, the output is unchanged, that is, the output is turned from the high level to the low level, or from the low level to the high level, the corresponding threshold voltages are different, and only when the input voltage is changed enough, the output is changed, and the hysteresis phenomenon exists. Therefore, the Schmitt trigger can be used as a waveform shaping element, and the hysteresis characteristic of the Schmitt trigger enables the anti-interference capability to be strong.

With continued reference to fig. 2, in different embodiments, the comparing unit 2 may be composed of different elements, but it is only required to acquire and compare the PEAK voltage signal PEAK with the preset voltage signal VREF, and output a comparison signal based on the comparison result, and the present application provides a specific but non-limiting scheme: the comparison unit 2 comprises a PEAK voltage branch 21, a preset voltage branch 22 and a comparator U1C PEAK voltage branch 21 for inputting a PEAK voltage signal PEAK, the preset voltage branch 22 for inputting a preset voltage signal VREF, the non-inverting input terminal of the comparator U1C is connected to the preset voltage branch 22, the inverting input terminal of the comparator U1C is connected to the PEAK voltage branch 21, a negative feedback resistor R4 is connected between the output terminal and the non-inverting input terminal of the comparator U1C, and the output terminal of the comparator U1C outputs a comparison signal. When the peak voltage is greater than the preset voltage, the output end of the comparator U1C outputs a comparison signal with a low level, and when the peak voltage is less than the preset voltage, the output end of the comparator U1C outputs a comparison signal with a high level.

With continued reference to fig. 2, in different embodiments, the pulse width modulation unit 4 may be composed of different elements, but any element that can output a pulse modulation signal to the switching control point based on the PWM switching control signal, so that the switching control point can control the pulse width of the PWM output signal, the present application provides a specific but non-limiting scheme: the pulse width modulation unit 4 comprises an NMOS switch tube Q1 and a first resistor R3, the grid electrode of the NMOS switch tube Q1 is connected with the output end of the logic unit 3, the source electrode of the NMOS switch tube Q1 is connected with the ground wire, the drain electrode of the NMOS switch tube Q1 is connected with a switch control point, the NMOS switch tube Q1 is used for generating a pulse width modulation signal, and the first resistor R3 is connected between the grid electrode and the source electrode of the NMOS switch tube Q1. The voltage at two ends of the first resistor R3 is equal to the voltage between the gate and the source of the NMOS switch tube Q1, and since the source of the NMOS switch tube Q1 is connected to the ground, when the PWM switch control signal output by the logic unit 3 is at a low level, the gate-source voltage of the NMOS switch tube Q1 is less than the turn-on voltage of the NMOS switch tube Q1, that is, vgs < Vt, and therefore, the NMOS switch tube Q1 is in a turn-off state, that is, id =0; correspondingly, when the PWM switching control signal output by the logic unit 3 is at a high level, the gate-source voltage of the NMOS switch Q1 is greater than the turn-on voltage of the NMOS switch Q1, i.e., vgs > Vt, and therefore, the NMOS switch Q1 is in a conducting state.

In view of the above solution, in different embodiments, the switch control point may control the pulse width of the PWM output signal in different manners, and the present application provides a solution specifically but not limited to: the switch control point comprises a PWM3A signal switch control point positioned on the PWM3A signal output branch and a PWM4A signal switch control point positioned on the PWM4A signal output branch, the pulse width modulation unit 4 further comprises a first diode D1 and a second diode D2, the input end of the first diode D1 is connected to the PWM3A signal switch control point, the output end of the first diode D1 is connected to the drain electrode of the NMOS switch tube Q1, the input end of the second diode D2 is connected to the PWM4A signal switch control point, and the output end of the second diode D2 is connected to the drain electrode of the NMOS switch tube Q1.

When the NMOS switch tube Q1 is turned on, both the PWM3A signal switch control point and the PWM4A signal switch control point can be connected to the ground through the NMOS switch tube Q1, and therefore, both the PWM3A signal output branch and the PWM4A signal output branch are in a low level state, and when the NMOS switch tube Q1 is turned off, both the PWM3A signal switch control point and the PWM4A signal switch control point cannot be connected to the ground through the NMOS switch tube Q1, and therefore, both the PWM3A signal output branch and the PWM4A signal output branch are in a high level state, and thus, the PWM output signal controlled by the pulse width modulation unit 4 can be output.

The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims (9)

1. A cycle-by-cycle peak control circuit, comprising:

a PWM signal unit (1) having one end for inputting a PWM input signal and the other end for outputting a PWM output signal;

the comparison unit (2) is used for acquiring and comparing the PEAK voltage signal PEAK with a preset voltage signal VREF, and outputting a comparison signal based on a comparison result;

the input end of the logic unit (3) is connected with the PWM signal unit (1) and the comparison unit (2), and the logic unit (3) is used for carrying out logic operation on a PWM input signal and a comparison signal and outputting a PWM switch control signal;

the input end of the pulse width modulation unit (4) is connected to the logic unit (3), a switch control point is formed between the input end of the PWM signal unit (1) and the output end of the PWM signal unit (1), the output end of the pulse width modulation unit (4) is connected to the switch control point, the pulse width modulation unit (4) outputs a pulse width modulation signal to the switch control point based on the PWM switch control signal, and the switch control point controls the pulse width of a PWM output signal output by the PWM signal output end based on the pulse width modulation signal.

2. The cycle-by-cycle peak control circuit according to claim 1, wherein the PWM signal unit (1) comprises a phase shift unit (11), the PWM input signal input by the PWM signal unit (1) comprises a PWM1 signal and a PWM2 signal, the frequency of the PWM2 signal is one half of the frequency of the PWM1 signal, the phase shift unit (11) is connected between the input end of the PWM signal unit (1) and the switch control point, the phase shift unit (11) is configured to modulate the input PWM1 signal and the input PWM2 signal and output a PWM3A signal and a PWM4A signal with a phase difference of 180 degrees after modulation, and the dead time of the PWM3A signal and the PWM4A signal is the off time of the PWM1 signal.

3. The cycle-by-cycle peak control circuit of claim 2, wherein the duty cycle of the PWM1 signal is 95%, the duty cycle of the PWM2 signal is 50%, the PWM3A and the PWM4A are out of phase by 180 degrees of complementary waveforms and the dead time is 5%.

4. A cycle-by-cycle peak control circuit according to claim 2, wherein the phase shift unit (11) comprises:

the first wave shaping element T1 is connected to the input end of the PWM1 signal;

a first two-input AND gate AND1, one input end of which is connected to the output end of the first waveform shaping element T1, AND the other input end of which inputs the PWM2 signal;

the second waveform shaping element T2 is connected to the input end of the PWM2 signal;

a second AND gate AND2 having one input terminal connected to the output terminal of said first wave shaping element T1 AND the other input terminal connected to the output terminal of said second wave shaping element T2;

the third waveform shaping element T3 is connected to the output end of the second input AND gate AND2 AND outputs the PWM3A signal;

AND a fourth waveform shaping element T4 connected to the output terminal of the first two-input AND gate AND1 AND outputting the PWM4A signal.

5. The cycle-by-cycle peak control circuit of claim 4, wherein the first, second, third and fourth waveform shaping elements T1, T2, T3 and T4 are Schmitt triggers.

6. A cycle-by-cycle peak control circuit according to claim 1, characterized in that the comparison unit (2) comprises:

a PEAK voltage branch (21) for inputting a PEAK voltage signal PEAK;

the preset voltage branch circuit (22) is used for inputting a preset voltage signal VREF;

the non-inverting input end of the comparator U1C is connected to the preset voltage branch (22), the inverting input end of the comparator U1C is connected to the peak voltage branch (21), a negative feedback resistor R4 is connected between the output end and the non-inverting input end of the comparator U1C, and the output end of the comparator U1C outputs a comparison signal.

7. The cycle-by-cycle peak control circuit according to claim 6, wherein the predetermined voltage branch (22) comprises a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series between a power supply and a ground, a predetermined voltage point is formed between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the predetermined voltage point is connected to a non-inverting input terminal of the comparator U1C for inputting the predetermined voltage signal VREF.

8. A cycle-by-cycle peak control circuit according to claim 2, characterized in that the pulse width modulation unit (4) comprises:

the grid electrode of the NMOS switch tube Q1 is connected to the output end of the logic unit (3), the source electrode of the NMOS switch tube Q1 is connected with the ground wire, the drain electrode of the NMOS switch tube Q1 is connected to the switch control point, and the NMOS switch tube Q1 is used for generating a pulse width modulation signal;

and the first resistor R3, wherein the first resistor R3 is connected between the grid electrode and the source electrode of the NMOS switch tube Q1.

9. The cycle-by-cycle peak control circuit of claim 8,

the switch control points comprise a PWM3A signal switch control point on the PWM3A signal output branch and a PWM4A signal switch control point on the PWM4A signal output branch,

the pulse width modulation unit (4) further comprises:

the input end of the first diode D1 is connected to the PWM3A signal switch control point, and the output end of the first diode D1 is connected to the drain electrode of the NMOS switch tube Q1;

and the input end of the second diode D2 is connected to the PWM4A signal switch control point, and the output end of the second diode D2 is connected to the drain electrode of the NMOS switch tube Q1.

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