CN113611669A - 制作半导体元件的方法 - Google Patents

制作半导体元件的方法 Download PDF

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CN113611669A
CN113611669A CN202010883406.4A CN202010883406A CN113611669A CN 113611669 A CN113611669 A CN 113611669A CN 202010883406 A CN202010883406 A CN 202010883406A CN 113611669 A CN113611669 A CN 113611669A
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stress
layer
nmos
pmos
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胡涛
施晓东
欧阳锦坚
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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Priority to US17/026,319 priority patent/US20220068723A1/en
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Abstract

本发明公开一种制作半导体元件的方法。提供半导体基板，具有NMOS区域、PMOS区域和非硅化金属区域。分别于NMOS区域和PMOS区域内形成NMOS晶体管和PMOS晶体管。形成应力记忆层，覆盖NMOS区域、PMOS区域和非硅化金属区域。将应力记忆层从PMOS区域移除。将应力从应力记忆层移转至NMOS晶体管的N通道中。将应力记忆层从NMOS区域移除，但留下非硅化金属区域内的应力记忆层。进行自对准硅化金属制作工艺，于NMOS区域和PMOS区域形成硅化金属层。

Description

制作半导体元件的方法
技术领域
本发明涉及半导体制作工艺技术领域，特别是涉及一种制作半导体元件的方法。
背景技术
已知，应力记忆技术(SMT，Stress Memorization Technology)通常是在半导体制作工艺中用于源极/漏极(S/D)离子注入步骤后进行，以诱发应力于金属氧化物半导体场效晶体管(MOSFET)的通道区域。
在传统的SMT制作工艺中，通常采用沉积应力层及激光退火，以诱发应力于基底中，即通过激光退火使位于应力层下的多晶硅栅极再结晶，从而改善N通道金属氧化物半导体场效晶体管(NMOSFET，以下简称NMOS)的电性。上述的应力层在后续的自对准硅化金属(self-aligned silicidation)制作工艺前会被移除。
在自对准硅化金属制作工艺过程中，需要另外沉积一自对准硅化金属阻挡(salicide block，SAB)层，例如，氧化硅层和氮化硅层，并进行曝光和显影制作工艺，图案化自对准硅化金属阻挡层，以遮盖住不需要形成硅化金属层的区域(非硅化金属区域)。然而，上述SMT制作工艺和自对准硅化金属制作工艺需要多次的沉积和蚀刻，步骤较为繁复。
发明内容
本发明的主要目的在于提供一种改良的半导体制作工艺，可以简化制作工艺步骤，以解决现有技术的不足与缺点。
本发明一方面提供了一种制作半导体元件的方法，包含：提供一半导体基板，其上具有一NMOS区域、一PMOS区域和一非硅化金属区域；分别于所述NMOS区域和所述PMOS区域内形成一NMOS晶体管和一PMOS晶体管；形成一应力记忆层，覆盖所述NMOS区域、所述PMOS区域和所述非硅化金属区域；将所述应力记忆层从所述PMOS区域移除；将一应力从所述应力记忆层移转至所述NMOS晶体管的一N通道中；将所述应力记忆层从所述NMOS区域移除，但留下所述非硅化金属区域内的所述应力记忆层；以及进行一自对准硅化金属制作工艺，于所述NMOS区域和所述PMOS区域形成一硅化金属层。
依据本发明实施例，其中留在所述非硅化金属区域内的所述应力记忆层在所述自对准硅化金属制作工艺用作一自对准硅化金属阻挡层。
依据本发明实施例，其中所述应力记忆层包含一氧化硅层和一氮化硅层。
依据本发明实施例，其中所述应力包含一伸张应力。
依据本发明实施例，其中将所述应力从所述应力记忆层移转包含进行一激光尖峰退火制作工艺。
依据本发明实施例，其中另包含：进行一源极/漏极退火制作工艺将所述NMOS晶体管和所述PMOS晶体管的一源极/漏极区域内的掺质活化。
依据本发明实施例，其中所述源极/漏极退火制作工艺包含一快速热退火制作工艺。
依据本发明实施例，其中在进行所述自对准硅化金属制作工艺之前，另包含：将所述NMOS晶体管和所述PMOS晶体管的间隙壁进行厚度缩减。
本发明另一方面提供了一种制作半导体元件的方法，包含：提供一半导体基板，其上具有一NMOS区域、一PMOS区域和一非硅化金属区域；分别于所述NMOS区域和所述PMOS区域内形成一NMOS晶体管和一PMOS晶体管；其中所述NMOS晶体管包含在所述半导体基板中的N型源极/漏极掺杂区、介于所述N型源极/漏极掺杂区之间的一N型通道、位于所述N型通道上的一NMOS栅，和位于所述NMOS栅的侧壁上的第一间隙壁，其中所述PMOS晶体管包含在所述半导体基板中的P型源极/漏极掺杂区、介于所述P型源极/漏极掺杂区之间的一P型通道、位于所述P型通道上的一PMOS栅，和位于所述PMOS栅的侧壁上的第二间隙壁；形成一应力记忆层，覆盖所述NMOS区域、所述PMOS区域和所述非硅化金属区域，其中所述应力记忆层包含一氧化硅层和一氮化硅层；将所述应力记忆层的所述氮化硅层从所述PMOS区域移除；将一应力从所述应力记忆层移转至所述NMOS晶体管的所述N通道中；将所述应力记忆层的所述氮化硅层从所述NMOS区域移除，但留下所述非硅化金属区域内的所述应力记忆层；将所述氧化硅层从所述NMOS区域和所述PMOS区域移除，显露出所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区；以及进行一自对准硅化金属制作工艺，在所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区上形成一硅化金属层。
依据本发明实施例，其中留在所述非硅化金属区域内的所述应力记忆层在所述自对准硅化金属制作工艺用作一自对准硅化金属阻挡层。
依据本发明实施例，其中所述应力包含一伸张应力。
依据本发明实施例，其中将所述应力从所述应力记忆层移转包含进行一激光尖峰退火制作工艺。
依据本发明实施例，其中另包含：
进行一源极/漏极退火制作工艺将所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区内的掺质活化。
依据本发明实施例，其中所述源极/漏极退火制作工艺包含一快速热退火制作工艺。
依据本发明实施例，其中在进行所述自对准硅化金属制作工艺之前，另包含：将所述NMOS晶体管的所述第一间隙壁和所述PMOS晶体管的所述第二间隙壁进行厚度缩减。
附图说明
图1至图6为本发明一实施例所绘示的制作半导体元件的方法的剖面示意图。
主要元件符号说明
10 半导体基板
101 NMOS区域
102 PMOS区域
103 非硅化金属区域
20 NMOS晶体管
201 NMOS栅
202 N型源极/漏极掺杂区
202a N型轻掺杂漏极区域
203 N型源极/漏极掺杂区
203a N型轻掺杂漏极区域
204 栅极介电层
205 N型通道
206 第一间隙壁
30 PMOS晶体管
301 PMOS栅
302 P型源极/漏极掺杂区
302a P型轻掺杂漏极区域
303 P型源极/漏极掺杂区
303a P型轻掺杂漏极区域
304 栅极介电层
305 P型通道
306 第二间隙壁
40 半导体结构
401 电极
406 第三间隙壁
50 应力记忆(SMT)层
52 氧化硅层
54 氮化硅层
60 光致抗蚀剂图案
62 蚀刻制作工艺
66 激光尖峰退火制作工艺
68 应力
70 光致抗蚀剂图案
72 蚀刻制作工艺
700 硅化金属层
701 硅化金属层
702 硅化金属层
703 硅化金属层
800 硅化金属层
801 硅化金属层
802 硅化金属层
803 硅化金属层
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技艺人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图6，其为依据本发明一实施例所绘示的制作半导体元件的方法的剖面示意图。如图1所示，首先提供一半导体基板10，例如，硅基底，但不限于此。依据本发明实施例，半导体基板10可以包含一鳍状结构，但不限于此。在半导体基板10上具有一NMOS区域101、一PMOS区域102和一非硅化金属(non-silicide)区域103。接着，于NMOS区域101和PMOS区域102内分别形成一NMOS晶体管20和一PMOS晶体管30。依据本发明实施例，NMOS晶体管20和PMOS晶体管30可以是鳍式场效晶体管(FinFET)，但不限于此。
依据本发明实施例，NMOS晶体管20可以包含在半导体基板10中的N型源极/漏极掺杂区202和203、介于N型源极/漏极掺杂区202和203之间的一N型通道205、位于N型通道205上的一NMOS栅201，和位于NMOS栅201的侧壁上的第一间隙壁206，例如，氮化硅间隙壁。此外，在NMOS栅201和N型通道205之间可以具有一栅极介电层204，例如，二氧化硅层。
依据本发明实施例，N型源极/漏极掺杂区202可以包含一N型轻掺杂漏极(NLDD)区域202a，N型源极/漏极掺杂区203可以包含一N型轻掺杂漏极(NLDD)区域203a，而N型通道205位于NLDD区域202a和NLDD区域203a之间。
依据本发明实施例，PMOS晶体管30可以包含在半导体基板10中的P型源极/漏极掺杂区302和303、介于P型源极/漏极掺杂区302和303之间的一P型通道305、位于P型通道305上的一PMOS栅301，和位于PMOS栅301的侧壁上的第二间隙壁306，例如，氮化硅间隙壁。此外，在PMOS栅301和P型通道305之间可以具有一栅极介电层304，例如，二氧化硅层。
依据本发明实施例，P型源极/漏极掺杂区302可以包含一P型轻掺杂漏极(PLDD)区域302a，P型源极/漏极掺杂区303可以包含一P型轻掺杂漏极(PLDD)区域303a，而P型通道305位于PLDD区域302a和PLDD区域303a之间。
依据本发明实施例，在非硅化金属区域103可以形成至少一半导体结构40，例如，电阻、电容或二极管等，但不限于此。依据本发明实施例，例如，半导体结构40可以包含一电极401以及设置在电极401侧壁上的第三间隙壁406。
接着，形成一应力记忆(stress memorization technique，SMT)层50，覆盖NMOS区域101、PMOS区域102和非硅化金属区域103。依据本发明实施例，SMT层50顺形的覆盖在NMOS晶体管20、PMOS晶体管30和半导体结构40上。依据本发明实施例，SMT层50可以包含一氧化硅层52和一氮化硅层54。其中，氧化硅层52可以作为一缓冲层，氮化硅层54可以具有一伸张应力(tensile stress)。
如图2所示，接着将SMT层50从PMOS区域102移除，更明确的说，是将SMT层50的氮化硅层54从PMOS区域102移除。具体作法是在半导体基板10上以曝光和显影等制作工艺形成一光致抗蚀剂图案60，其中光致抗蚀剂图案60覆盖NMOS区域101和非硅化金属区域103，显露出PMOS区域102。接着，进行一蚀刻制作工艺62，将显露出来的SMT层50的氮化硅层54从PMOS区域102移除。随后，将剩下的光致抗蚀剂图案60去除。依据本发明实施例，接着可以进行一源极/漏极退火(source/drainanneal)制作工艺，将N型源极/漏极掺杂区202、203和P型源极/漏极掺杂区302、303内的掺质活化。依据本发明实施例，其中源极/漏极退火制作工艺包含一快速热退火(rapid thermal anneal，RTA)制作工艺。
如图3所示，接着进行例如一激光尖峰退火(laser spike anneal)制作工艺66，将一应力68从SMT层50移转至NMOS晶体管20的N型通道205中。依据本发明实施例，其中应力68包含一伸张应力。
如图4所示，接着将SMT层50从NMOS区域101移除，但留下非硅化金属区域102内的SMT层50。具体作法是在半导体基板10上以曝光和显影等制作工艺形成一光致抗蚀剂图案70，其中光致抗蚀剂图案70覆盖PMOS区域102和非硅化金属区域103，显露出NMOS区域101。接着进行一蚀刻制作工艺72，将显露出来的SMT层50的所述氮化硅层54从NMOS区域101移除。随后，将剩下的光致抗蚀剂图案70去除。
如图5所示，接着将氧化硅层52从NMOS区域101和PMOS区域102移除，显露出N型源极/漏极掺杂区202、203和P型源极/漏极掺杂区302、303。依据本发明实施例，此时，非硅化金属区域103仍然被SMT层50覆盖住。
接着，可以对NMOS晶体管20的第一间隙壁206和PMOS晶体管30的第二间隙壁306进行一厚度缩减制作工艺，例如，干蚀刻或湿蚀刻。此时，由于非硅化金属区域103仍然被SMT层50覆盖住，因此，半导体结构40的第三间隙壁406的厚度不会改变。换言之，在进行上述厚度缩减制作工艺后，半导体结构40的第三间隙壁406的厚度可以大于第一间隙壁206和第二间隙壁306的厚度。
如图6所示，进行一自对准硅化金属制作工艺，在NMOS区域101和PMOS区域102形成一硅化金属层700和800，包括，在N型源极/漏极掺杂区202和203上分别形成硅化金属层702和703和于P型源极/漏极掺杂区302和303上分别形成硅化金属层802和803，并且在NMOS栅201上和PMOS栅301上分别形成硅化金属层701和801。具体作法是先全面的沉积一金属层(图未示)，再加热使金属层与显露出来的硅表面反应成硅化金属层，最后移除未反应的剩余金属层。
依据本发明实施例，硅化金属层700和800可以包括硅化镍(NiSi)或硅化钴(CoSi)等，但不限于此。依据本发明实施例，在自对准硅化金属制作工艺中，留在非硅化金属区域103内的SMT层50用作一自对准硅化金属阻挡(salicide blocking，SAB)层。
本发明的优点在于将SMT制作工艺中的SMT层50进一步定义成位于非硅化金属区域103内的SAB层，使得在后续的自对准硅化金属制作工艺中，非硅化金属区域103可以被遮盖住，不会形成硅化金属层。如此一来，可以不需要另外沉积自对准硅化金属阻挡层，也节省了蚀刻、曝光和显影等步骤，使得制作工艺步骤可以简化。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种制作半导体元件的方法，包含：
提供半导体基板，其上具有NMOS区域、PMOS区域和非硅化金属区域；
分别于所述NMOS区域和所述PMOS区域内形成NMOS晶体管和PMOS晶体管；
形成应力记忆层，覆盖所述NMOS区域、所述PMOS区域和所述非硅化金属区域；
将所述应力记忆层从所述PMOS区域移除；
将应力从所述应力记忆层移转至所述NMOS晶体管的N型通道中；
将所述应力记忆层从所述NMOS区域移除，但留下所述非硅化金属区域内的所述应力记忆层；以及
进行自对准硅化金属制作工艺，于所述NMOS区域和所述PMOS区域形成硅化金属层。
2.如权利要求1所述的方法，其中留在所述非硅化金属区域内的所述应力记忆层在所述自对准硅化金属制作工艺用作自对准硅化金属阻挡层。
3.如权利要求1所述的方法，其中所述应力记忆层包含氧化硅层和一氮化硅层。
4.如权利要求1所述的方法，其中所述应力包含伸张应力。
5.如权利要求1所述的方法，其中将所述应力从所述应力记忆层移转包含进行激光尖峰退火制作工艺。
6.如权利要求1所述的方法，其中另包含：
进行源极/漏极退火制作工艺，将所述NMOS晶体管和所述PMOS晶体管的源极/漏极区域内的掺质活化。
7.如权利要求6所述的方法，其中所述源极/漏极退火制作工艺包含快速热退火制作工艺。
8.如权利要求1所述的方法，其中在进行所述自对准硅化金属制作工艺之前，另包含：
将所述NMOS晶体管和所述PMOS晶体管的间隙壁进行厚度缩减。
9.一种制作半导体元件的方法，包含：
提供半导体基板，其上具有NMOS区域、PMOS区域和非硅化金属区域；
分别于所述NMOS区域和所述PMOS区域内形成NMOS晶体管和PMOS晶体管；其中所述NMOS晶体管包含在所述半导体基板中的N型源极/漏极掺杂区、介于所述N型源极/漏极掺杂区之间的N型通道、位于所述N型通道上的NMOS栅，和位于所述NMOS栅的侧壁上的第一间隙壁，其中所述PMOS晶体管包含在所述半导体基板中的P型源极/漏极掺杂区、介于所述P型源极/漏极掺杂区之间的P型通道、位于所述P型通道上的PMOS栅，和位于所述PMOS栅的侧壁上的第二间隙壁；
形成应力记忆层，覆盖所述NMOS区域、所述PMOS区域和所述非硅化金属区域，其中所述应力记忆层包含氧化硅层和氮化硅层；
将所述应力记忆层的所述氮化硅层从所述PMOS区域移除；
将应力从所述应力记忆层移转至所述NMOS晶体管的所述N型通道中；
将所述应力记忆层的所述氮化硅层从所述NMOS区域移除，但留下所述非硅化金属区域内的所述应力记忆层；
将所述氧化硅层从所述NMOS区域和所述PMOS区域移除，显露出所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区；以及
进行自对准硅化金属制作工艺，在所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区上形成一硅化金属层。
10.如权利要求9所述的方法，其中留在所述非硅化金属区域内的所述应力记忆层在所述自对准硅化金属制作工艺用作自对准硅化金属阻挡层。
11.如权利要求9所述的方法，其中所述应力包含伸张应力。
12.如权利要求9所述的方法，其中将所述应力从所述应力记忆层移转包含进行激光尖峰退火制作工艺。
13.如权利要求9所述的方法，其中另包含：
进行源极/漏极退火制作工艺，将所述N型源极/漏极掺杂区和所述P型源极/漏极掺杂区内的掺质活化。
14.如权利要求13所述的方法，其中所述源极/漏极退火制作工艺包含快速热退火制作工艺。
15.如权利要求9所述的方法，其中在进行所述自对准硅化金属制作工艺之前，另包含：
将所述NMOS晶体管的所述第一间隙壁和所述PMOS晶体管的所述第二间隙壁进行厚度缩减。
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