CN113608934A - Dual-redundancy server based on Feiteng processor - Google Patents

Dual-redundancy server based on Feiteng processor Download PDF

Info

Publication number
CN113608934A
CN113608934A CN202110791313.3A CN202110791313A CN113608934A CN 113608934 A CN113608934 A CN 113608934A CN 202110791313 A CN202110791313 A CN 202110791313A CN 113608934 A CN113608934 A CN 113608934A
Authority
CN
China
Prior art keywords
processor
pcie
switch
controller
server based
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110791313.3A
Other languages
Chinese (zh)
Inventor
陈聪葱
方明
李贺
章阳
王佳
姬叶华
邹志强
张佩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 32 Research Institute
Original Assignee
CETC 32 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 32 Research Institute filed Critical CETC 32 Research Institute
Priority to CN202110791313.3A priority Critical patent/CN113608934A/en
Publication of CN113608934A publication Critical patent/CN113608934A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Hardware Redundancy (AREA)

Abstract

The invention provides a dual-redundancy server based on a Feiteng processor, which comprises: the system comprises a first FT2000+ processor, a second FT2000+ processor, an FPGA, a SWITCH, a PCIE selector, an SAS controller, a USB controller, an Ethernet controller and a BMC controller; the first FT2000+ processor and the second FT2000+ processor are connected with a PCIE selector and an FPGA through PCIE interfaces, the FPGA is connected with the PCIE selector, the PCIE selector is connected with an SWITCH, the FPGA is connected with the SWITCH through GPIO signals, the first FT2000+ processor is connected with an uplink port of the SWITCH through the PCIE selector, the second FT2000+ processor is connected with an NT port of the SWITCH, and the SAS controller, the USB controller, the Ethernet controller and the BMC controller are connected with the SWITCH through the PCIE interfaces. The invention adopts a dual-processor architecture, realizes the functions of safe fault transfer and load sharing of the server, increases the reliability of the system, and combines manual switching and automatic switching by the dual-processor.

Description

Dual-redundancy server based on Feiteng processor
Technical Field
The invention relates to the field of computers, in particular to a double redundancy server based on a Feiteng processor.
Background
In the information security era, the universal server based on the domestic processor avoids risks and hidden dangers in the aspects of technology and maintenance, and the redundant processor architecture can realize the functions of safe fault transfer and load sharing of the server. Therefore, when a fault occurs, the standby equipment can still maintain normal operation, and the reliability of the system is increased.
Chinese patent publication No. CN210954893U discloses a two-way server motherboard based on a soar processor, which includes: the two Feiteng processors are interconnected through a Serdes interface, are respectively connected with a FLASH memory chip with an SPIO interface and a plurality of DDR4 memory slots, and are both connected with a USB interface through a USB interface chip; the system comprises PCIE expansion chips, wherein a group of X16 PCIE interfaces output by one Feiteng processor are connected with an input port of the PCIE expansion chip, and an output port of the PCIE expansion chip is connected with more than one SATA interface chip, more than one network chip and a management chip; and the plurality of PCIE slots, wherein one of the PCIE slots is connected with a corresponding interface in the Feiteng processor, and the rest PCIE slots are connected with a corresponding interface in the other Feiteng processor. However, the dual-way server motherboard in this patent document does not support the fail-over mechanism, and when one processor fails, switching cannot be implemented.
Disclosure of Invention
In view of the defects in the prior art, the invention aims to provide a dual-redundancy server based on a Feiteng processor.
The invention provides a double-redundancy server based on a Feiteng processor, which comprises: the system comprises a first FT2000+ processor, a second FT2000+ processor, an FPGA, a SWITCH, a PCIE selector, an SAS controller, a USB controller, an Ethernet controller and a BMC controller;
the first FT2000+ processor and the second FT2000+ processor are connected with a PCIE selector through PCIE interfaces, the first FT2000+ processor and the second FT2000+ processor are connected with an FPGA through PCIE interfaces, the first FT2000+ processor and the second FT2000+ processor share memory and synchronize data in the FPGA, the FPGA is connected with the PCIE selectors, the PCIE selectors are connected with a SWITCH, the FPGA is connected with the SWITCH through GPIO signals, the first FT2000+ processor is connected with an uplink port of the SWITCH through the PCIE selectors, the second FT2000+ processor is connected with an NT port of the SWITCH, and the SAS controller, the USB controller, the Ethernet controller and the BMC controller are connected with the SWITCH through PCIE interfaces.
Preferably, the first FT2000+ processor and the second FT2000+ processor are embedded with an eight-channel DDR4 controller, and each processor is extended with eight ECC-equipped RDIMM memory slots.
Preferably, the PCIE selector is formed by combining a PCIE sending one-out selector PI3EQX16812 of four channels and a PCIE receiving one-out selector PI3EQX16821 of four channels.
Preferably, the PCIE selector supports a serial rate of 16Gbps at most, and is compatible with the PCIE4.0 standard.
Preferably, the SWITCH uses PEX8780, and the PCIE bridge of the SWITCH supports 80lanes and supports fail-over mode under multiple main processors.
Preferably, the SWITCH extends one PCIE slot of X16, two PCIE slots of X8, and one XMC daughter card of X8 through the PCIE interface.
Preferably, three RAMs are opened inside the FPGA, namely Section A, Section B and Section C, the first FT2000+ processor can only perform write operation on Section A, and the first FT2000+ processor can perform read operation on the three RAMs; the second FT2000+ can only perform write operation on Section B, and the second FT2000+ can perform read operation on three RAMs; the IO mounted under the SWITCH can only perform write operation on the Section C, and the IO mounted under the SWITCH can perform read operation on the three RAMs.
Preferably, the three RAM capacities opened in the FPGA are all 16 KB.
Preferably, the SAS controller is 88SE1495, and the SAS controller extends two miniHD-SAS interfaces for connecting storage hard disks.
Preferably, the ethernet controller includes a gigabit ethernet controller i350 and a gigabit ethernet controller 82599, the i350 extends four gigabit ethernet interfaces, and the i350 external interface is in the form of RJ 45; the 82599 extends two gigabit ethernet interfaces, and the external interface of 82599 is in the form of SFP and optical port.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts a dual-processor architecture, realizes the functions of safe fault transfer and load sharing of the server and increases the reliability of the system.
2. The safe dual-processor of the invention supports the combination of manual switching and automatic switching: the PCIE switching method has the advantages that manual switching of the active and standby processors can be achieved through the PCIE switch, automatic switching in a fail-over mode under multiple main processors is achieved, and switching time reaches millisecond level.
3. According to the invention, the memory sharing of the main processor, the standby processor and the peripheral IO is realized in the FPGA through the PCIE, the circuit integration level of the programmable logic device is high, the memory capacity can be enlarged or reduced according to the requirement, and the programmable logic device is more flexible.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a system diagram of a dual redundant server based on Feiteng processors according to an embodiment of the present application;
fig. 2 is a schematic diagram of an internal memory sharing design of an FPGA in the embodiment of the present application.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The dual-redundancy server based on the Feiteng processor mainly comprises a first FT2000+ processor, a second FT2000+ processor, an FPGA, a SWITCH, a PCIE selector, an SAS controller, a USB controller, an Ethernet controller and a BMC controller.
The first FT2000+ processor and the second FT2000+ processor are embedded with an eight-channel DDR4 controller, and each processor is provided with eight ECC-equipped RDIMM memory slots in an expansion mode. The PCIE selector is realized by combining a four-channel PCIE sending alternative selector PI3EQX16812 and a four-channel PCIE receiving alternative selector PI3EQX16821, the PCIE selector supports a serial rate of 16Gbps at most and is completely compatible with a PCIE4.0 standard. The FPGA realizes the switch control of the PCIE selector, and the manual switching of the active and standby processors can be realized through the PCIE selector. The SWITCH adopts PEX8780, the PCIE bridge supports 80lanes and supports fail-over mode under multiple main processors. In the invention, the first FT2000+ processor is connected to the uplink port of the SWITCH chip through the PCIE selector, the width is PCIE X4, the second FT2000+ processor is connected to the NT port of the SWITCH chip, and the width is PCIE X4, so that the dual-processor becomes a mutual standby system.
Under the condition that the two processors normally operate, the first FT2000+ processor is used as a system main processor by default, and in the operation process of the system, if the first FT2000+ processor fails, the SWITCH chip disables the connection between the first FT2000+ processor and the downlink port, sends an interrupt signal through the doorbell register and informs the second FT2000+ processor to take over all the downlink ports through the NT port instead of the first FT2000+ processor, so that the automatic switching of the two processors is realized, and the safety and the reliability of the system are improved.
The FPGA adopts XC7VX690TFFG176 model, and is respectively in physical connection communication with the processor 1 and the processor 2 through PCIE signals and in physical connection communication with the SWITCH through GPIO signals. The dual processors implement memory sharing and data synchronization in the FPGA, and the specific implementation method is shown in fig. 2. Three RAMs with the capacity of 16KB are developed inside the FPGA, namely Section A, Section B and Section ion C, and the IOs mounted under the processor 1, the processor 2 and the SWITCH can only write into the respective specific RAMs, but can read from all the three RAMs. Due to the adoption of the mode of sharing the memory data, the data loss in the operation process can not be caused when any processor fails to send the data.
The SWITCH chip PEX8780 is connected with the SAS controller 88SE1495 through a PCIE interface to expand 2 miniHD-SAS interfaces for connecting storage hard disks; 4 gigabit Ethernet interfaces are expanded through i350, and the external interface is in the form of RJ 45; 2 gigabit Ethernet interfaces are expanded by 82599, and the external interface is in the form of SFP + optical interface. The PEX8780 is provided with 4 paths of USB interfaces led out through a PCIE-to-USB chip uPD720201, wherein one path of USB2.0 is connected with the BMC, and the other three paths of USB3.0 are connected to the USB interfaces. The PEX8780 leads out a management network interface through a BMC controller AST2500 management chip for management, and outputs as a graphic image of the system through a VGA display module of the AST 2500. The PEX8780 extends one path of X16 and two paths of X8 PCIE slots through PCIE interfaces, and extends one path of X8 XMC daughter card.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. A dual redundant server based on a FT processor, comprising: the system comprises a first FT2000+ processor, a second FT2000+ processor, an FPGA, a SWITCH, a PCIE selector, an SAS controller, a USB controller, an Ethernet controller and a BMC controller;
the first FT2000+ processor and the second FT2000+ processor are connected with a PCIE selector through PCIE interfaces, the first FT2000+ processor and the second FT2000+ processor are connected with an FPGA through PCIE interfaces, the first FT2000+ processor and the second FT2000+ processor share memory and synchronize data in the FPGA, the FPGA is connected with the PCIE selectors, the PCIE selectors are connected with a SWITCH, the FPGA is connected with the SWITCH through GPIO signals, the first FT2000+ processor is connected with an uplink port of the SWITCH through the PCIE selectors, the second FT2000+ processor is connected with an NT port of the SWITCH, and the SAS controller, the USB controller, the Ethernet controller and the BMC controller are connected with the SWITCH through PCIE interfaces.
2. The dual redundant server based on a FT processor of claim 1, wherein: the first FT2000+ processor and the second FT2000+ processor are embedded with eight-channel DDR4 controllers, and each processor is extended with eight ECC-equipped RDIMM memory slots.
3. The dual redundant server based on a FT processor of claim 1, wherein: the PCIE selector is formed by combining a PCIE sending one-out-of-four selector PI3EQX16812 and a PCIE receiving one-out-of-four selector PI3EQX 16821.
4. The dual redundant server based on a Feiteng processor of claim 3, wherein: the PCIE selector supports the serial rate of 16Gbps at most and is compatible with the PCIE4.0 standard.
5. The dual redundant server based on a FT processor of claim 1, wherein: the SWITCH adopts PEX8780, a PCIE bridge of the SWITCH supports 80lanes, and a fail-over mode under multiple main processors is supported.
6. The dual redundant server based on a Feiteng processor of claim 5, wherein: the SWITCH extends one path of PCIE slot of X16, two paths of PCIE slots of X8 and one path of XMC daughter card of X8 through the PCIE interface.
7. The dual redundant server based on a FT processor of claim 1, wherein: three RAMs are opened inside the FPGA, namely Section A, Section B and Section C, the first FT2000+ processor can only perform write operation on the Section A, and the first FT2000+ processor can perform read operation on the three RAMs; the second FT2000+ can only perform write operation on Section B, and the second FT2000+ can perform read operation on three RAMs; the IO mounted under the SWITCH can only perform write operation on the Section C, and the IO mounted under the SWITCH can perform read operation on the three RAMs.
8. The dual redundant server based on a FT processor of claim 7, wherein: the capacity of three RAMs opened in the FPGA is 16 KB.
9. The dual redundant server based on a FT processor of claim 1, wherein: the SAS controller is 88SE1495, and the SAS controller expands two miniHD-SAS interfaces and is used for connecting the storage hard disk.
10. The dual redundant server based on a FT processor of claim 1, wherein: the Ethernet controller comprises a gigabit Ethernet controller i350 and a gigabit Ethernet controller 82599, wherein the i350 extends four gigabit Ethernet interfaces, and the i350 external interface is in the form of RJ 45; the 82599 extends two gigabit ethernet interfaces, and the external interface of 82599 is in the form of SFP and optical port.
CN202110791313.3A 2021-07-13 2021-07-13 Dual-redundancy server based on Feiteng processor Pending CN113608934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110791313.3A CN113608934A (en) 2021-07-13 2021-07-13 Dual-redundancy server based on Feiteng processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110791313.3A CN113608934A (en) 2021-07-13 2021-07-13 Dual-redundancy server based on Feiteng processor

Publications (1)

Publication Number Publication Date
CN113608934A true CN113608934A (en) 2021-11-05

Family

ID=78304595

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110791313.3A Pending CN113608934A (en) 2021-07-13 2021-07-13 Dual-redundancy server based on Feiteng processor

Country Status (1)

Country Link
CN (1) CN113608934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023208135A1 (en) * 2022-04-29 2023-11-02 苏州元脑智能科技有限公司 Server and server management system therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023208135A1 (en) * 2022-04-29 2023-11-02 苏州元脑智能科技有限公司 Server and server management system therefor

Similar Documents

Publication Publication Date Title
US6131169A (en) Reliability of crossbar switches in an information processing system
US11967364B2 (en) Variable width memory module supporting enhanced error detection and correction
US7519854B2 (en) Internal failover path for SAS disk drive enclosure
US20170300445A1 (en) Storage array with multi-configuration infrastructure
KR101592374B1 (en) Double data rate controller having shared address and separate data error correction unit
US20120260024A1 (en) Memory buffer with one or more auxiliary interfaces
US10572426B2 (en) System-level redundancy in PCI express equipment
US11907152B2 (en) Reconfigurable server and server rack with same
WO2021254368A1 (en) Memory module, computer, and server
CN112000501A (en) Management system for multi-node partition server to access I2C equipment
CN107220196A (en) A kind of built-in high-end storage card for supporting Tri Mode
US11869626B2 (en) Internal and external data transfer for stacked memory dies
CN213365380U (en) Server mainboard and server
CN110908475A (en) Shenwei 1621CPU ICH-free 2 suite server mainboard
CN113608934A (en) Dual-redundancy server based on Feiteng processor
CN112948316A (en) AI edge computing all-in-one machine framework based on network interconnection
CN116501678A (en) Topological board card and on-board system
CN201444642U (en) Data transmission link redundancy switching device
CN212723997U (en) Device for realizing multi-control sharing of full flash memory array
CN217157283U (en) Double-circuit server self-adaptive circuit and electronic equipment
CN214846518U (en) Storage blade and blade server
CN216527166U (en) Large-capacity storage system
US11983443B2 (en) Multi-access memory modules
CN113867648B (en) Server storage subsystem and control method thereof
CN116841949A (en) Four-way server mainboard and server based on domestic processor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination