CN201444642U - Data transmission link redundancy switching device - Google Patents
Data transmission link redundancy switching device Download PDFInfo
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- CN201444642U CN201444642U CN2009200272392U CN200920027239U CN201444642U CN 201444642 U CN201444642 U CN 201444642U CN 2009200272392 U CN2009200272392 U CN 2009200272392U CN 200920027239 U CN200920027239 U CN 200920027239U CN 201444642 U CN201444642 U CN 201444642U
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 abstract description 4
- 238000003491 array Methods 0.000 abstract 2
- 238000013515 script Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Abstract
The utility model discloses a data transmission link redundancy switching device, which belongs to a data transmission device and comprises a PC, disk arrays and IOP platforms, wherein the IOP platforms are arranged for redundancy, each IOP platform comprises an IOP mainboard, a DDR memory, a gigabit network, a SATA controller, an XRS10L140, a FLASH, a CPLD and an NVSRAM, wherein the PC is connected with the IOP mainboards of the two IOP platforms respectively via the gigabit networks of the two IOP platforms, and the IOP mainboards of the two IOP platforms are respectively connected with the disk arrays via respective SATA controllers and then via data lines. Compared with the prior art, the data transmission link redundancy switching device has a simple and reliable method, can make one line successfully replace the other data transmission line to transmit data when the other data transmission line fails, and ensures the stability of data transmission.
Description
Technical field
The utility model relates to a kind of apparatus for transmitting data, the redundant device for switching of specifically a kind of transmission data link.
Background technology
IOP I/O processor (I/O Processor) is the Direction Center of NetRAID controller, realizes comprising command process, and the transfer of data of PCI and SCSI bus, the processing of RAID, disc driver is rebuild, functions such as the management of high-speed cache and wrong recovery.
The utility model content
Technical assignment of the present utility model is at above weak point, provide a kind of simple, reliable, can guarantee the redundant device for switching of the stable a kind of transmission data link of transfer of data.
The technical scheme that its technical problem that solves the utility model adopts is: comprise PC, disk array and IOP platform, PC is connected with the IOP platform, and the IOP platform is connected with disk array by data wire; The IOP platform is redundant the setting, and each IOP platform includes IOP mainboard, DDR internal memory, kilomega network, SATA controller, XRS10L140, FLASH, CPLD and NVSRAM; The DDR internal memory of each IOP platform, kilomega network, SATA controller, FLASH, CPLD and NVSRAM all are connected with the IOP mainboard, wherein kilomega network is connected with the IOP mainboard by pci bus with the SATA controller, FLASH, CPLD are connected with the IOP mainboard by the PBI bus with NVSRAM, the SATA controller connects XRS10L140, and CPLD is by data/address bus control FLASH and NVRAM; PC is connected with the IOP mainboard of two IOP platforms by the kilomega network of two IOP platforms respectively, and the SATA controller that the IOP mainboard of two IOP platforms passes through separately respectively is connected with disk array by data wire again.
The IOP mainboard is the IOP331 mainboard, and kilomega network is 82545 kilomega networks, and the SATA controller is 8 mouthfuls of 88SX6081 SATA controllers.
FLASH wherein is used for the BOOTLOADER of storage system, kernel and file system etc., 82545 kilomega networks are the data that are used for receiving Network Transmission, the SATA controller can be used for articulating disk array, make soft RAID, CPLD is responsible for controlling chip select address decoding and the data buffering of FLASH and NVRAM, and NVRAM is used for the saved system configuration information.XRS10L140 is responsible for the switching to the SATA hard-disk interface, because the SATA hard disk has two interfaces unlike the SAS hard disk, so realize the expansion and the interface of SATA hard-disk interface are switched with XRS10L140 here.
The redundant device for switching of a kind of transmission data link of the present utility model is compared with prior art, method is simple, and is reliable, when can be implemented in a data transmission link and going wrong, another link is taken over it smoothly and is continued transmission, has guaranteed stability of data transmission; Thereby, have good value for applications.
Description of drawings
Below in conjunction with accompanying drawing the utility model is further specified.
Accompanying drawing 1 is a kind of structured flowchart that transmits the redundant device for switching of data link.
Embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
The redundant device for switching of a kind of transmission data link of the present utility model, its structure comprises PC, disk array and IOP platform, and PC is connected with the IOP platform, and the IOP platform is connected with disk array by data wire; The IOP platform is redundant the setting, and each IOP platform includes IOP mainboard, DDR internal memory, kilomega network, SATA controller, XRS10L140, FLASH, CPLD and NVSRAM; The DDR internal memory of each IOP platform, kilomega network, SATA controller, FLASH, CPLD and NVSRAM all are connected with the IOP mainboard, wherein kilomega network is connected with the IOP mainboard by pci bus with the SATA controller, FLASH, CPLD are connected with the IOP mainboard by the PBI bus with NVSRAM, the SATA controller connects XRS10L140, and CPLD is by data/address bus control FLASH and NVRAM; PC is connected with the IOP mainboard of two IOP platforms by the kilomega network of two IOP platforms respectively, and the SATA controller that the IOP mainboard of two IOP platforms passes through separately respectively is connected with disk array by data wire again.
The IOP mainboard is the IOP331 mainboard, and kilomega network is 82545 kilomega networks, and the SATA controller is 8 mouthfuls of 88SX6081S ATA controllers.
The redundant device for switching workflow of a kind of transmission data link of the present utility model is as follows:
Two IOP331 mainboards all can identify disk array by SATA controller and XRS10L140, for PC can be read and write data in disk array, at first will set up the transmission data link, and the process of setting up data transmission link is:
Start two iscsitarget in the mainboard respectively, IP among the iscsitarget is hereinafter set virtual IP address, far-end PC can identify set disk array in the iscsitarget script by the initiator on the PC like this, owing to be i.e. two links of two mainboards, we two links to be divided into advocate peace from, when wherein a link disconnected, another can connect, and let it be worked, and this part work is wrapped by cross compile UCARP in file system and realized.
UCARP is a simple address redundancy protocol, and it can be provided with virtual ip address on a pair of common main frame, and allows them realize that heat is equipped with automatically.We dispose a pair of fictitious host computer earlier, and for fictitious host computer disposes a pair of virtual IP, this is to be used for illustrating whether main frame is normal.Each main frame also needs a real IP, and each main frame all can be announced his state in regular hour issue broadcasting, and 1 of acquiescence just represents that main frame is normal, and 0 expression main frame has problem.Also need to write two scripts, one of them script allows him replace Host Status when main frame is made mistakes.Another script allows his relinquish host status when main frame recovers.Two IOP mainboard IP are provided with address 192.168.1.1 for we and 192.168.1.2 allows two mainboards can both respond the request of same IP address (192.168.1.252), stop when a mainboard goes wrong, and another can take over this service.At first we create a script, are used for adding virtual ip address, and we are stored in script/etc/vip-up.sh earlier
#！/bin/sh
/sbin/ip?addr?add?192.168.1.252?dev?eth0
We also will create a script that is used for closing real IP, and we are stored in script/etc/vip-down.sh earlier
#！/bin/sh
/sbin/ip?addr?del?192.168.1.252?dev?eth0
On first key plate, add real IP address and make corresponding 192.168.1.1 (the MASTER)/usr/local/sbin/ucarp-v 52-p mmm-a 10.1.1.252-s 10.1.1.1 ﹠amp of sign; On second mainboard, add real IP address and make corresponding 192.168.1.2 (the SLAVE)/usr/local/sbin/ucarp-v 52-p mmm-a 10.1.1.252-s 10.1.1.2 ﹠amp of sign;
" 52 " are virtual IP signs, and " mmm " is a password. now just can see that a mainboard has become the master, another become from.After the main disconnection, take over main work from meeting.The link redundancy of just having realized transfer of data when PC is to hard disk operation like this switches.
Except that the described technical characterictic of specification, be the known technology of those skilled in the art.
Claims (2)
1. the redundant device for switching of transmission data link comprises PC, disk array and IOP platform, and PC is connected with the IOP platform, and the IOP platform is connected with disk array by data wire; It is characterized in that the IOP platform is provided with for redundant, each IOP platform includes IOP mainboard, DDR internal memory, kilomega network, SATA controller, XRS10L140, FLASH, CPLD and NVSRAM; The DDR internal memory of each IOP platform, kilomega network, SATA controller, FLASH, CPLD and NVSRAM all are connected with the IOP mainboard, wherein kilomega network is connected with the IOP mainboard by pci bus with the SATA controller, FLASH, CPLD are connected with the IOP mainboard by the PBI bus with NVSRAM, the SATA controller connects XRS10L140, and CPLD is by data/address bus control FLASH and NVRAM; PC is connected with the IOP mainboard of two IOP platforms by the kilomega network of two IOP platforms respectively, and the SATA controller that the IOP mainboard of two IOP platforms passes through separately respectively is connected with disk array by data wire again.
2. the redundant device for switching of a kind of transmission data link according to claim 1 is characterized in that the IOP mainboard is the IOP331 mainboard, and kilomega network is 82545 kilomega networks, and the SATA controller is 8 mouthfuls of 88SX6081SATA controllers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200272392U CN201444642U (en) | 2009-06-10 | 2009-06-10 | Data transmission link redundancy switching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200272392U CN201444642U (en) | 2009-06-10 | 2009-06-10 | Data transmission link redundancy switching device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201444642U true CN201444642U (en) | 2010-04-28 |
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| CN2009200272392U Expired - Fee Related CN201444642U (en) | 2009-06-10 | 2009-06-10 | Data transmission link redundancy switching device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107589912A (en) * | 2017-09-12 | 2018-01-16 | 郑州云海信息技术有限公司 | The access method and device of a kind of hard disk |
| US10910025B2 (en) | 2012-12-20 | 2021-02-02 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Flexible utilization of block storage in a computing system |
-
2009
- 2009-06-10 CN CN2009200272392U patent/CN201444642U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10910025B2 (en) | 2012-12-20 | 2021-02-02 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Flexible utilization of block storage in a computing system |
| CN107589912A (en) * | 2017-09-12 | 2018-01-16 | 郑州云海信息技术有限公司 | The access method and device of a kind of hard disk |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100428 Termination date: 20120610 |