CN113595530B - Operation monitoring control circuit suitable for electric power secondary equipment - Google Patents
Operation monitoring control circuit suitable for electric power secondary equipment Download PDFInfo
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- CN113595530B CN113595530B CN202110845617.3A CN202110845617A CN113595530B CN 113595530 B CN113595530 B CN 113595530B CN 202110845617 A CN202110845617 A CN 202110845617A CN 113595530 B CN113595530 B CN 113595530B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 25
- 238000007599 discharging Methods 0.000 claims description 4
- 230000002441 reversible effect Effects 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000001143 conditioned effect Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses an operation monitoring control circuit suitable for electric power secondary equipment, which comprises a differential circuit, a first level comparison circuit, a level broadening circuit and an output buffer circuit; the input end of the differential circuit is connected with a trigger signal which is controlled and output by a processor, a controller or an FPGA program, and the output end of the differential circuit is connected with a first level comparison circuit; the output end of the first level comparison circuit is connected with the level broadening circuit, the output end of the level broadening circuit is connected with the output buffer circuit, and the output buffer circuit outputs a control signal. The circuit can monitor the running state of the used processor, controller or FPGA program, and meets the requirement of large parameter changes such as trigger signal period, duty ratio and the like output when the processor, controller or FPGA is used in different application occasions; meanwhile, the anti-interference capability is strong, the output signal quality is high, and the anti-interference device can be used for triggering execution circuits with different interface requirements.
Description
Technical Field
The invention belongs to an electric power system, and particularly relates to an operation monitoring control circuit suitable for electric power secondary equipment.
Background
The secondary power equipment uses processors and controllers as core processing components to complete the functions of system management, logic operation, online decision, outlet control and the like, and when the internal programs of the chips have the problems of running and the like, devices in the fields of protection, stability control, measurement and control and the like are in an uncontrolled state, and serious power system faults such as misoperation of an operation loop and the like can be caused. In addition, the FPGA is widely used in the electric power secondary equipment, in the fields of protection, stability control and the like, the FPGA is often used for synchronizing, sampling data receiving and transmitting and other functions, when the internal clock of the FPGA is greatly deviated, the time sequence logic state of the FPGA program is wrong, so that the functional module in the FPGA is abnormal, the operation of the FPGA is disordered, the failure of a device synchronizing system is easy to cause, the sampling data is abnormal, the communication is interrupted, and serious electric power system faults such as misoperation of an operation loop are also caused. In order to avoid the above problems, it is necessary to design an operation monitoring control circuit in the electric power secondary equipment, monitor the operation state of the processor, the controller or the FPGA program in real time, and output an abnormal signal to perform operations such as cutting off the operation power supply when the program abnormality is monitored.
Depending on the processor, controller, or FPGA program operating characteristics, the operation monitoring control circuit is typically implemented using monostable circuits. When the processor, the controller or the FPGA normally works, a periodic signal is output to trigger the monostable circuit, so that the monostable circuit is in a transient working mode, and the operating power supply and the like are kept in an effective state. When the processor, the controller or the FPGA works abnormally, the output signal of the monostable circuit is triggered to be lost or to be interrupted, so that the monostable circuit enters a steady-state working mode, an operation power supply is disconnected, and the like.
The monostable circuit mainly comprises a differential monostable circuit and an integral monostable circuit from the implementation principle, and the differential monostable circuit and the integral monostable circuit are thousands of years. The differential monostable circuit can be triggered by narrow pulse, but has the problems of overshoot and undershoot of the edge of an output pulse, low effective level of a falling edge and the like; the integral monostable circuit has stronger anti-interference capability, but has the problems of long output signal transition time, limited trigger pulse width and the like.
The coverage field of the electric power secondary equipment is wide, the parameters such as the period, the duty ratio and the like of the trigger signals output by the processor, the controller or the FPGA are used in different application occasions, and the high requirement is provided for the adaptability of the operation monitoring control circuit represented by a monostable circuit. How to design an operation monitoring control circuit with strong anti-interference capability, wide input response range and high output signal quality is an important work for realizing reliable operation of operation monitoring control of electric power secondary equipment.
The Chinese patent publication No. CN106374886A discloses a non-repeatable triggering CMOS integrated monostable circuit, wherein a realization method of the non-repeatable triggering CMOS integrated monostable circuit is provided, a stable current source is adopted to charge a capacitor, a stable control temporary stable time width is realized in an on-chip mode, the chip area is effectively reduced, and the monostable timing accuracy is improved. However, the monostable circuit in the prior art can only be triggered once, can not be triggered again in a short time, and can not meet the requirement of repeatable triggering in the operation monitoring control circuit of the secondary equipment of the road power. Meanwhile, the monostable circuit needs to be realized on a chip, monostable parameters are inconvenient to adjust, and the monostable circuit is difficult to adapt to the requirements of large parameter changes such as the monostable trigger signal period, the duty ratio and the like output by a processor, a controller or an FPGA in different application occasions.
Disclosure of Invention
The invention aims to: the invention aims to provide an operation monitoring control circuit suitable for electric power secondary equipment, which can meet the requirement that parameters such as a trigger signal period, a duty ratio and the like output by a processor, a controller or an FPGA are large in change in different application occasions, wherein the coverage field of the electric power secondary equipment is wide; meanwhile, the anti-interference capability is strong, the output signal quality is high, and the anti-interference device can be used for triggering execution circuits with different interface requirements.
The technical scheme is as follows: the invention comprises a differentiating circuit, a first level comparing circuit, a level widening circuit and an output buffer circuit; the input end of the differential circuit is connected with a trigger signal which is controlled and output by a processor, a controller or an FPGA program, and the output end of the differential circuit is connected with a first level comparison circuit; the output end of the first level comparison circuit is connected with the level broadening circuit, the output end of the level broadening circuit is connected with the output buffer circuit, and the output buffer circuit outputs a control signal.
The differential circuit comprises an RC differential circuit and a level clamping circuit, wherein the RC differential circuit comprises a capacitor C1, a resistor R1 and a resistor R2; one end of the capacitor C1 is connected with the input signal Vi, the other end of the capacitor C is respectively connected with one end of the resistor R1 and the level clamping circuit, and the other end of the resistor R1 is respectively connected with the resistor R2 and the first level comparison circuit.
The level clamping circuit comprises a clamping diode Z1 and a clamping diode Z2, the other end of the capacitor C1 is respectively connected with the anode of the clamping diode Z1 and the cathode of the clamping diode Z2, the cathode of the clamping diode Z1 is connected with a power supply Vcc, and the anode of the clamping diode Z2 is grounded GND.
The first level comparison circuit comprises a comparator U1, a resistor R3, a resistor R4 and a resistor R5; the positive input end of the comparator U1 is connected with the output end of the comparator U1 through a resistor R3, and the output end of the comparator U1 is connected with a level widening circuit; the reverse input end of the comparator U1 is respectively connected with a resistor R4 and a resistor R5.
The level widening circuit comprises an RC charge-discharge circuit and a second level comparison circuit, wherein the RC charge-discharge circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C2, a diode Z3 and a diode Z4; one end of the resistor R6 is connected with one end of the resistor R7, the other end of the resistor R6 is connected with the anode of the diode Z3, and the other end of the resistor R7 is connected with the cathode of the diode Z4; the cathode of the diode Z3 is connected to the anode of the diode Z4, one end of the capacitor C2 and one end of the resistor R8, the other end of the capacitor C2 is grounded, and the other end of the resistor R8 is connected with the resistor R9 and the second level comparison circuit respectively.
The second level comparison circuit has the same structure as the first level comparison circuit.
The charging time and the discharging time are set by adjusting the resistance values of the resistor R6 and the resistor R7 in the RC charging and discharging circuit.
The output buffer circuit comprises a logic gate, and an output end of the logic gate generates an output signal Vo.
The logic gate selects an AND gate NOR gate, and is determined according to the level of the driven source and positive and negative logic.
The logic gate type selects either a CMOS operating level or a TTL operating level.
The beneficial effects are that: compared with the prior art, the invention has the beneficial effects that: (1) Different types of trigger signals of a processor, a controller or an FPGA can be received, and the circuit has wide application range; (2) The input trigger signal is processed by adopting an improved differential circuit and level comparator mode, so that the problem that the effective level of the signal falling edge is low caused by directly using the differential circuit is solved; (3) The level widening circuit is realized by using a mode of adding a level comparator into an RC charge-discharge circuit, and the charge time and the discharge time can be independently set by setting different resistors, so that signals with different duty ratios can be conditioned; (4) The level widening circuit fully utilizes the characteristic of strong anti-interference capability of the integrating circuit, not only realizes the function of level width change, but also filters high-frequency noise; meanwhile, in order to solve the problems of long transition time, limited trigger pulse width and the like of an output signal of the integrating circuit, a comparator is used for shaping the output of the RC charge-discharge circuit; (5) The whole circuit is built by using the discrete devices such as the resistor, the capacitor, the logic gate circuit and the comparator, the technology implementation difficulty of the discrete devices is low, the autonomous controllable substitution can be realized, and the problem that the autonomous controllable substitution is difficult to realize by using the devices with high design difficulty or high integration level is solved.
Drawings
Fig. 1 is a schematic circuit structure of the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the detailed description and the attached drawings.
As shown in fig. 1, the present invention includes a differentiating circuit, a first level comparing circuit, a level widening circuit, and an output buffer circuit; the input end of the differential circuit is connected with a trigger signal which is controlled and output by a processor, a controller or an FPGA program, and the output end of the differential circuit is connected with the first level comparison circuit; the output end of the first level comparison circuit is connected with the level broadening circuit, the output end of the level broadening circuit is connected with the output buffer circuit, and the output buffer circuit outputs a control signal.
The differential circuit comprises an RC differential circuit and a level clamping circuit, wherein the RC differential circuit comprises a capacitor C1, a resistor R1 and a resistor R2; one end of the capacitor C1 is connected with the input signal Vi, the other end of the capacitor C is respectively connected with one end of the resistor R1 and the level clamping circuit, the other end of the resistor R1 is respectively connected with the resistor R2 and the first level comparison circuit, and the resistor R2 is grounded. The level clamping circuit comprises a clamping diode Z1 and a clamping diode Z2, the other end of the capacitor C1 is respectively connected with the anode of the clamping diode Z1 and the cathode of the clamping diode Z2, the cathode of the clamping diode Z1 is connected with a power supply Vcc, and the anode of the clamping diode Z2 is grounded GND. The two series resistors R1 and R2 form voltage division, the voltage division output result of the series resistors is connected to the reverse input end of the comparator U1 in the level comparison circuit, and the pulse level of differential output can be prevented from impacting the comparator through the voltage division of the series resistors. The level clamping circuit is arranged at the output end of the capacitor C1 and eliminates out-of-limit spike pulse of differential output.
The first level comparison circuit comprises a comparator U1, a resistor R3, a resistor R4 and a resistor R5; the other end of the resistor R1 in the differential circuit is connected with the positive input end 2 of the comparator U1, the positive input end 2 of the comparator U1 is also connected with the output end 1 of the comparator U1 through the resistor R3, and the output end 1 of the comparator U1 is connected with the level widening circuit; the inverting input terminal 3 of the comparator U1 is respectively connected to a resistor R4 and a resistor R5, the resistor R4 is connected to the power supply Vcc, and the resistor R5 is connected to the ground GND. In the present invention, the first level comparing circuit performs level comparison using the comparator U1. The comparison reference level is obtained by dividing the power supply by using a resistor R4 and a resistor R5, when the output voltage of the differentiating circuit is higher than the comparison reference level, the comparator U1 outputs a low level, otherwise, the comparator U1 outputs a high level. The output signal of the differentiating circuit is processed by the first level comparing circuit, so that the defect of low effective level of the signal falling edge can be effectively reduced; meanwhile, hysteresis voltage is set by utilizing the positive feedback resistor of the comparator, so that the circuit can adapt to wider input noise and improve the anti-interference capability of the circuit.
The level widening circuit comprises an RC charge-discharge circuit and a second level comparison circuit, wherein the RC charge-discharge circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C2, a diode Z3 and a diode Z4. The second level comparison circuit comprises a resistor R10, a resistor R11, a resistor R12 and a comparator U2. The output end 1 of the comparator U1 in the first level comparison circuit is respectively connected with a resistor R6 and a resistor R7. One end of a resistor R6 is connected with one end of a resistor R7, the other end of the resistor R6 is connected with the anode of a diode Z3, and the other end of the resistor R7 is connected with the cathode of a diode Z4; the cathode of the diode Z3 is simultaneously connected to the anode of the diode Z4, one end of the capacitor C2 and one end of the resistor R8, the other end of the capacitor C2 is grounded, and the other end of the resistor R8 is respectively connected with the resistor R9, the resistor R10 and the positive input end 2 of the comparator U2. Resistor R9 is connected to GND and resistor R10 is connected to output 1 of comparator U2. The inverting input 3 of the comparator U2 is connected to the resistor R11 and the resistor R12. In the invention, the RC charge-discharge circuit isolates the charge loop resistor from the discharge loop resistor by using diodes with different conducting directions, and the charge time and the discharge time are set by adjusting the resistance values of the resistor R6 and the resistor R7 in the RC charge-discharge circuit, so that signals with different duty ratios can be conditioned. The output of the charge-discharge loop is connected with a second level comparison circuit, the second level comparison circuit is realized by selecting a comparator U2, and the reference level is compared and obtained by using a resistor to divide the voltage of the power supply. The adjustment of the pulse width of the input level can be completed by adjusting the time constant of the charge-discharge circuit and comparing the reference level, so that the function of level widening is realized. The RC charge-discharge loop is an integral circuit in nature, and the level widening circuit fully utilizes the characteristic of strong anti-interference capability of the integral circuit, so that the function of level width change is realized, and high-frequency noise is filtered; meanwhile, in order to solve the problems of long transition time of an output signal of the integrating circuit, limited trigger pulse width and the like, a comparator is used for shaping the output of the RC charge-discharge loop.
The output buffer circuit comprises a NOT gate U3, a resistor R10 is connected with an input end 1 of the NOT gate U3, and an output end 2 of the NOT gate U3 generates an output signal Vo. The output buffer circuit is realized by using logic gates, the logic gates can select AND gates or NOR gates according to different levels of the driven source and different positive and negative logics, the logic gates can select CMOS working level or TTL working level, and the power supply level can select 3.3V or 5V.
The working principle of the invention is as follows: the processor, the controller or the FPGA program outputs periodic pulse signals Vi, the Vi is reversed in a specified time to prove that the processor, the controller or the FPGA program runs in a normal state, and therefore the jump state of the Vi is needed to be used for analyzing whether the program runs normally or not. Vi is sent into an operation monitoring control circuit, and firstly, the jump edge of Vi is obtained by taking differentiation through a differentiating circuit consisting of a resistor R1, a resistor R2 and a capacitor C1. Because the differentiated signal is easy to overshoot and exceeds the allowable working range of the input end of the comparator U1, two protection measures are added in the differentiating circuit, namely, the clamping diodes Z1 and Z2 are designed to clamp the signal, and the resistors R1 and R2 are used for dividing the voltage.
Since the differentiated signal output is an analog signal and the level state cannot be directly determined, the signal output from the differentiating circuit is sent to the level comparing circuit, and the signal is shaped by the comparator U1 and converted into a CMOS level signal. The comparison reference level of the comparator U1 is obtained by dividing the power supply voltage Vcc using the resistors R4 and R5. The frequency of the comparator output signal can be changed by adjusting the magnitude of the comparison level.
The level comparison circuit outputs a CMOS level signal, but the signal duty cycle at the time of partial application is small. Therefore, a level widening circuit is designed, the RC charge-discharge circuit is used for adjusting the signal duty ratio, and the CMOS level is obtained through shaping of a comparator U2.
Since the operation monitoring control circuit is commonly used to drive the operation loop control circuit and various status indication circuits, the direct use of the comparator output is difficult to adapt to these applications. An output buffer circuit is thus designed, using a logic not gate U3 for buffering. According to different levels and different positive and negative logics of the driven source, the NOT gate U3 is replaced by an AND gate, the output level type can select a CMOS working level or a TTL working level, and the power supply can select 3.3V or 5V.
When the input signal Vi in the circuit is a direct current level or the frequency is lower than a set value, the output signal Vo is fixed to output a high level; when the frequency of the input signal Vi is higher than the set value, vo is fixed to output a low level.
Claims (6)
1. An operation monitoring control circuit suitable for electric power secondary equipment, characterized in that: the device comprises a differentiating circuit, a first level comparing circuit, a level widening circuit and an output buffer circuit; the input end of the differential circuit is connected with a trigger signal which is controlled and output by a processor, a controller or an FPGA program, and the output end of the differential circuit is connected with a first level comparison circuit; the output end of the first level comparison circuit is connected with the level broadening circuit, the output end of the level broadening circuit is connected with the output buffer circuit, and the output buffer circuit outputs a control signal;
The differential circuit comprises an RC differential circuit and a level clamping circuit, wherein the RC differential circuit comprises a capacitor C1, a resistor R1 and a resistor R2; one end of the capacitor C1 is connected with an input signal Vi, the other end of the capacitor C is respectively connected with one end of the resistor R1 and the level clamping circuit, and the other end of the resistor R1 is respectively connected with the resistor R2 and the first level comparison circuit;
The level clamping circuit comprises a clamping diode Z1 and a clamping diode Z2, the other end of the capacitor C1 is respectively connected with the anode of the clamping diode Z1 and the cathode of the clamping diode Z2, the cathode of the clamping diode Z1 is connected with a power supply Vcc, and the anode of the clamping diode Z2 is grounded GND;
the first level comparison circuit comprises a comparator U1, a resistor R3, a resistor R4 and a resistor R5; the positive input end of the comparator U1 is connected with the output end of the comparator U1 through a resistor R3, and the output end of the comparator U1 is connected with a level widening circuit; the reverse input end of the comparator U1 is respectively connected with a resistor R4 and a resistor R5;
the level widening circuit comprises an RC charge-discharge circuit and a second level comparison circuit, wherein the RC charge-discharge circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C2, a diode Z3 and a diode Z4; one end of the resistor R6 is connected with one end of the resistor R7, the other end of the resistor R6 is connected with the anode of the diode Z3, and the other end of the resistor R7 is connected with the cathode of the diode Z4; the cathode of the diode Z3 is connected to the anode of the diode Z4, one end of the capacitor C2 and one end of the resistor R8, the other end of the capacitor C2 is grounded, and the other end of the resistor R8 is connected with the resistor R9 and the second level comparison circuit respectively.
2. The operation monitoring control circuit for electric power secondary equipment according to claim 1, wherein: the second level comparison circuit has the same structure as the first level comparison circuit.
3. The operation monitoring control circuit for electric power secondary equipment according to claim 1, wherein: the charging time and the discharging time are set by adjusting the resistance values of the resistor R6 and the resistor R7 in the RC charging and discharging circuit.
4. The operation monitoring control circuit for electric power secondary equipment according to claim 1, wherein: the output buffer circuit comprises a logic gate, and an output end of the logic gate generates an output signal Vo.
5. The operation monitoring control circuit for electric power secondary equipment according to claim 4, wherein: the logic gate selects an AND gate NOR gate, and is determined according to the level of the driven source and positive and negative logic.
6. The operation monitoring control circuit for electric power secondary equipment according to claim 4, wherein: the logic gate type selects either a CMOS operating level or a TTL operating level.
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| CN202110845617.3A CN113595530B (en) | 2021-07-26 | 2021-07-26 | Operation monitoring control circuit suitable for electric power secondary equipment |
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| CN202110845617.3A CN113595530B (en) | 2021-07-26 | 2021-07-26 | Operation monitoring control circuit suitable for electric power secondary equipment |
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| CN113595530B true CN113595530B (en) | 2024-07-19 |
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| CN101394165A (en) * | 2008-10-30 | 2009-03-25 | 上海大学 | Differentiation hysteresis comparator and application thereof |
| CN108955866A (en) * | 2017-05-21 | 2018-12-07 | 天津大学（青岛）海洋工程研究院有限公司 | A kind of piezoelectric vibration frequency sensor system based on biasing reverse circuit |
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| DE2440424C3 (en) * | 1974-08-23 | 1981-04-16 | Robert 7995 Neukirch Buck | Circuit arrangement for monitoring two pulse trains |
| CN2048271U (en) * | 1988-12-03 | 1989-11-22 | 戴品忠 | Audio control timing lamp |
| JPH11145796A (en) * | 1997-11-12 | 1999-05-28 | Fujitsu Ltd | Pulse width control circuit and duty factor detection circuit |
| JP2001053732A (en) * | 1999-08-13 | 2001-02-23 | Oki Comtec Ltd | Nonlinear extraction circuit and clock extracting circuit |
| US6504409B1 (en) * | 2001-04-17 | 2003-01-07 | K-Tek Corporation | Controller for generating a periodic signal with an adjustable duty cycle |
| CN101968541B (en) * | 2010-09-17 | 2012-07-11 | 国营红林机械厂 | Pulse ultra-wideband ranging system |
| CN203720666U (en) * | 2014-01-15 | 2014-07-16 | 浙江大学 | Intelligent water full automation control system |
| CN205647492U (en) * | 2016-04-21 | 2016-10-12 | 常州信息职业技术学院 | Motor rotation number processing circuit |
| CN109302177A (en) * | 2018-11-27 | 2019-02-01 | 国网上海市电力公司 | A kind of digital feedback precision square wave phase shifter based on two frequency multiplication two divided-frequencies |
| CN112986724B (en) * | 2021-02-01 | 2023-03-28 | 南京南瑞继保电气有限公司 | Electric power secondary equipment test control management device |
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|---|---|---|---|---|
| CN101394165A (en) * | 2008-10-30 | 2009-03-25 | 上海大学 | Differentiation hysteresis comparator and application thereof |
| CN108955866A (en) * | 2017-05-21 | 2018-12-07 | 天津大学（青岛）海洋工程研究院有限公司 | A kind of piezoelectric vibration frequency sensor system based on biasing reverse circuit |
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