CN110426551B - Satellite-borne single-particle locking detection recovery circuit - Google Patents
Satellite-borne single-particle locking detection recovery circuit Download PDFInfo
- Publication number
- CN110426551B CN110426551B CN201910815543.1A CN201910815543A CN110426551B CN 110426551 B CN110426551 B CN 110426551B CN 201910815543 A CN201910815543 A CN 201910815543A CN 110426551 B CN110426551 B CN 110426551B
- Authority
- CN
- China
- Prior art keywords
- mosfet
- circuit
- pin
- locking
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
Abstract
The invention discloses a satellite-borne single particle locking detection recovery circuit, wherein a current detection amplifying circuit detects the current of a plurality of secondary power supplies, converts each path of current into a weak voltage value respectively, and outputs the weak voltage value after amplification; the ADC acquisition circuit acquires a plurality of paths of analog voltage values output by the current detection amplifying circuit, converts each path of analog voltage value into a corresponding digital signal respectively and sends the digital signal to the locking judgment processing circuit; the locking judgment processing circuit judges whether the circuit is locked by single particles or not according to each path of digital signal and correspondingly outputs an MOSFET enabling control signal to the MOSFET switch circuit; the MOSFET switch circuit controls the on-off of the secondary power supply according to the MOSFET enabling control signal, so that the function of anti-single event locking is realized. The single event locking detection recovery function of different device satellite-borne circuits in different modes can be realized.
Description
Technical Field
The application relates to the field of electronic circuit design, in particular to a satellite-borne single event locking detection recovery circuit.
Background
Due to the particularity of the space environment, in the in-orbit operation process of the satellite, the devices on the satellite are influenced by the single particles, latching is easy to occur, and when the latching occurs, a low-impedance channel is established between a power supply and the ground of the CMOS integrated circuit, so that a very large current is generated. If the current is not limited, the device will burn out.
The traditional anti-single-particle locking circuit generally adopts a mode that a power supply end is connected with a current-limiting resistor in series, when latch-up occurs, the current entering an integrated circuit is controlled through the current-limiting function of the resistor, and the device is ensured not to be burnt.
At present, large-scale and high-power-consumption integrated circuits are used in aerospace in a large scale, requirements of an interface power supply and a core power supply of a device are higher and higher, current is higher and higher, and if a traditional current limiting mode is adopted, voltage drop is larger, so that normal work of the device is possibly influenced; in addition, the integration level of the satellite-borne products is higher and higher, the same product has multiple working modes, the current variation of the secondary power supply corresponding to different working modes is large, and if a traditional single event resistant locking circuit is still adopted, the size of current limiting is set in a hardware mode, and the protection function of devices in different modes cannot be met.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to solve the problem of single event locking resistance of the satellite-borne product under the conditions of large current, different devices and different working modes.
In order to solve the problems, the invention provides a satellite-borne single-particle locking detection recovery circuit which comprises a current detection amplifying circuit, an ADC (analog to digital converter) acquisition circuit, an MOSFET (metal-oxide-semiconductor field effect transistor) switching circuit and a locking judgment processing circuit, wherein the current detection amplifying circuit detects the current of a plurality of secondary power supplies, converts each current into a weak voltage value respectively, and outputs the weak voltage value after amplification; the ADC acquisition circuit acquires a plurality of paths of analog voltage values output by the current detection amplifying circuit, converts each path of analog voltage value into a corresponding digital signal respectively and sends the digital signal to the locking judgment processing circuit; the locking judgment processing circuit judges whether the circuit is locked by single particles or not according to each path of digital signal and correspondingly outputs an MOSFET enabling control signal to the MOSFET switch circuit; the MOSFET switch circuit controls the on-off of the secondary power supply according to the MOSFET enabling control signal, so that the function of anti-single event locking is realized.
Preferably, the lock determination processing circuit averages the digital signal, and compares the average with a single event lock current threshold in a corresponding operating mode: if the average value is smaller than the single event locking current threshold value, judging that the circuit does not generate the single event locking phenomenon, wherein the MOSFET enabling control signal output by the locking judgment processing circuit is at a low level; if the average value is larger than the single event lockout current threshold value and the duration time exceeds the current threshold value time, the circuit is judged to have the single event lockout phenomenon, the MOSFET enabling control signal output by the lockout judgment processing circuit is in a high level, so that the secondary power supply output is turned off, and the MOSFET enabling control signal output after a certain time is in a low level, so that the function of anti-single event lockout recovery is realized.
Preferably, the current detection amplifying circuit includes a precision sampling resistor RC1, voltage dividing resistors R1, R2, R3, R4, filter capacitors C1, C2, protection resistors R10, R12, a diode V2 and an amplifier A1, wherein the precision sampling resistor RC1 is connected in series between the secondary power input terminal and the MOSFET switching circuit, and the precision sampling resistor RC1 converts a current value flowing therethrough into a voltage value; two ends of the divider resistor R1 are respectively connected with the 4 ends of the precision sampling resistor RC1 and the non-inverting input end of the amplifier A1; two ends of the divider resistor R2 are respectively connected with the non-inverting input end of the amplifier A1 and the GND; two ends of the divider resistor R3 are respectively connected with the end 3 of the precision sampling resistor RC1 and the inverting input end of the amplifier A1; two ends of the divider resistor R4 are respectively connected with the inverting input end of the amplifier A1 and the output end of the amplifier A1; two ends of the filter capacitor C1 are respectively connected with the non-inverting input end of the amplifier A1 and the GND; two ends of the filter capacitor C2 are respectively connected with the inverting input end of the amplifier A1 and the GND; two ends of the protective resistor R10 are respectively connected with the output end of the amplifier A1 and the negative end of the diode V2; the two ends of the protective resistor R12 are respectively connected with the negative end of the diode V2 and GND; the positive end of the diode V2 is connected with GND.
Preferably, the amplifier A1 is OP400AY/QMLV.
Preferably, the ADC acquisition circuit includes an AD acquisition chip D1, configuration resistors R13, R14, R15, and R16, and filter capacitors C100, C101, C102, and C103, wherein a plurality of voltages output by the current detection amplifying circuit are respectively connected to any different pins at the IN0 to IN7 ends of the ADC acquisition chip D1; an enabling signal 1 pin of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R14; a control signal pin 14 of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R16; a clock signal 16 pin of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R15; the pin 15 of the output signal of the ADC acquisition chip D1 is connected to the locking judgment processing circuit; a VA end 2 pin of the ADC acquisition chip D1 is connected to 5V voltage; one end of each of the filter capacitors C102 and C103 is connected to a pin 2 of the ADC acquisition chip D1, and the other end of each of the filter capacitors is connected to the ground; a VD end 13 pin of the ADC acquisition chip D1 is connected to a 5V voltage through a resistor R13; one end of each of the filter capacitors C100 and C101 is connected to pin 13 of the ADC acquisition chip D1, and the other end is connected to ground.
Preferably, the ADC acquisition chip D1 is selected as ADC128S102WGRQV.
Preferably, the locking judgment processing circuit includes a microprocessor chip D2, wherein an enable signal pin 1 of the ADC acquisition chip D1 is connected to an output terminal of the microprocessor chip D2; a control signal pin 14 of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2; a clock signal 16 pin of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2; an output signal 15 pin of the ADC acquisition chip D1 is connected to the input end of the microprocessor chip D2; a plurality of paths of MOSFET enabling control signal marks of the microprocessor chip D2 are output to corresponding single machine telemetering processing modules; and the MOSFET enabling control signals of the microprocessor chip D2 are respectively connected to the MOSFET switch circuit.
Preferably, the microprocessor chip D2 is an FPGA product having single particle resistance and radiation resistance.
Preferably, the MOSFET switch circuit includes a current-limiting resistor R20, protection resistors R21 and R22, filter capacitors C9 and C10, and a MOSFET V1, wherein two ends of the protection resistor R21 are respectively connected to pin 3 and pin 1 of the MOSFET V1; two ends of the filter capacitor C10 are respectively connected to a pin 3 and a pin 2 of the MOSFET V1; two ends of the protective resistor R20 are respectively connected to a pin 2 of the MOSFET V1 and an MOSFET enabling control signal output end of the microprocessor chip D2; two ends of the filter capacitor C9 are respectively connected to a pin 2 of the MOSFET V1 and GND; two ends of the protective resistor R22 are respectively connected to a pin 2 and GND of the MOSFET V1; the secondary power supply output by the current detection amplifying circuit 1 is connected to the 3 pins of the MOSFET V1, and is output by the 1 pin of the MOSFET V1 after passing through the MOSFET V1.
Preferably, the MOSFET tube V1 is an IRL5NJ 7404P-channel MOSFET tube.
Compared with the prior art, the invention has the following technical effects:
1. the satellite-borne single-particle locking detection recovery circuit can realize the single-particle locking detection recovery function of different device satellite-borne circuits in different modes.
2. The current detection amplifying circuit of the embodiment of the invention converts weak voltage signals into voltage signals suitable for ADC acquisition by detecting the voltage at two ends of the precision sampling resistor, and has the characteristics of high precision, high gain, robustness, small size and low cost.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. In the drawings:
FIG. 1 is a block diagram of a structure of a satellite-borne single event lock detection recovery circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a current sense amplifier circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an ADC acquisition circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a lock determination processing circuit according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a MOSFET switch circuit according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a recovery circuit for detecting a satellite-borne single event latch according to an embodiment of the present invention.
Detailed Description
The present invention is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments, and those skilled in the art can modify and revise the present invention within the scope that does not change the spirit and content of the present invention.
The satellite-borne single event locking detection recovery circuit flexibly sets different single event locking resistance threshold values according to the current using conditions of each actual power supply in different working states, effectively solves the problem of single event locking resistance of large current, different devices and different working states, realizes the single event locking detection and recovery functions of different power supplies, and is reliable in circuit and strong in expansibility.
Referring to fig. 1 and fig. 6, the satellite-borne single event latchup detection and recovery circuit according to the embodiment of the present invention includes a current detection amplifying circuit 1, an ADC collecting circuit 2, a latchup judgment processing circuit 3, and a MOSFET switch circuit 4, wherein,
the current detection amplifying circuit 1 detects the currents of a plurality of paths of secondary power supplies, converts each path of current into a weak voltage value respectively, and outputs the weak voltage value after amplification;
the ADC acquisition circuit 2 acquires a plurality of paths of analog voltage values output by the current detection amplifying circuit, converts each path of analog voltage value into a corresponding digital signal respectively and sends the digital signal to the locking judgment processing circuit;
the locking judgment processing circuit 3 judges whether the circuit is locked by single particles or not according to each path of digital signals and correspondingly outputs an MOSFET enabling control signal to be output to the MOSFET switch circuit;
specifically, the locking judgment processing circuit 3 can realize the control of the anti-single event locking function of the multi-path input secondary power supply; the locking judgment processing circuit controls the ADC acquisition circuit to respectively acquire current values of different paths of secondary power supplies, digital filtering processing is carried out on the sent digital signals, an average value is obtained on the data after abnormal values are eliminated, and the average value is used as a final sampling value; then, comparing the final sampling value with a single event locking current threshold value corresponding to the working mode, if the sampling value is smaller than the corresponding single event locking current threshold value, judging that the circuit does not generate a single event locking phenomenon, always outputting a low level by a locking judgment processing circuit, supplying power to a target load by a secondary power supply, and simultaneously outputting a remote measurement signal without single event locking; if the sampling value is greater than the corresponding single event locking current threshold value and the duration exceeds the current threshold value time, judging that the circuit has a single event locking phenomenon, and outputting a high level by the locking judgment processing circuit to block a secondary power supply from supplying power to a target load, thereby realizing the function of resisting single event locking and simultaneously outputting a telemetering signal for locking the occurrence of the single event; the locking judgment processing circuit automatically outputs low level after a certain time, and the secondary power supply is recovered to supply power to the target load, so that the anti-single event recovery function is realized.
And the MOSFET switch circuit 4 controls the on-off of the secondary power supply according to the MOSFET enabling control signal, so that the function of anti-single event locking is realized.
As a possible embodiment, referring to fig. 2, the current detection amplifying circuit 1 includes a precision sampling resistor RC1, voltage dividing resistors R1, R2, R3, and R4, filter capacitors C1 and C2, protection resistors R10 and R12, a diode V2, and an amplifier A1, wherein,
the precision sampling resistor RC1 is connected in series between the input end of the secondary power supply and the MOSFET switch circuit 4, the precision sampling resistor RC1 converts the current value flowing through the precision sampling resistor RC1 into a voltage value, two ends of the divider resistor R1 are respectively connected with the 4 ends of the precision sampling resistor RC1 and the non-inverting input end of the amplifier A1, two ends of the divider resistor R2 are respectively connected with the non-inverting input end of the amplifier A1 and the GND, two ends of the divider resistor R3 are respectively connected with the 3 ends of the precision sampling resistor RC1 and the inverting input end of the amplifier A1, and two ends of the divider resistor R4 are respectively connected with the inverting input end of the amplifier A1 and the output end of the amplifier A1; the two ends of the filter capacitor C1 are respectively connected with the non-inverting input end and the GND of the amplifier A1, the two ends of the filter capacitor C2 are respectively connected with the inverting input end and the GND of the amplifier A1, the two ends of the protective resistor R10 are respectively connected with the output end of the amplifier A1 and the negative end of the diode V2, the two ends of the protective resistor R12 are respectively connected with the negative end and the GND of the diode V2, and the positive end of the diode V2 is connected with the GND.
That is, the in-phase proportional amplifier circuit mode adopted by the amplifier A1 is composed of a divider resistor network and an operational amplifier, so that the gain of the whole current detection amplifier circuit can be flexibly changed, and the gains of the two stages of amplifiers can be equalized. Wherein, the non-inverting input end of the amplifier is connected with the voltage dividing resistors R1 and R2, the inverting input end is connected with the voltage dividing resistors R3 and R4, the other ends of the voltage dividing resistors R2 and R4 are respectively grounded, the inverting input end of the amplifier A1 is connected to the output end of the amplifier through a resistor R4, the non-inverting input end of the amplifier A1 is grounded through a resistor R2, and the output end of the amplifier A1 is connected to the ADC acquisition circuit 2 through a protection resistor R10. One end of the protective resistor R12 and the diode is connected with the output of the R10, and the other end is grounded.
In this embodiment, the amplification factor of the amplifier is set according to the voltage value of the R12 terminal, and it is ensured that the voltage value of the R12 terminal is not greater than 3.5V.
Specifically, the resistance values of the voltage dividing resistors R1 and R2 are determined according to the amplification factor of the amplifier A1; the resistance values of the voltage dividing resistors R1 and R3 are the same, and the resistance values of the voltage dividing resistors R2 and R4 are the same; the amplification factor N of the amplifier A1 is equal to the resistance of the divider resistor R4 divided by the resistance of the divider resistor R3; the adjustment of the amplification factor N of the amplifier A1 ensures that the voltage of the output end protection resistor R12 of the amplifier A1 is below 3.5V when the circuit normally works;
wherein, the amplification factor N of the reverse phase amplification is:
n = R4/R3, the resistance values of R3 and R4 dividing resistors R3 × and R4, respectively;
the R12 terminal voltage Vanalog is:
V analog ＝N·U Rc
＝N·R C ·I
＝I·R C ·R4/R3
n is the amplification factor of the amplifier A1, rc is the resistance value of the precision sampling resistor RC, and I is the steady-state current value of the secondary power supply.
In this embodiment, the accurate sampling resistor RC1 is a WFM series current sensing resistor manufactured by Vishay corporation, and the series current sensing resistor has the characteristics of low resistance, low inductance, good high-frequency characteristics, low temperature drift and the like, and is suitable for current sensing in various occasions such as switching power supplies and linear power supplies.
In this embodiment, the resistance of the precision sampling resistor RC1 is determined according to the magnitude of the steady-state current of each secondary power supply. For example, when the load steady-state current is 1A, a CSM3637 series product with the resistance value smaller than 50m Ω can be selected, and the voltage drop of the power supply does not exceed 0.05V, so that the load cannot be greatly influenced; when the load steady-state current exceeds 3A, CSM3637 series products with the resistance value smaller than 10m omega can be selected, and the voltage drop of the power supply does not exceed 0.03V, so that the influence on the rear-stage load is avoided.
In the embodiment, the amplifier A1 is OP400AY/QMLV, the chip is V-level, the use requirement of the satellite-borne amplifier is met, and the OP400AY/QMLV has the characteristics of low offset voltage, low input offset current, low voltage noise spectral density, high open-loop gain, high common-mode rejection ratio and the like, and is very suitable for small-signal amplification.
As a feasible embodiment, please refer to fig. 3, the ADC acquisition circuit 2 includes an AD acquisition chip D1, configured resistors R13, R14, R15, R16, and filter capacitors C100, C101, C102, C103, wherein a plurality of voltages output by the current detection amplifying circuit are respectively connected to any different pins IN the IN 0-IN 7 ends of the ADC acquisition chip D1, as shown IN fig. 3, the voltages output by the current detection amplifying circuit are respectively connected to the IN 0-IN 3 ends of the ADC acquisition chip D1, the enable signal 1 pin of the ADC acquisition chip D1 is connected to the lock determination processing circuit 3 through a resistor R14, the control signal 14 pin of the ADC acquisition chip D1 is connected to the lock determination processing circuit 3 through a resistor R16, the clock signal 16 pin of the ADC acquisition chip D1 is connected to the lock determination processing circuit 3 through a resistor R15, the output signal 15 pin of the ADC acquisition chip D1 is connected to the lock determination processing circuit 3, the VA terminal 2 pin of the ADC acquisition chip D1 is connected to the voltage of 5V, one end of the filter capacitors C102, one end of the filter capacitors C103 is connected to the ADC acquisition chip D1, and the other end of the ADC acquisition chip D1 is connected to the voltage acquisition chip V13; one end of each of the filter capacitors C100 and C101 is connected to pin 13 of the ADC acquisition chip D1, and the other end is connected to ground.
In this embodiment, the ADC acquisition chip D1 is an ADC128S102WGRQV, which is a V-stage, and meets the condition of satellite-borne use, and the ADC128S102QML has an 8-way analog-to-digital converter with a wide input voltage range, a linear error of not more than ± 1.5LSB, and a no-missing-code precision of 12 bits; the ADC128S102QML analog input is preceded by a voltage follower for matching the input impedance of a few k omega levels of the analog-to-digital converter to meet the requirement of sampling precision.
As a possible embodiment, the lock determination processing circuit 3 has functions of performing digital filtering processing on the sampled data, performing a configurable/annotated function, and controlling the MOSFET switch circuit, wherein the digital filtering function is to eliminate abnormal values (maximum and minimum values) from the sampled data and then average the data to obtain a final sampling value; the configurable/injection function refers to locking a current threshold, exceeding the current threshold, automatically opening the power of the MOSFET switch, and the like, and can be configured or switched through a remote control command; the MOSFET switch circuit is controlled to send a high level to turn off the MOSFET transistor and send a low level to turn on the MOSFET transistor by the MOSFET enable control signal, referring to fig. 4, the lock determination processing circuit includes a microprocessor chip D2, wherein,
an enabling signal 1 pin of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2;
a control signal pin 14 of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2;
a clock signal 16 pin of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2;
an output signal 15 pin of the ADC acquisition chip D1 is connected to the input end of the microprocessor chip D2;
4 paths of secondary power supply MOSFET control signals (a secondary power supply 1 locking mark, a secondary power supply 2 locking mark, a secondary power supply 3 locking mark and a secondary power supply 4 locking mark) of the microprocessor chip D2 are output to the corresponding single machine telemetering processing module;
the 4 paths of MOSFET enable control signals (PMOS GATE 1, PMOS GATE 2, PMOS GATE 3 and PMOS GATE 4) of the microprocessor chip D2 are respectively connected with one end of the resistor R20 of the 4 paths of MOSFET switch circuits with enable ends.
The microprocessor chip selects FPGA products with single particle resistance and radiation resistance, such as antifuse chips of Actel company.
The microprocessor chip D2 outputs an enabling signal, a control signal and a clock signal to the ADC acquisition chip D1, and controls the ADC acquisition chip D1 to output digital quantity telemetering according to the frequency of 0.5S; the microprocessor chip D2 controls the MOSFET switch circuit to output MOSFET control signals; and the microprocessor chip D2 outputs a mark whether the circuit is locked or not according to whether the circuit is locked by the single event or not.
The microprocessor chip D2 compares the acquired digital quantity remote measurement value with a single-event locking current threshold value in a corresponding working mode, if the acquired digital quantity remote measurement value is larger than the single-event locking current threshold value and the duration time exceeds the current threshold value time, the circuit is judged to have a single-event locking phenomenon, the locking judgment processing circuit 4 outputs a high level to close the MOSFET V1, and simultaneously outputs a signal for single-event locking telemetering measurement; if the collected digital quantity remote measurement value is smaller than the single event locking current threshold value, the circuit is judged not to have the single event locking phenomenon, the locking judgment processing circuit 4 outputs low level all the time to open the MOSFET V1, and simultaneously outputs a remote measurement signal which does not have the single event locking phenomenon.
In this embodiment, the working mode of the product, the single event latchup current threshold and the time of exceeding the current threshold may be configured or counted according to the actual use condition of the product, wherein the single event latchup current threshold may be set according to the magnitude of the steady-state current value of the secondary power supply, and the recommended threshold is set to be 1.2 to 1.4 times of the steady-state current value.
As a possible embodiment, referring to fig. 5, the MOSFET switch circuit 4 includes a current limiting resistor R20, protection resistors R21, R22, filter capacitors C9, C10 and a P-channel MOSFET V1, wherein,
two ends of the protective resistor R21 are respectively connected to a pin 3 and a pin 1 of the MOSFET V1;
two ends of the filter capacitor C10 are respectively connected to a pin 3 and a pin 2 of the MOSFET V1;
two ends of the protective resistor R20 are respectively connected to a pin 2 of the MOSFET V1 and an MOSFET enabling control signal output end of the microprocessor chip;
two ends of the filter capacitor C9 are respectively connected to a pin 2 of the MOSFET V1 and GND;
two ends of the protective resistor R22 are respectively connected to a pin 2 and GND of the MOSFET V1;
the secondary power supply output from the current detection amplifying circuit 1 is connected to a pin 3 of the MOSFET V1, and is output to each stage of rear-end circuits from a pin 1 of the MOSFET V1.
The MOSFET control signal is connected to a pin 2 of the MOSFET V1 through a resistor R20, the MOSFET control signal is a TTL signal, the level is 5V, when the MOSFET control signal is low level (0V), the MOSFET V1 is opened, and a pin 1 of the MOSFET V1 outputs a secondary power supply; when the MOSFET control signal is at a high level (5V), the MOSFET V1 is closed, and no secondary power supply is output at pin 1 of the MOSFET V1.
In this embodiment, the MOSFET V1 is IRL5NJ7404, which is a highly reliable P-channel MOSFET with low on-resistance, large current passing capability, and small control voltage.
The above disclosure is only one specific embodiment of the present application, but the present application is not limited thereto, and any variations that can be considered by those skilled in the art are within the scope of the present application.
Claims (8)
1. A satellite-borne single-particle locking detection recovery circuit is characterized by comprising a current detection amplifying circuit, an ADC acquisition circuit, an MOSFET switch circuit and a locking judgment processing circuit, wherein,
the current detection amplifying circuit detects the currents of a plurality of paths of secondary power supplies, converts each path of current into a weak voltage value respectively, and outputs the weak voltage value after amplification;
the ADC acquisition circuit acquires a plurality of paths of analog voltage values output by the current detection amplifying circuit, converts each path of analog voltage value into a corresponding digital signal respectively and sends the digital signal to the locking judgment processing circuit;
the locking judgment processing circuit judges whether the circuit is locked by single particles or not according to each path of digital signal and correspondingly outputs an MOSFET enabling control signal to the MOSFET switch circuit;
the MOSFET switch circuit controls the on-off of a secondary power supply according to the MOSFET enabling control signal, so that the function of anti-single event locking is realized;
the locking judgment processing circuit averages the digital signals, and compares the average value with a single event locking current threshold value under a corresponding working mode: if the average value is smaller than the single event locking current threshold value, judging that the circuit does not generate the single event locking phenomenon, wherein the MOSFET enabling control signal output by the locking judgment processing circuit is at a low level; if the average value is larger than the single event locking current threshold value and the duration time exceeds the current threshold value time, judging that the circuit has a single event locking phenomenon, wherein the MOSFET enabling control signal output by the locking judgment processing circuit is at a high level so as to turn off the secondary power supply output, and the MOSFET enabling control signal output after a certain time is at a low level so as to realize the anti-single event locking recovery function;
the locking judgment processing circuit comprises a microprocessor chip D2; wherein the content of the first and second substances,
an enabling signal 1 pin of an ADC acquisition chip D1 of the ADC acquisition circuit is connected to the output end of the microprocessor chip D2;
a control signal pin 14 of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2;
a clock signal 16 pin of the ADC acquisition chip D1 is connected to the output end of the microprocessor chip D2;
an output signal 15 pin of the ADC acquisition chip D1 is connected to the input end of the microprocessor chip D2;
a plurality of paths of MOSFET enabling control signal marks of the microprocessor chip D2 are output to corresponding single machine telemetering processing modules;
and the MOSFET enabling control signals of the microprocessor chip D2 are respectively connected to the MOSFET switch circuit.
2. The star-loaded single event latchup detection recovery circuit according to claim 1, wherein the current detection amplifying circuit comprises a precision sampling resistor RC1, voltage dividing resistors R1, R2, R3, R4, filter capacitors C1, C2, protection resistors R10, R12, a diode V2 and an amplifier A1,
the precision sampling resistor RC1 is connected between the secondary power supply input end and the MOSFET switching circuit in series, and the precision sampling resistor RC1 converts the current value flowing through the precision sampling resistor RC1 into a voltage value;
two ends of the divider resistor R1 are respectively connected with the 4 end of the precision sampling resistor RC1 and the non-inverting input end of the amplifier A1;
two ends of the divider resistor R2 are respectively connected with the non-inverting input end of the amplifier A1 and the GND;
two ends of the divider resistor R3 are respectively connected with the end 3 of the precision sampling resistor RC1 and the inverting input end of the amplifier A1;
two ends of the divider resistor R4 are respectively connected with the inverting input end of the amplifier A1 and the output end of the amplifier A1;
two ends of the filter capacitor C1 are respectively connected with the non-inverting input end of the amplifier A1 and the GND;
two ends of the filter capacitor C2 are respectively connected with the inverting input end of the amplifier A1 and the GND;
two ends of the protective resistor R10 are respectively connected with the output end of the amplifier A1 and the negative end of the diode V2;
the two ends of the protective resistor R12 are respectively connected with the negative end of the diode V2 and GND;
the positive end of the diode V2 is connected with GND.
3. The on-board single-event-lock detection recovery circuit of claim 2, wherein the amplifier A1 is selected from OP400AY/QMLV.
4. The satellite-borne single-event-lock detection recovery circuit according to claim 1, wherein the ADC acquisition circuit comprises the ADC acquisition chip D1, configuration resistors R13, R14, R15 and R16, and filter capacitors C100, C101, C102 and C103, wherein,
the plurality of paths of voltages output by the current detection amplifying circuit are respectively connected to any different pins IN the IN 0-IN 7 ends of the ADC acquisition chip D1;
the pin 1 of the enabling signal of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R14;
a control signal 14 pin of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R16;
a clock signal 16 pin of the ADC acquisition chip D1 is connected to the locking judgment processing circuit through the resistor R15;
the pin 15 of the output signal of the ADC acquisition chip D1 is connected to the locking judgment processing circuit;
a VA end 2 pin of the ADC acquisition chip D1 is connected to 5V voltage;
one end of each of the filter capacitors C102 and C103 is connected to a pin 2 of the ADC acquisition chip D1, and the other end of each of the filter capacitors is connected to the ground;
a VD end 13 pin of the ADC acquisition chip D1 is connected to a 5V voltage through a resistor R13;
one end of each of the filter capacitors C100 and C101 is connected to pin 13 of the ADC acquisition chip D1, and the other end is connected to ground.
5. The on-board single-event-lock detection recovery circuit of claim 4, wherein the ADC acquisition chip D1 is ADC128S102WGRQV.
6. The spaceborne single-event-lock detection recovery circuit according to claim 1, wherein the microprocessor chip D2 is an FPGA product having single-event resistance and radiation resistance.
7. The on-board single event latchup detection recovery circuit according to claim 1, wherein the MOSFET switching circuit comprises a current limiting resistor R20, protection resistors R21, R22, filter capacitors C9, C10 and a MOSFET V1, wherein,
two ends of the protective resistor R21 are respectively connected to a pin 3 and a pin 1 of the MOSFET V1;
two ends of the filter capacitor C10 are respectively connected to a pin 3 and a pin 2 of the MOSFET V1;
two ends of the protective resistor R20 are respectively connected to a pin 2 of the MOSFET V1 and an MOSFET enabling control signal output end of the microprocessor chip D2;
two ends of the filter capacitor C9 are respectively connected to a pin 2 of the MOSFET V1 and GND;
two ends of the protective resistor R22 are respectively connected to a pin 2 and GND of the MOSFET V1;
the secondary power supply output by the current detection amplifying circuit 1 is connected to the pin 3 of the MOSFET V1 and is output by the pin 1 of the MOSFET V1.
8. The spaceborne single-event-lock detection recovery circuit according to claim 7, wherein the MOSFET tube V1 is an IRL5NJ 7404P channel MOSFET tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910815543.1A CN110426551B (en) | 2019-08-30 | 2019-08-30 | Satellite-borne single-particle locking detection recovery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910815543.1A CN110426551B (en) | 2019-08-30 | 2019-08-30 | Satellite-borne single-particle locking detection recovery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110426551A CN110426551A (en) | 2019-11-08 |
| CN110426551B true CN110426551B (en) | 2023-01-20 |
Family
ID=68416802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910815543.1A Active CN110426551B (en) | 2019-08-30 | 2019-08-30 | Satellite-borne single-particle locking detection recovery circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110426551B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111679937B (en) * | 2020-06-01 | 2023-02-24 | 西安微电子技术研究所 | Single event lock release method based on local potential collapse |
| CN112986797A (en) * | 2021-02-08 | 2021-06-18 | 昂宝电子（上海）有限公司 | Chip test circuit and method |
| CN113037082A (en) * | 2021-03-10 | 2021-06-25 | 上海航天测控通信研究所 | Satellite-borne current sampling control power supply device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471562A (en) * | 2007-12-28 | 2009-07-01 | 中国航天科技集团公司第五研究院第五一〇研究所 | Protective circuit for locking single particle |
| CN101505093A (en) * | 2009-03-09 | 2009-08-12 | 哈尔滨工业大学 | Multipath output electrical power suitable for space environment |
| CN103474951A (en) * | 2013-08-28 | 2013-12-25 | 北京空间飞行器总体设计部 | Low drop-out overcurrent protection circuit with controllable output |
| CN103701087A (en) * | 2013-11-28 | 2014-04-02 | 兰州空间技术物理研究所 | On-track monitoring method for space single event latchup effect |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060119410A1 (en) * | 2004-12-06 | 2006-06-08 | Honeywell International Inc. | Pulse-rejecting circuit for suppressing single-event transients |
| CN102332311B (en) * | 2011-10-18 | 2013-10-02 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
-
2019
- 2019-08-30 CN CN201910815543.1A patent/CN110426551B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471562A (en) * | 2007-12-28 | 2009-07-01 | 中国航天科技集团公司第五研究院第五一〇研究所 | Protective circuit for locking single particle |
| CN101505093A (en) * | 2009-03-09 | 2009-08-12 | 哈尔滨工业大学 | Multipath output electrical power suitable for space environment |
| CN103474951A (en) * | 2013-08-28 | 2013-12-25 | 北京空间飞行器总体设计部 | Low drop-out overcurrent protection circuit with controllable output |
| CN103701087A (en) * | 2013-11-28 | 2014-04-02 | 兰州空间技术物理研究所 | On-track monitoring method for space single event latchup effect |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110426551A (en) | 2019-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110426551B (en) | Satellite-borne single-particle locking detection recovery circuit | |
| US8928307B2 (en) | Signal detection circuit, method and system | |
| US7821333B2 (en) | High-voltage differential amplifier and method using low voltage amplifier and dynamic voltage selection | |
| US7705573B2 (en) | Constant voltage circuit | |
| US10840960B1 (en) | Demodulator/detector for digital isolators | |
| TWI425772B (en) | Envelope detetor and associated method | |
| US10840861B1 (en) | Receiver intermediate variable gain stage for isolator products | |
| US10564186B2 (en) | Current sense amplifier architecture and level shifter | |
| CN105548672B (en) | Overcurrent detection circuit of power switch | |
| US10942217B2 (en) | Calibration of digital isolators | |
| CN112311406B (en) | Receiver front-end and method for receiving signals | |
| CN109343644A (en) | A kind of automatic adjustment current-limiting protection circuit | |
| US6842063B2 (en) | Analog switch circuit | |
| CN115733116A (en) | Overcurrent protection circuit | |
| EP1545029B1 (en) | Optical receiving device | |
| CN208257378U (en) | A kind of multiple-channel output low voltage difference overcurrent protector | |
| CN106104951A (en) | Protection circuit | |
| CN100472637C (en) | Digitizer | |
| CN108376967A (en) | A kind of multiple-channel output low voltage difference overcurrent protector | |
| CN107846285A (en) | A kind of current-limiting circuit and the electric power system for including it | |
| CN104660229A (en) | PWM modulation device and output power limiting circuit thereof | |
| CN112134257B (en) | DC power supply short-circuit protection circuit | |
| CN111198310B (en) | Data transmission link fault monitoring technology based on alternating current coupling LVDS standard | |
| US9093961B2 (en) | Operational amplifier | |
| US11218123B2 (en) | Chopper stabilized attenuation for sense amplifiers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |