CN112986797A - Chip test circuit and method - Google Patents
Chip test circuit and method Download PDFInfo
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- CN112986797A CN112986797A CN202110179071.2A CN202110179071A CN112986797A CN 112986797 A CN112986797 A CN 112986797A CN 202110179071 A CN202110179071 A CN 202110179071A CN 112986797 A CN112986797 A CN 112986797A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
A chip test circuit and method are provided. The chip test circuit includes: the chip testing device comprises a mode judging module, a test module and a control module, wherein the mode judging module is configured to judge whether to enable a chip to enter a specific test mode or not based on a port signal at a specific port of the chip and generate a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result; and the mode latch module is configured to generate a mode latch signal by sampling and latching the mode enable signal so as to control the chip to enter a specific test mode or a normal working mode before powering down based on the mode latch signal. Here, since the mode latch signal is used to control the chip to enter the specific test mode or the normal operation mode and then to be in the specific test mode or the normal operation mode before powering down, the abnormal operation of the chip and even the explosion of the chip caused by the chip entering the specific test mode by mistake when the chip is in the normal operation mode can be avoided.
Description
Technical Field
The invention relates to the field of circuits, in particular to a chip test circuit and a chip test method.
Background
Due to the process and packaging, various characteristic parameters in the chip are often shifted. Therefore, the parameters of the offset generated in the chip need to be debugged or screened out through testing so as to ensure that the chip can meet the specification requirements of products. Most parameters in the chip cannot be directly measured, and the purpose of measuring the parameters is realized by leading the chip into one or more test modes in sequence and leading one or more parameters in the chip out of the chip through a certain port of the chip.
Generally, it is required that a test circuit within a chip (hereinafter referred to as a chip test circuit) cannot affect normal use of the chip and cannot affect performance of other circuits within the chip. The chip test circuit can judge whether to enable the chip to enter a test mode or not based on a port signal at a specific port of the chip, and can lead out the parameters in the chip to the outside of the chip for measurement through another port of the chip after the chip enters the test mode. For a conventional chip test circuit, its input and output ports are two different ports of the chip, respectively, and its input port is required to be a high-impedance output port of the chip. When the chip is in a normal working mode, an input port of a traditional chip testing circuit may be interfered, so that the chip enters the testing mode by mistake, and the chip works abnormally and even the chip explodes. On the other hand, for a chip with relatively few ports, for example, a chip with only a power supply, a ground and an output port, the conventional chip test circuit cannot realize a test function. Meanwhile, a chip with fewer ports usually has only one port serving as an output port of a chip test circuit, and at this time, the chip also needs to sequentially enter multiple test modes to lead out multiple parameters in the chip to the outside of the chip for measurement.
Disclosure of Invention
In view of one or more of the problems described above, a chip test circuit and method, and a chip including the chip test circuit according to embodiments of the present invention are provided.
The chip test circuit according to the embodiment of the invention comprises: the chip testing device comprises a mode judging module, a test module and a control module, wherein the mode judging module is configured to judge whether to enable a chip to enter a specific test mode or not based on a port signal at a specific port of the chip and generate a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result; and the mode latch module is configured to generate a mode latch signal by sampling and latching the mode enable signal so as to control the chip to enter a specific test mode or a normal working mode before powering down based on the mode latch signal.
The chip testing method according to the embodiment of the invention comprises the following steps: judging whether to enable the chip to enter a specific test mode or not based on a port signal at a specific port of the chip, and generating a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result; and generating a mode latch signal by sampling and latching the mode enable signal, so as to control the chip to enter a specific test mode or a normal working mode before powering down based on the mode latch signal.
The chip testing circuit and the chip testing method can accurately judge whether the chip enters the specific testing mode or not, and can enable the chip to be in the specific testing mode or the normal working mode all the time after entering the specific testing mode or the normal working mode based on the judgment result before powering off, so that the chip working abnormity and even the explosion caused by the chip mistakenly entering the specific testing mode when being in the normal working mode can be avoided.
The chip according to the embodiment of the invention comprises one or more chip test circuits, wherein the one or more chip test circuits respectively correspond to different test modes, and the chip enters and always stays in the test mode or the normal working mode corresponding to the chip test circuit only under the control of one chip test circuit in the one or more chip test circuits at the same time.
The chip according to the embodiment of the invention can enter the test mode or the normal working mode corresponding to the chip test circuit under the control of any one of the one or more chip test circuits and is always in the test mode or the normal working mode before power-off, so that the chip can be prevented from mistakenly entering the test mode or other test modes when being in the normal working mode to cause abnormal chip working and even machine explosion.
Drawings
The invention may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a schematic block diagram of a chip test circuit according to an embodiment of the invention.
FIG. 2 illustrates an example circuit implementation of the chip test circuit shown in FIG. 1.
Fig. 3 shows a timing diagram of a plurality of signals associated with the chip test circuit shown in fig. 2.
FIG. 4 illustrates a functional diagram of a single-port multi-test mode implemented using a plurality of the chip test circuits shown in FIG. 1.
FIG. 5 illustrates a functional diagram of a multi-port, multi-test mode implemented using a plurality of the chip test circuits shown in FIG. 1.
FIG. 6 shows a flow chart of a chip testing method according to an embodiment of the invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but rather covers any modification, replacement or improvement of elements, components or algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.
In view of one or more problems with conventional chip test circuits, chip test circuits and methods according to embodiments of the present invention are presented. The following describes a chip test circuit and method according to an embodiment of the present invention in detail with reference to the accompanying drawings.
FIG. 1 shows a schematic block diagram of a chip test circuit 100 according to an embodiment of the invention. As shown in fig. 1, the chip test circuit 100 includes a mode determining module 102 and a mode latch module 104, wherein: the mode judging module 102 is configured to judge whether to make the chip enter a specific test mode based on a port signal at a specific port of the chip, and generate a mode enabling signal for enabling the chip to enter the specific test mode or a normal operating mode based on a judgment result; the mode latch module 104 is configured to generate a mode latch signal by sampling and latching a mode enable signal to control the chip to enter into a specific test mode or a normal operation mode until powered down based on the mode latch signal.
Here, it should be noted that the mode determining module 102 may generate a mode enable signal for enabling the chip to enter the specific test mode when determining to make the chip enter the specific test mode, and generate a mode enable signal for enabling the chip to enter the normal operation mode when determining not to make the chip enter the specific test mode. For example, the mode determination module 102 may generate a high level mode enable signal to enable the chip to enter a specific test mode, or may generate a low level mode enable signal to enable the chip to enter a normal operation mode.
The chip test circuit 100 according to the embodiment of the invention can accurately judge whether the chip enters the specific test mode or not, and can enable the chip to be in the specific test mode or the normal working mode all the time after entering the specific test mode or the normal working mode based on the judgment result and before powering off, thereby avoiding the chip working abnormity and even the explosion caused by the chip mistakenly entering the specific test mode when the chip is in the normal working mode.
In some embodiments, the chip test circuit 100 according to the embodiment of the present invention may further include a circuit start module 106 configured to generate circuit start signals for starting the mode determining module 102 and the mode latch module 104, and generate a first delay signal by delaying the circuit start signals, wherein the mode latch module 104 may sample and latch the mode enable signal based on the first delay signal. Here, the delay of the first delay signal with respect to the circuit start signal may be set to be short, so that the mode latch module 104 can generate the mode latch signal by sampling and latching the mode enable signal as soon as possible after the mode determination module 102 generates the mode enable signal, so that the mode latch module 104 can lock the state of the chip (i.e., lock the chip in a specific test mode or a normal operation mode) as soon as possible.
In some embodiments, the circuit start module 106 may be further configured to generate a second delay signal by delaying the circuit start signal as a determination stop signal for controlling the mode determination module 102 to stop determining whether to make the chip enter the specific test mode. By controlling the mode determining module 102 to stop determining whether to enter the chip into the specific test mode, the power consumption of the chip test circuit 100 can be reduced, thereby reducing the overall power consumption of the chip.
In some embodiments, the delay of the second delayed signal relative to the circuit activation signal may be longer than the delay of the first delayed signal relative to the circuit activation signal. In this way, it can be ensured that the mode determining module 102 stops generating the mode enable signal after the mode latch module 104 generates the mode latch signal by sampling and latching the mode enable signal, so that the overall power consumption of the chip can be reduced while ensuring that no influence is caused on other circuits of the chip.
In some embodiments, as shown in fig. 1, the circuit enable block 106 generates circuit enable signals for enabling the mode decision block 102 and the mode latch block 104 (e.g., based on a chip enable signal), and generates the first delay signal and the second delay signal by delaying the circuit enable signals. After the chip is started, the mode determining module 102 samples a port signal at a specific port of the chip, and determines whether to enter a specific test mode based on the port signal. When the port signal satisfies a predetermined condition, the mode determination module 102 generates a mode enable signal for enabling the chip to enter a specific test mode. When the port signal does not satisfy the predetermined condition, the mode determining module 102 generates a mode enable signal for enabling the chip to enter the normal operating mode. The predetermined condition here may be a parameter determination condition such as voltage, current, voltage-current change rate, or time. The mode latch module 104 samples and latches the mode enable signal based on the first delay signal to generate a mode latch signal, and controls the chip to enter and be always in a specific test mode or a normal operation mode based on the mode latch signal. The mode determination module 102 stops determining whether to enter the chip into a specific test mode (i.e., stops operating) based on the second delay signal.
Here, once the mode latch module 104 generates the mode latch signal, the mode latch signal is no longer affected by the mode determining module 102, and the mode latch signal can be erased only when the chip is off, so that the chip can be prevented from entering the specific test mode by mistake when the chip is in the normal operation mode. In addition, after the mode determination module 102 stops determining whether to make the chip enter the specific test mode, the port of the chip that serves as the input port of the chip test circuit 100 (i.e., the specific port that provides the mode determination module 102 with the port signal for determining whether to make the chip enter the specific test mode) may also serve as the output port of the chip test circuit 100, thereby realizing multiplexing of the above-mentioned port of the chip in the specific test mode.
FIG. 2 illustrates an example circuit implementation of the chip test circuit shown in FIG. 1. Fig. 3 shows a timing diagram of a plurality of signals associated with the chip test circuit shown in fig. 2. The operation of the chip test circuit shown in fig. 2 will be described with reference to fig. 2 and 3.
In fig. 2, EN is a circuit enable signal, EN _ delay1 is a first delay signal, and EN _ delay2 is a second delay signal.
As shown in fig. 2, the mode determining module 102 determines whether to enter a chip into a specific test mode by determining whether a port signal at a specific port of the chip satisfies a predetermined condition. In this example, the mode determining module 102 includes an inverter, an and gate, and a comparator, and the port signal is a voltage signal. The inverter inverts the second delay signal EN _ delay2, and the and gate generates a determination enable signal for enabling the comparator based on the circuit enable signal EN and the inverted second delay signal. When the port signal is larger than the reference voltage Vref, the chip is enabled to enter a specific test mode, and the comparator outputs a mode enable signal with a high level. When the port signal is not greater than the reference voltage Vref, indicating that the chip is not to enter a specific test mode, the comparator outputs a mode enable signal of a low level.
Further, as shown in fig. 2, the mode latch module 104 samples and latches the mode enable signal output by the mode determination module 102 to generate a mode latch signal. In the present example, the mode latch module 104 is implemented as a latch, and samples the mode enable signal when the first delay signal EN _ delay1 changes from a low level to a high level, and maintains a latched state when the first delay signal EN _ delay is at a high level. When the mode latch signal is high, the chip enters a special test mode. When the mode latch signal is at low level, the chip enters a normal working state.
Further, as shown in fig. 2, the circuit enable module 106 generates the circuit enable signal EN and the first and second delay signals EN _ delay1 and EN _ delay 2. In some embodiments, the circuit enable signal EN may be an enable signal generated inside the chip after the chip is powered on or enabled, and the signal is high to indicate that each module of the chip is about to start operating. The first delay signal EN _ delay1 is used to control the mode latch module 104 to sample and latch the mode enable signal, and the second delay signal EN _ delay2 is used to control the module determination module 102 to determine whether to make the chip enter a specific test mode.
As shown in fig. 3, the circuit enable signal EN is low before the chip is powered on or enabled. The circuit enable signal EN becomes high when the power supply voltage of the chip is sufficiently high or after the chip is enabled. When the circuit enable signal EN changes from a low level to a high level, the mode determining block 102 and the mode latch block 104 start to operate. The mode determining module 102 samples a port signal at a specific port of the chip, generates a mode enable signal based on the port signal, and outputs the mode enable signal to the mode latch module 104. The mode latch module 104 samples the mode enable signal when the first delay signal EN _ delay1 changes from a low level to a high level. The mode latch module 104 samples the mode enable signal only at the rising edge of the first delay signal EN _ delay1, and otherwise maintains the latched state. The chip enters and locks in a specific test mode or a normal working mode under the control of the mode latch signal. When the mode latch signal is at a high level, the chip is in a specific test mode, and a parameter in the chip can be led out from one port of the chip, which is an output port of the chip test circuit 100, to the outside of the chip. When the mode latch signal is at low level, the chip is in normal operation mode. When the second delay signal EN _ delay2 changes from low level to high level, the mode determining module 102 is powered off, so that the mode determining module 102 does not increase the overall power consumption of the chip and affect other circuits of the chip.
FIG. 4 illustrates a functional diagram of a single-port multi-test mode implemented using a plurality of the chip test circuits shown in FIG. 1. Here, it is assumed that the chip includes chip test circuits 100-1 to 100-3 connected in parallel to one specific port of the chip, the three chip test circuits correspond to different test modes, respectively, and the chip enters and is always in a test mode or a normal operation mode corresponding to a chip test circuit only under the control of one of the three chip test circuits at the same time.
As shown in FIG. 4, the chip test circuits 100-1 to 100-3 respectively include the mode decision modules 102-1 to 102-3 and the mode locking modules 104-1 to 104-3, but share the same circuit start-up module 106. After the chip starts to work, the mode judging modules 102-1 to 102-3 respectively sample port signals on a specific port of the chip and judge whether to enable the chip to enter a corresponding test mode or not based on the port signals. Specifically, when the port signal satisfies the predetermined condition 1, the mode enable signal 1 generated by the mode determining module 102-1 is at a high level, and the chip enters the test mode 1; when the port signal meets the preset condition 2, the mode enabling signal 2 generated by the mode judging module 102-2 is at a high level, and the chip enters a test mode 2; when the port signal satisfies the predetermined condition 3, the mode enable signal 3 generated by the mode determining module 102-3 is at a high level, and the chip enters the test mode 3. The predetermined condition here may be a parameter judgment condition such as voltage, current, voltage-current change rate, or time, and there may be a case where the port signal satisfies two or more of the predetermined conditions 1 to 3 at the same time. The circuit start block 106 controls the mode latch blocks 104-1 to 104-3, and samples and latches the mode enable signals 1 to 3 after the circuit start signal is valid for a period of time, so that the chip is always in a latched state. The state of the mode latch blocks 104-1 to 104-3, once latched, is not affected by the mode decision block 102 and can only be erased by power-down of the chip. A plurality of test modes can be realized through one port of the chip, so that a plurality of parameters in the chip can be output to the outside of the chip through fewer ports for measurement.
FIG. 5 illustrates a functional diagram of a multi-port, multi-test mode implemented using a plurality of the chip test circuits shown in FIG. 1. Here, it is assumed that the chip includes chip test circuits 100-1 to 100-3 respectively connected to ports 1 to 3 of the chip, the three chip test circuits respectively correspond to different test modes, and the chip enters and always stays in a test mode or a normal operation mode corresponding to a chip test circuit only under the control of a certain chip test circuit among the three chip test circuits at the same time.
As shown in FIG. 5, the chip test circuits 100-1 to 100-3 respectively include the mode decision modules 102-1 to 102-3 and the mode locking modules 104-1 to 104-3, but share the same circuit start-up module 106. After the chip starts to work, the mode judging modules 102-1 to 102-3 respectively sample port signals 1 to 3 on the ports 1 to 3 of the chip, and judge whether the chip needs to enter a corresponding test mode based on the port signals 1 to 3. Specifically, when the port signal 1 meets the predetermined condition 1, the mode enable signal 1 generated by the mode determining module 102-1 is at a high level, and the chip enters the test mode 1; when the port signal 2 meets the preset condition 2, the mode enabling signal 2 generated by the mode judging module 102-2 is at a high level, and the chip enters a test mode 2; when the port signal 3 satisfies the predetermined condition 3, the mode enable signal 3 generated by the mode determining module 102-3 is at a high level, and the chip enters the test mode 3. The predetermined conditions 1 to 3 here may be parameter judgment conditions such as voltage, current, voltage-current change rate, or time, and there may be a case where two or more of the port signals 1 to 3 satisfy respective two or more of the predetermined conditions 1 to 3 at the same time. After the circuit enable signal is asserted for a period of time, the mode latch modules 104-1 to 104-3 respectively sample and latch the corresponding mode enable signal, so that the chip is always in a latched state. Once the state of the mode latch modules 104-1 to 104-3 is latched, the latched state can be erased only by the power-down of the chip without being affected by the mode decision modules 102-1 to 102-3. Multiple test modes can be realized through multiple ports of the chip, so that multiple parameters in the chip can be led out to the outside of the chip for measurement.
In summary, the chip test circuit 100 according to the embodiment of the invention realizes a chip test method 600. FIG. 6 shows a flow diagram of a chip testing method 600 according to an embodiment of the invention. As shown in fig. 6, the chip testing method 600 may include: s602, judging whether to enable the chip to enter a specific test mode or not based on a port signal at a specific port of the chip, and generating a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result; and S604, generating a mode latch signal by sampling and latching the mode enable signal, so as to control the chip to enter a specific test mode or a normal working mode before powering down based on the mode latch signal.
In some embodiments, the chip testing method 600 may further include: s606, after sampling and latching the mode enable signal, stops generating the mode enable signal.
It should be noted here that the chip test method 600 can be implemented by the chip test circuit 100, and other details and advantages related to the chip test method can be found in the related description of the chip test circuit 100.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. A chip test circuit, comprising:
the chip testing device comprises a mode judging module, a test module and a control module, wherein the mode judging module is configured to judge whether a chip needs to enter a specific test mode or not based on a port signal at a specific port of the chip and generate a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result;
a mode latch module configured to generate a mode latch signal by sampling and latching the mode enable signal to control the chip to enter into the specific test mode or the normal operation mode until power is down based on the mode latch signal.
2. The chip test circuit of claim 1, further comprising:
a circuit start-up module configured to generate a circuit start-up signal for starting up the mode judgment module and the mode latch module, and generate a first delay signal by delaying the circuit start-up signal, wherein
The mode latch module samples and latches the mode enable signal based on the first delay signal.
3. The chip test circuit according to claim 2, wherein the circuit start module is further configured to generate a second delay signal by delaying the circuit start signal as a determination stop signal for controlling the mode determination module to stop determining whether to cause the chip to enter the specific test mode.
4. The chip test circuit of claim 3, wherein the second delay signal is delayed relative to the circuit enable signal by a longer delay than the first delay signal.
5. The chip test circuit according to claim 1, wherein the mode determination module determines whether to enter the chip into the specific test mode by comparing the port signal with a predetermined threshold when the port signal is a voltage signal.
6. A chip comprising one or more chip test circuits according to any one of claims 1 to 5, wherein the one or more chip test circuits correspond to different test modes respectively, and the chip enters and always stays in the test mode or normal operation mode corresponding to one of the one or more chip test circuits only under the control of the chip test circuit at the same time.
7. The chip of claim 6, wherein inputs of the one or more chip test circuits are connected in parallel to a same port of the chip.
8. The chip of claim 6, wherein inputs of the one or more chip test circuits are respectively connected to different ports of the chip.
9. A method of chip testing, comprising:
judging whether to enable the chip to enter a specific test mode or not based on a port signal at a specific port of the chip, and generating a mode enabling signal for enabling the chip to enter the specific test mode or a normal working mode based on a judgment result; and
generating a mode latch signal by sampling and latching the mode enable signal to control the chip to enter the specific test mode or the normal operation mode until powering down based on the mode latch signal.
10. The chip test method as claimed in claim 9, wherein the generation of the mode enable signal is stopped after sampling and latching the mode enable signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110179071.2A CN112986797A (en) | 2021-02-08 | 2021-02-08 | Chip test circuit and method |
| TW110115939A TWI774352B (en) | 2021-02-08 | 2021-05-03 | Wafer test circuit and method |
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| CN202110179071.2A CN112986797A (en) | 2021-02-08 | 2021-02-08 | Chip test circuit and method |
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| Publication number | Publication date |
|---|---|
| TWI774352B (en) | 2022-08-11 |
| TW202232117A (en) | 2022-08-16 |
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