CN113595529B - Bias potential transient compensation circuit of power amplifier - Google Patents
Bias potential transient compensation circuit of power amplifier Download PDFInfo
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- CN113595529B CN113595529B CN202110925352.8A CN202110925352A CN113595529B CN 113595529 B CN113595529 B CN 113595529B CN 202110925352 A CN202110925352 A CN 202110925352A CN 113595529 B CN113595529 B CN 113595529B
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- 238000005513 bias potential Methods 0.000 title claims abstract description 11
- 230000001052 transient effect Effects 0.000 title claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 104
- 238000000034 method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract 1
- 230000000630 rising effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a bias potential transient compensation circuit technology of a power amplifier, which comprises a narrow pulse generator, wherein a first switch transistor is arranged at the output end of the narrow pulse generator, a buffer is arranged at the output end of the first switch transistor, a second switch transistor is arranged at the output end of the buffer, a driver is arranged at the output end of the second switch transistor, a first capacitor, a second capacitor and a third capacitor are arranged at the output end of the first switch transistor, and the first capacitor is electrically connected with the first switch transistor. Compared with the common exponential decay type compensation signal in the industry, the circuit structure of the invention generates a triangular wave overshoot compensation signal which linearly changes along with time, the compensation effect on the EVM performance is better in the delta t period, the continuous time length parameter of the compensation signal is less sensitive to the fluctuation of factors such as process, temperature, voltage and the like, and the mass production stability of the EVM performance in the delta t period is better.
Description
Technical Field
The invention relates to the technical field of power amplifiers, in particular to a bias potential transient compensation circuit of a power amplifier.
Background
In a communication system of a Time Division Duplex (TDD) mode, a bias potential of an input amplifying tube of the power amplifier is required to be continuously and rapidly switched between an establishment state and a closing state along with a TDD switching signal so as to save the power consumption of the whole transmitting link, when the input bias potential of the power amplifier is rapidly established from 0V to a potential value in a stable working state, the working point and the output performance of the power amplifier cannot reach a stable working value immediately, but can reach a steady state only after a certain delay delta t (generally about 100us magnitude), so that the dynamic EVM performance of the transmitting system is poor in a delta t period;
in order to solve this problem, the prior art solution is generally that, when the TDD enable signal comes, a time domain overshoot compensation signal is generated inside the chip, so that the gate bias potential of the input amplifying tube of the power amplifier is slightly higher than the steady state value in the normal working state in the Δt period, thereby improving the dynamic EVM performance in the Δt period to a certain extent, and the domain overshoot compensation signal is generally implemented by the charge pump+rc discharge principle.
The prior art has the following defects:
1. the RC discharge time determines the up-rush compensation duration, and the up-rush compensation duration fluctuates greatly along with factors such as process, temperature, voltage and the like, so that the fluctuation dispersion of the compensation signal duration index is large, and the dynamic EVM performance of a certain number of chips in actual mass production at the TDD switching moment cannot be compensated to be within a target range;
2. the RC discharge curve has an exponential characteristic, and compared with the linear discharge characteristic, the dynamic EVM performance compensation effect on the TDD switching moment is relatively poor.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, an embodiment of the present invention provides a bias potential transient compensation circuit for a power amplifier, which can generate a triangular wave overshoot compensation signal that varies linearly with time, so that the compensation effect on the EVM performance is better in the delta t period, and the duration parameter of the compensation signal is less sensitive to the fluctuation of factors such as process, temperature, voltage, etc., and the mass production stability of the EVM performance is good in the delta t period, so as to solve the problems set forth in the above-mentioned background art.
In order to achieve the above object, the present invention provides a power amplifier bias potential transient compensation circuit: the pulse generator comprises a narrow pulse generator, wherein a first switching transistor is arranged at the output end of the narrow pulse generator, a buffer is arranged at the output end of the first switching transistor, a second switching transistor is arranged at the output end of the buffer, and a driver is arranged at the output end of the second switching transistor.
In a preferred embodiment, the first switching transistor is electrically connected to the narrow pulse generator, the buffer is electrically connected to the first switching transistor, the second switching transistor is electrically connected to the buffer, the driver is electrically connected to the second switching transistor, and the ratio of the third capacitor to the second capacitor is equal to 1: and N, the serial structure of the first capacitor and the second capacitor is connected in parallel with the serial structure of the buffer and the second switch transistor, when the rising edge of the TDD control signal TDD comes, the narrow Pulse generating circuit generates a negative narrow Pulse signal Pulse for controlling the grid electrode of the first switch transistor, and the drain electrode of the first switch transistor is connected with the positive end of the current source, the upper polar plate of the first capacitor, the input end of the buffer (sub-circuit B) and the upper polar plate of the third capacitor.
In a preferred embodiment, the output end of the first switching transistor is provided with a first capacitor, a second capacitor and a third capacitor, the first capacitor is electrically connected with the first switching transistor, the input end of the narrow pulse generator is provided with a TDD control signal, the input end of the second switching transistor is provided with a VREF reference voltage, the output end of the driver is provided with a vref_comp output signal, a node V1 is arranged between the first switching transistor and the third capacitor, and a node V2 is arranged between the buffer and the second switching transistor.
In a preferred embodiment, the first capacitor, the second capacitor and the third capacitor are connected in series, and the ratio of the third capacitor to the second capacitor is equal to 1: n, the series structure of the first capacitor and the second capacitor is connected in parallel with the series structure of the buffer and the second switch transistor, a node V3 is arranged between the second switch transistor and the driver, the output of the buffer drives the grid electrode of the second switch transistor, the lower polar plate of the third capacitor and the upper polar plate of the second capacitor, the source end of the second switch transistor is connected with the input end of the driver (sub-circuit C), the drain end of the second switch transistor is connected with a reference voltage, and the lower polar plate of the second capacitor, the lower polar plate of the first capacitor and the N end of the current source are connected with the system ground potential.
In a preferred embodiment, the input end of the first capacitor is provided with a current source, the first capacitor is electrically connected with the current source, and the output ends of the first capacitor and the current source are grounded.
In a preferred embodiment, the input end of the first switching transistor is provided with a VDD power supply, the first switching transistor is electrically connected to the VDD power supply, and the input end of the narrow pulse generator is provided with a TDD control signal.
In a preferred embodiment, the input terminal of the second switching transistor is provided with a VREF reference voltage, the output terminal of the driver is provided with a vref_comp output signal, a node V1 is provided between the first switching transistor and the third capacitor, a node V2 is provided between the buffer and the second switching transistor, and a node V3 is provided between the second switching transistor and the driver.
In a preferred embodiment, the first capacitor is connected in parallel with the current source, the output terminal of the first capacitor is commonly grounded, the narrow pulse generator (sub-circuit a) outputs a negative narrow pulse signal at the time of rising edge of the TDD signal, the first switch transistor is controlled to be turned on during the duration of the narrow pulse, the equivalent capacitance of the series connection of the first capacitor, the second capacitor and the third capacitor is charged by the power supply VDD, the node V1 is rapidly pulled up to near VDD potential, the output potential of the buffer (sub-circuit B) is near VDD, the second switch transistor is in the off state, and the potential of the node V3 is rapidly pulled up from the steady state value (equal to VREF) to vref+vdd [ 1/(1+n) ].
In a preferred embodiment, the gate terminal of the first switching transistor is connected to the output terminal of the narrow pulse generator, the source terminal of the first switching transistor is connected to the power supply, the drain terminal of the first switching transistor is connected to the input terminal of the buffer and the input terminal of the third capacitor, when the rising edge of the narrow pulse signal comes, the first switching transistor is turned off, the charges stored on the serial equivalent capacitances of the first capacitor, the second capacitor and the third capacitor are discharged to GND by the current source, the discharge duration is [ c1+c2×c3/(c2+c3) ], VDD/I1, and the discharge waveform curves of the nodes V1 and V3 are in a linearly decreasing shape with time.
In a preferred embodiment, the gate terminal of the second switching transistor is electrically connected to the output terminal of the buffer, the source terminal of the second switching transistor is connected to the reference voltage, the drain terminal of the second switching transistor is connected to the input terminal of the second capacitor, the output terminal of the third capacitor and the input terminal of the driver, when the potential of the node V2 is reduced to the steady-state value (equal to VREF) along with the node V1 when the second switching transistor is turned on, the potential of the node V3 is reduced to its steady-state value (equal to VREF) until the next rising edge of the TDD signal comes, the above procedure is repeated, and the V3 signal is the desired waveform in the whole period and is output via the driver (sub-circuit C) to drive the input amplifying transistor gate of the power amplifier.
The invention has the technical effects and advantages that:
compared with the common exponential decay type compensation signal in the industry, the circuit structure of the invention generates a triangular wave overshoot compensation signal which linearly changes along with time, the compensation effect on the EVM performance is better in the delta t period, the continuous time length parameter of the compensation signal is less sensitive to the fluctuation of factors such as process, temperature, voltage and the like, and the mass production stability of the EVM performance in the delta t period is better.
Drawings
Fig. 1 is a schematic diagram of a circuit module according to the present invention.
Fig. 2 is a schematic circuit diagram of the present invention.
FIG. 3 is a schematic diagram of a node discharge waveform according to the present invention.
The reference numerals are: 1. a narrow pulse generator; 2. a buffer; 3. a driver; 4. a first switching transistor; 5. a second switching transistor; 6. a first capacitor; 7. a second capacitor; 8. a third capacitor; 9. a current source.
Schematic circuit diagram symbol:
a: narrow pulse generator
B: buffer device
C: driver(s)
Q1: first switching transistor
Q2: second switching transistor
C1: first capacitor
C2: second capacitor
And C3: third capacitor
I1: current source
V1\v2\v3: node
TDD: control signal
VDD: power supply
GND: grounded (earth)
Pulse: narrow pulse signal
VREF: reference voltage
Vref_comp: and outputting a signal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-3 of the specification, a bias potential transient compensation circuit of a power amplifier according to an embodiment of the present invention includes a narrow pulse generator 1, wherein an output end of the narrow pulse generator 1 is provided with a first switching transistor 4, an output end of the first switching transistor 4 is provided with a buffer 2, an output end of the buffer 2 is provided with a second switching transistor 5, an output end of the second switching transistor 5 is provided with a driver 3, the first switching transistor 4 is electrically connected with the narrow pulse generator 1, the buffer 2 is electrically connected with the first switching transistor 4, the second switching transistor 5 is electrically connected with the buffer 2, the driver 3 is electrically connected to the second switching transistor 5, and at the time of rising edge of the TDD signal, the narrow pulse generator 1 (sub-circuit a) outputs a negative narrow pulse signal, which controls the first switching transistor 4 to be turned on during the duration of the narrow pulse, the equivalent capacitance of the series connection of the first capacitor 6, the second capacitor 7 and the third capacitor 8 is charged by the power supply VDD, the node V1 is rapidly pulled up to approximately VDD, the output potential of the buffer 2 (sub-circuit B) is approximately VDD during this period, the second switching transistor 5 is in an off state, and the potential of the node V3 is rapidly pulled up from a steady state value (equal to VREF) to vref+vdd [ 1/(1+n) ].
Further, the output end of the first switching transistor 4 is provided with a first capacitor 6, a second capacitor 7 and a third capacitor 8, the first capacitor 6 is electrically connected with the first switching transistor 4, the first capacitor 6, the second capacitor 7 and the third capacitor 8 are connected in series, and the ratio of the third capacitor 8 to the second capacitor 7 is equal to 1: n, the series structure of the first capacitor 6 and the second capacitor 7 is connected in parallel with the series structure of the buffer 2 and the second switching transistor 5, when the rising edge of the TDD control signal TDD comes, the narrow Pulse generating circuit generates a negative narrow Pulse signal Pulse for controlling the gate of the first switching transistor 4, and the drain of the first switching transistor 4 is connected to the positive terminal of the current source 9, the upper plate of the first capacitor 6, the input terminal of the buffer 2 (sub-circuit B) and the upper plate of the third capacitor 8.
Further, the input end of the first capacitor 6 is provided with a current source 9, the first capacitor 6 is electrically connected with the current source 9, the output ends of the first capacitor 6 and the current source 9 are grounded, the input end of the first switch transistor 4 is provided with a VDD power supply, the first switch transistor 4 is electrically connected with the VDD power supply, the input end of the narrow pulse generator 1 is provided with a TDD control signal, the input end of the second switch transistor 5 is provided with a VREF reference voltage, the output end of the driver 3 is provided with a vref_comp output signal, a node V1 is arranged between the first switch transistor 4 and the third capacitor 8, a node V2 is arranged between the buffer 2 and the second switch transistor 5, a node V3 is arranged between the second switch transistor 5 and the driver 3, the output of the buffer 2 drives the gate electrode of the second switch transistor 5, the lower electrode plate of the third capacitor 8 and the upper electrode plate of the second capacitor 7, the source end of the second switch transistor 5 is connected with the input end of the driver 3 (sub-circuit C), and the drain electrode plate of the second switch transistor 5 is connected with the ground potential of the second capacitor 7, and the drain electrode of the second capacitor 6 is connected with the ground potential of the first capacitor system.
Further, the input end of the second switching transistor 5 is provided with a VREF reference voltage, the output end of the driver 3 is provided with a vref_comp output signal, a node V1 is provided between the first switching transistor 4 and the third capacitor 8, a node V2 is provided between the buffer 2 and the second switching transistor 5, and a node V3 is provided between the second switching transistor 5 and the driver 3.
Further, the first capacitor 6 is connected in parallel with the current source, the output end of the first capacitor 6 and the output end of the current source are commonly grounded, the gate end of the first switch transistor 4 is connected with the output end of the narrow pulse generator 1, the source end of the first switch transistor 4 is connected with a power supply, the drain end of the first switch transistor 4 is connected with the input end of the buffer 2 and the input end of the third capacitor 8, the gate end of the second switch transistor 5 is electrically connected with the output end of the buffer 2, the source end of the second switch transistor 5 is connected with a reference voltage, and the drain end of the second switch transistor 5 is connected with the input end of the second capacitor 7, the output end of the third capacitor 8 and the input end of the driver 3.
Working principle: at the rising edge of the TDD signal, the narrow pulse generator 1 (sub-circuit a) outputs a negative narrow pulse signal, controlling the first switching transistor 4 to be turned on during the duration of the narrow pulse, the equivalent capacitance of the series connection of the first capacitor 6, the second capacitor 7 and the third capacitor 8 being charged by the power supply VDD, the node V1 being rapidly pulled up to approach VDD potential, during which the output potential of the buffer 2 (sub-circuit B) approaches VDD, the second switching transistor 5 being in an off state, and the potential of the node V3 being rapidly pulled up from a steady state value (equal to VREF) to vref+vdd [ 1/(1+n) ];
when the rising edge of the narrow pulse signal comes, the first switching transistor 4 is turned off, the charges stored on the serial equivalent capacitances of the first capacitor 6, the second capacitor 7 and the third capacitor 8 are discharged to GND through the current source 9, the discharge duration is [ c1+c2×c3/(c2+c3) ]×vdd/I1, and the discharge waveform curves of the nodes V1 and V3 take a linearly decreasing shape with time;
when the potential of the node V2 decreases to the second switching transistor 5 to turn on along with the node V1, the potential of the node V3 also decreases to its steady-state value (equal to VREF) until the next rising edge of the TDD signal comes, and the above-mentioned process is repeated, and the V3 signal is in a desired waveform in the whole period, and the signal vref_comp is outputted via the driver 3 (sub-circuit C) for driving the gate of the input amplifying tube of the power amplifier.
The last points to be described are: first, in the description of the present application, it should be noted that, unless otherwise specified and defined, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be mechanical or electrical, or may be a direct connection between two elements, and "upper," "lower," "left," "right," etc. are merely used to indicate relative positional relationships, which may be changed when the absolute position of the object being described is changed;
secondly: in the drawings of the disclosed embodiments, only the structures related to the embodiments of the present disclosure are referred to, and other structures can refer to the common design, so that the same embodiment and different embodiments of the present disclosure can be combined with each other under the condition of no conflict;
finally: the foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (1)
1. A power amplifier bias potential transient compensation circuit, characterized by: the pulse generator comprises a narrow pulse generator (1), wherein a first switching transistor (4) is arranged at the output end of the narrow pulse generator (1), a buffer (2) is arranged at the output end of the first switching transistor (4), a second switching transistor (5) is arranged at the output end of the buffer (2), and a driver (3) is arranged at the output end of the second switching transistor (5);
the first switching transistor (4) is electrically connected with the narrow pulse generator (1), the buffer (2) is electrically connected with the first switching transistor (4), the second switching transistor (5) is electrically connected with the buffer (2), and the driver (3) is electrically connected with the second switching transistor (5);
the output end of the first switch transistor (4) is provided with a first capacitor (6), a second capacitor (7) and a third capacitor (8), and the first capacitor (6) is electrically connected with the first switch transistor (4);
the first capacitor (6), the second capacitor (7) and the third capacitor (8) are connected in series, and the ratio of the third capacitor (8) to the second capacitor (7) is equal to 1: n, the serial structure of the first capacitor (6) and the second capacitor (7) is connected in parallel with the serial structure of the buffer (2) and the second switch transistor (5);
the input end of the first capacitor (6) is provided with a current source (9), the first capacitor (6) is electrically connected with the current source (9), and the output ends of the first capacitor (6) and the current source (9) are grounded;
the input end of the first switching transistor (4) is provided with a VDD power supply, the first switching transistor (4) is electrically connected with the VDD power supply, and the input end of the narrow pulse generator (1) is provided with a TDD control signal;
the input end of the second switching transistor (5) is provided with VREF reference voltage, the output end of the driver (3) is provided with VREF_COMP output signals, a node V1 is arranged between the first switching transistor (4) and the third capacitor (8), a node V2 is arranged between the buffer (2) and the second switching transistor (5), and a node V3 is arranged between the second switching transistor (5) and the driver (3);
the first capacitor (6) is connected with the current source in parallel, and the output end of the first capacitor (6) and the output end of the current source are commonly grounded;
the gate end of the first switching transistor (4) is connected with the output end of the narrow pulse generator (1), the source end of the first switching transistor (4) is connected with a power supply, and the drain end of the first switching transistor (4) is connected with the input end of the buffer (2) and the input end of the third capacitor (8);
the gate end of the second switching transistor (5) is electrically connected with the output end of the buffer (2), the source end of the second switching transistor (5) is connected with a reference voltage, and the drain end of the second switching transistor (5) is connected with the input end of the second capacitor (7), the output end of the third capacitor (8) and the input end of the driver (3).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110925352.8A CN113595529B (en) | 2021-08-12 | 2021-08-12 | Bias potential transient compensation circuit of power amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110925352.8A CN113595529B (en) | 2021-08-12 | 2021-08-12 | Bias potential transient compensation circuit of power amplifier |
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| CN113595529A CN113595529A (en) | 2021-11-02 |
| CN113595529B true CN113595529B (en) | 2024-03-05 |
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| CN1905356A (en) * | 2005-07-28 | 2007-01-31 | 中兴通讯股份有限公司 | Low delay temp compensation bias circuit for TDD mode |
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| US20160056813A1 (en) * | 2013-03-15 | 2016-02-25 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Displacement current compensation circuit |
| US9825616B2 (en) * | 2013-03-15 | 2017-11-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Circuit for reducing slope magnitude during increasing and decreasing voltage transitions |
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