CN113593424A

CN113593424A - Splicing display panel and display device

Info

Publication number: CN113593424A
Application number: CN202110869487.7A
Authority: CN
Inventors: 胡道兵
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd; TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2021-11-02

Abstract

The application discloses concatenation display panel and display device, concatenation display panel sets up many connecting lead through the concatenation position at two adjacent sub-display panel, connecting lead is used for transmitting one of them sub-display panel's drive signal to another sub-display panel, omits the COF of concatenation department, can reduce driving cost, still realizes real seamless concatenation, has still solved simultaneously because the asynchronous demonstration problem that leads to of signal.

Description

Splicing display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a spliced display panel and a display device capable of realizing seamless splicing.

Background

With the higher demand of the high-level TV market for image quality, the improvement of display image quality becomes a new demand of the high-level TV. At present, 8K OLEDs are limited to the problems of compensation circuits, IGZO (Indium Gallium Zinc Oxide) backplane technology, driving design and the like, and need to be developed. The Mini LED/Micro-LED is a brand new display technology, has advantages in brightness and power consumption compared with Organic Light-Emitting diodes (OLEDs) and dual liquid crystal displays (dual Cell), and is currently a hot direction in the display field.

However, as the pixel Pitch (Pitch) of the Mini/Micro LEDs is made smaller, the requirement of the large-size tiled display device for the seamless tiling technology is more urgent. However, the conventional glass-based Mini/Micro LED needs to be connected to the Mini/Micro LED substrate via a Chip On Film (COF) by a Bonding process. Due to the fact that the pixel pitch is continuously reduced, the wiring space of the binding area or the splicing position of the Mini/Micro LED substrate is smaller and smaller until the limit is reached, wiring cannot be conducted, and further reduction of the pixel pitch is limited.

Moreover, in the process of splicing a plurality of small-size sub-display panels, if the distance between the splicing positions of the adjacent small-size sub-display panels is large, dark stripes are easily formed at the splicing positions, the display effect of the spliced large-size splicing panels is reduced, and the use experience of a user is influenced.

In addition, the IC and COF are required for a plurality of small-sized sub-display panels, which results in higher IC and COF usage, higher driving reduction, and display problems due to asynchronous driving signals.

Therefore, it is desirable to provide a tiled display panel and a display device to solve the above-mentioned problems.

Disclosure of Invention

In order to solve the technical problems, the application provides a tiled display panel and a display device, which can omit a COF at a tiled part and realize real seamless tiling; in addition, all the sub-display panels can synchronously drive signals, the display problem caused by asynchronous signals is solved, and the driving cost is reduced.

In order to achieve the above purpose, the tiled display panel and the display device described in the present application adopt the following technical solutions.

The application provides a tiled display panel, including a plurality of sub-display panel that splice together, every adjacent two be provided with many connecting leads in the sub-display panel, connecting leads is used for adjacent two transmit drive signal between the sub-display panel.

Optionally, in some embodiments, each of the sub-display panels includes a display area and a non-display area located on at least one side of the display area;

in two adjacent sub display panels, the non-display areas of the sub display panels are adjacently arranged;

and the connecting lead extends from the non-display area of one of the sub-display panels to the non-display area of the other sub-display panel.

Optionally, in some embodiments, a plurality of binding wires are disposed in the non-display area of each sub-display panel;

in two adjacent sub-display panels, the binding wires of one sub-display panel correspond to the binding wires of the other sub-display panel one to one;

each connecting lead is electrically connected with the corresponding two binding wires.

Optionally, in some embodiments, the binding traces extend vertically from an outer edge of the display area to an outer edge of the non-display area;

and the two corresponding binding wires are connected in a counterpoint mode at the splicing positions of the two adjacent sub-display panels.

Optionally, in some embodiments, a conductive adhesive is disposed between two adjacent sub display panels, and the conductive adhesive is used to connect two corresponding binding traces.

Optionally, in some embodiments, one end of the connecting lead is disposed on one of the two corresponding bonding wires, and the other end of the connecting lead is disposed on the other of the two corresponding bonding wires.

Optionally, in some embodiments, a line width of the connection lead is smaller than or equal to a line width of the bonding trace.

Optionally, in some embodiments, the material of the connecting lead is gold or silver.

Optionally, in some embodiments, the sub-display panel is a Mini-LED sub-display panel or a Micro-LED sub-display panel.

Correspondingly, the application also provides a display device which comprises the spliced display panel and the chip on film;

the chip on film is arranged on the periphery of the spliced display panel and bound on the side face of the sub display panel.

Compared with the prior art, this application concatenation display panel and display device sets up the connecting lead wire in two adjacent display panel through introducing, utilizes connecting lead wire to transmit drive signal between adjacent sub-display panel, can omit the COF that sets up between the adjacent sub-display panel, reduces the width of concatenation seam, realizes real seamless concatenation. Meanwhile, in the scheme of the application, only the COF can be bound at the outermost periphery of the whole spliced display panel, so that the use amount of ICs and COFs is saved, the driving cost is reduced, driving signals of all the sub display panels can be synchronized, and the display problem caused by asynchronous signals is avoided.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic plan view of a tiled display panel according to the present application.

Fig. 2 is a schematic plan view of a display device according to the present application.

Description of reference numerals:

200 chip on film for 100-tiled display panel

20 connecting lead 10 sub-display panel

110 display area 120 non-display area

11 binding wire 12 signal wire

13 light emitting device 111 first wire

112 second binding trace 21 first connecting lead

22 second connecting lead

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

Fig. 1 is a schematic plan view of a tiled display panel 100 according to the present application. As shown in fig. 1, the tiled display panel 100 of the present application includes a plurality of sub-display panels 10 tiled together. The tiled display panel 100 further includes connecting leads 20, and the connecting leads 20 are disposed in two adjacent sub-display panels 10 and used for transmitting driving signals between the two sub-display panels 10.

More specifically, a plurality of connecting leads 20 are disposed at the joint position of two adjacent sub-display panels 10, and the bonding wires 11 are used for transmitting the driving signal of one of the sub-display panels 10 to the other sub-display panel 10. That is, the driving signal of one sub display panel 10 can be transmitted to another adjacent sub display panel 10 through the connection lead 20. Therefore, the flip-chip film 200 is not required to be arranged between the two sub-display panels 10 which are spliced with each other, and the normal display of each sub-display panel 10 is not affected.

Therefore, in the present embodiment, the connection leads 20 disposed in two adjacent sub-display panels 10 are used to transmit the driving signal of one sub-display panel 10 to another adjacent sub-display panel 10, so that the flip chip 200 that should be disposed at the joint position can be omitted. Furthermore, the tiled display panel 100 of the present application, on one hand, reduces the tiling gap between two adjacent sub-display panels 10, and realizes real seamless tiling, thereby overcoming the limitation of the larger tiling gap or binding area to the pixel pitch; on the other hand, the driving structure can be arranged only at the outermost periphery, so that the use amount of ICs and COFs is reduced, the driving cost is reduced, and meanwhile, the driving signals of the plurality of sub-display panels 10 are synchronized, so that the problem of display asynchronization can be avoided.

As shown in fig. 1, the tiled display panel 100 includes a plurality of sub-display panels 10 tiled together. Specifically, the plurality of sub-display panels 10 may be spliced together in a single row, a double row, or a plurality of rows.

For example, the sub display panels 10 have the same shape, and the sizes of the plurality of sub display panels 10 are also the same. At this time, a plurality of the sub display panels 10 may be tiled with each other in an array arrangement.

For example, referring to fig. 1, in the present embodiment, the tiled display panel 100 includes four sub-display panels 10 (for convenience of distinction, 10a,10b, 10c, and 10d are respectively denoted), and the sub-display panels 10 are tiled in two rows and two columns.

It should be noted that, for clarity of describing the technical solution of the tiled display panel 100 of the present application, only four

sub-display panels

10a,10b, 10c and 10d are schematically illustrated in the drawings, although the present application is not limited thereto, and in other embodiments, the number of the sub-display panels 10 may be set according to actual requirements.

It should also be noted that the present application does not limit the way the sub-display panels 10 are spliced. For example, in other embodiments, two or more sub-display panels 10 may be bound to the same side of another sub-display panel 10 at the same time.

Referring to fig. 1, specifically, for each sub-display panel 10, each sub-display panel 10 is divided into a display area 110 and a non-display area 120 located at the periphery 120 of the display area. The arrangement is such that, in two adjacent sub display panels 10, the non-display area 120 of one of the sub display panels 10 is adjacent to the non-display area 120 of the other display panel 10, and the display areas 110 of the two sub display panels 10 are spaced apart.

Further, each sub-display surface 10 includes an array substrate and light emitting elements 13 arrayed on the array substrate. It should be noted that, in order to clearly illustrate the technical solution of the tiled display panel 100 of the present application, only the structure of the sub-display panel 10 is schematically described in the drawings and the text, and the structure of the sub-display panel 10 is not limited.

Referring to fig. 1, the array substrate is provided with a bonding trace 11. That is, the bonding wires 11 of the sub-display panel 10 are disposed in the array substrate. The bonding wires 11 are used to realize the bonding between the sub-display panels 10, or to bond the flip-chip film 200.

In the scheme of the application, the binding technology is adopted to correspondingly connect the plurality of binding wires 11 between the two sub-display panels 10, so that the space occupied by the parts such as screws is reduced at the splicing seam between the two sub-display panels 10, and the width of the splicing seam of the spliced display panel 100 is further reduced. Moreover, after the lines 11 of binding of two sub-display panels 10 correspond to meet, the peripheral drive structure can drive a plurality of sub-display panels 10 synchronously, compare in current tiled display panel, do not correspond between two sub-display panels 10 and connect, tiled display panel 100 of this embodiment is when driving each sub-display panel 10, and the synchronism of picture display is better.

In a specific working process, the bonding trace 11 can receive a driving signal from the outside and transmit the driving signal to the array substrate to control the light emitting or displaying of the light emitting element 13. In the present application, the bonding wires 11 may receive a driving signal from the chip on film 200 or the bonding wires 11 of another adjacent sub-display panel 10.

For example, in the sub-display panel 10a, the plurality of bonding wires 11 at the left side and the upper side are used for bonding the flip chip 200, the plurality of bonding wires 11 at the right side are used for bonding with the bonding wires 11 of the sub-display panel 10b, and the bonding wires 11 at the lower side are used for bonding with the plurality of bonding wires 11 of the sub-display panel 10 c.

Referring to fig. 1, the bonding wires 11 are located in the non-display area 120 of the array substrate, and the bonding wires 11 vertically extend from the outer edge of the display area 110 to the outer edge of the non-display area 120. Accordingly, the bundled traces 11 include a first bundled trace 111 disposed horizontally and a second bundled trace 112 disposed vertically according to the extending direction of the outer edge of the non-display area 120. This arrangement also fully satisfies the requirement of splicing between the bonding wires 11 of the adjacent sub-display panels 10.

Specifically, the bundled traces 11 include a first bundled trace 111 that is horizontally disposed and a second bundled trace 112 that is vertically disposed. Wherein the first binding trace 111 is used for binding between two sub display panels 10 adjacent in the horizontal direction. The second binding trace 112 is used for binding between two vertically adjacent sub display panels 10.

For example, referring to fig. 1, the sub-display panel 10a and the sub-display panel 10b are aligned and spliced by the first bonding wires 111 in the horizontal direction. The sub-display panel 10a and the sub-display panel 10c are aligned and spliced by the second binding wire 112 in the horizontal direction.

Specifically, the plurality of binding traces 11 are arranged at intervals in a direction perpendicular to the extending direction thereof. More specifically, the bonding traces 11 are arranged at intervals along the side direction of the non-display area 120. The arrangement is such that the plurality of binding wires 11 of the two sub-display panels 10 that are spliced with each other are connected in one-to-one alignment at the side faces of the overlapped edges of the two sub-display panels 10.

More directly speaking, at the splicing position 10 of the two sub-display panels, the side surfaces of the two corresponding binding wires 11 are aligned and attached.

Specifically, the extending directions of the two corresponding binding traces 11 are the same. More directly speaking, the arrangement direction of the two corresponding bonding wires 11 is the same as the arrangement direction of the two sub-display panels 10 to which the bonding wires belong.

In a preferred embodiment, the line widths of the two corresponding bonding wires 11 are consistent, so as to facilitate alignment splicing.

Specifically, a conductive adhesive (not shown in the drawings) is disposed between two adjacent sub-display panels 10, and the conductive adhesive is used for connecting two corresponding bonding wires 11. In other words, the sides of the two corresponding binding traces 11 are connected by the conductive adhesive.

For example, the conductive glue is arranged in a corresponding manner to the binding tracks 11. More specifically, at the overlapped side surfaces of two adjacent sub-display panels 10, the conductive adhesive is only disposed on the side surfaces of the bonding wires 11, so as to realize the alignment splicing between the side surfaces of the corresponding bonding wires 11. With the arrangement, the mutual interference between the two adjacent binding wires 11 on the same side can be avoided.

In other embodiments, a sealant is disposed between two adjacent sub-display panels 10, such that the sealant and the conductive adhesive are disposed at a distance from each other. Thus, the sealant can enhance the strength of the tiled display panel 100 and can also prevent the interconnection between adjacent conductive adhesives.

Specifically, the bonding wires 11 are disposed in different film layers of the array substrate. That is, the bonding trace 11 may be disposed on the same layer as the different film layers of the tft. By the arrangement, the three-dimensional space of the array substrate can be fully utilized, the width of a non-display area can be reduced, and the problem of short circuit or signal crosstalk caused by the fact that wiring is concentrated on the same film layer can be avoided. Furthermore, from the binding angle between the sub-display panels 10, the binding wires 11 are disposed in different film layers, the area of the butt joint between the binding wires 11 can be increased correspondingly, the conduction area between the binding wires 11 in the corresponding butt joint can be increased, the resistance is reduced, and on the other hand, a plurality of signal transmission channels can be formed between two adjacent sub-display panels 10 simultaneously, so that the stability of signal transmission is improved.

Furthermore, the array substrate further comprises a signal wire, a thin film transistor and a binding electrode. Wherein the bonding electrode is connected to the thin film transistor, the thin film transistor is electrically connected to the signal trace, and the signal trace is electrically connected to the bonding trace 11. Thus, the driving signal in the bonding wire 11 is transmitted to the light emitting element 13 via the signal wire, the thin film transistor and the bonding electrode.

As shown in fig. 2, the signal trace 12 is disposed in the display area 110, and the signal trace 12 is connected to the bonding trace 11 for transmitting a driving signal of the bonding trace 11 to the thin film transistor.

Specifically, the signal traces 12 are Gate lines (Gate lines) and Data lines (Data lines). The grid line is connected to the grid electrode of the thin film transistor, and the data line is connected to the source electrode of the thin film transistor.

In other embodiments, the signal traces can also be, but are not limited to, a power line Vdd, a common voltage line Vss, a scan line Vscan, a sense line Vsense, or a reference voltage line Vref.

Specifically, the thin film transistor is located in the display region 110, and has a switching or driving function. Specifically, the thin film transistor may include a gate electrode, an active layer, a source electrode and a drain electrode, the source electrode and the drain electrode being connected to the doped regions at both sides of the active layer, respectively. A gate insulating layer may be further disposed between the gate electrode and the active layer to insulate the gate electrode and the active layer from each other. However, it should be noted that the present application does not limit the type or structure of the thin film transistor, and the type or structure may be modified or selected according to the actual display requirements.

Specifically, the plurality of binding electrode arrays are arranged in the display region 110 to drive the light emitting elements 13 by supplying power. In other words, the light emitting element 13 is electrically connected to the drain of the thin film transistor through the bonding electrode.

As shown in fig. 1, the plurality of light emitting elements 13 are disposed in the display region 110 of the array substrate. Specifically, the light emitting element 13 is bonded to the bonding electrode of the array substrate.

In a specific implementation, the light emitting element 13 is a Micro light emitting diode (Micro LED) or a Mini light emitting diode (Mini LED). The Mini LED size is between the size of a conventional LED and the size of a Micro LED. Note that the light-emitting element 13 of the present application is not limited thereto. That is, the structure of the light emitting element 13 can be changed in real time according to different requirements of the display.

For example, as shown in fig. 1, in the present embodiment, when the light emitting elements 13 are Micro LEDs or Mini LEDs, the light emitting elements 13 can be transferred onto the array substrate by a bulk transfer method, and bonded to the driving electrodes of the array substrate through the bonding electrodes of the light emitting elements 13.

Referring to fig. 1, in the present embodiment, the sub-display panel 10 forms at least one pixel unit. The number of the light emitting elements 13 in a pixel unit including the red light emitting element 13, the blue light emitting element 13, and the green light emitting element 13 is generally at least 3. That is, at least 1 red light emitting element 13, 1 blue light emitting element 13, and 1 green light emitting element 13 are included in the pixel unit.

In the present embodiment, the three light emitting elements 13 are arranged in a row in the lateral direction. In other embodiments, the three light emitting elements 13 are arranged longitudinally in a row. Note that, in order to more intuitively express the structure of the sub display panel 10 of the present application. The film structures of the array substrate and the light emitting device 13 are not illustrated in fig. 1 and 2. It should be understood by those skilled in the art that the array substrate and the light emitting element 13 actually include a film structure, but are not limited thereto.

Referring to fig. 1, the connecting leads 20 are located at the splicing position of two adjacent sub-display panels 10, and extend from the non-display area 120 of one of the sub-display panels 10 to the non-display area 120 of the other sub-display panel 10 continuously, so as to transmit the driving signal of one of the sub-display panels 10 to the other sub-display panel 10.

Obviously, by arranging the connection leads 20, signal transmission between the adjacent two sub display panels 10 can be achieved. Meanwhile, the connecting lead 20 can also increase the conduction path between the two corresponding binding wires 11, thereby improving the stability of the transmission of the driving signal and reducing the on-resistance. In addition, the connection lead 20 also increases the stability of the binding between the binding traces 11, and improves the strength and binding stability of the splicing of the two adjacent sub-display panels 10.

Specifically, the two opposite ends of the connection lead 20 are respectively connected to the two corresponding bonding wires 11, so as to transmit the driving signal of one of the bonding wires 11 to the other corresponding bonding wire 11, thereby achieving the purpose of transmitting the driving signal of one of the sub-display panels 10 to the other sub-display panel 10.

More specifically, in the present embodiment, one end of the connection lead 20 is directly formed on the surface of the bonding trace 11 therein, and the other end of the connection lead 20 is formed on the corresponding other bonding trace 11.

Further, the line width of the connection lead 20 is smaller than the line width of the bonding trace 11. The orthographic projection of the connecting lead 20 on the tiled display panel 100 is located on the two corresponding butted bonding wires 11.

In other embodiments, the connecting leads 20 and the bonding traces 11 may be separated by a dielectric layer, and then electrically connected by vias.

More specifically, in any two adjacent sub display panels 10, the extending direction of the connecting leads 20 is the same as the arrangement direction of the two adjacent sub display panels 10.

For example, in the present embodiment, the connection lead 20 includes a first connection lead 21 extending horizontally and a second connection lead 22 extending vertically. Wherein in the horizontally arranged

sub-display panels

10a,10b, first connecting leads 21 are arranged. In the vertically arranged

sub display panels

10a,10 c, the second connection leads 22 are arranged.

Specifically, the material of the connecting lead 20 is gold, silver or graphene. In one embodiment, the material of the connecting lead 20 is Ag. This may be used. In other embodiments, the connecting leads 20 may also be made of a conductive material such as graphene, which is convenient for performing a transfer printing and a jet printing process, and the specific material may be selected according to practical situations, which is not limited herein. In other embodiments, the patterned connection leads 20 may be formed by depositing a conductive material and then laser engraving.

Based on the same inventive concept, the present application further provides a display device, which includes the tiled display panel 100 and the flip-chip film 200 of the present application.

As shown in fig. 2, the flip-chip film 200 is located at the periphery of the tiled display panel 100, and the flip-chip film 200 is bonded on the outer side of the tiled display panel 100. That is, in the display device of the present application, the flip-chip film 200 is only disposed at the outermost periphery of the entire tiled display panel 100, and the disposing of the flip-chip film 200 between the adjacent sub-display panels 10 is avoided.

In specific implementation, the flip-chip film 200 includes a flip-chip film 200 for transmitting a driving signal to the gate line and a flip-chip film 200 for transmitting a driving signal to the data line.

The tiled display panel and the display device provided by the embodiment of the present application are described in detail above, and specific examples are applied herein to illustrate the principle and the implementation manner of the present application, and the description of the above embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A spliced display panel comprises a plurality of sub display panels spliced together, and is characterized in that a plurality of connecting leads are arranged in every two adjacent sub display panels and are used for transmitting driving signals between the two adjacent sub display panels.

2. The tiled display panel of claim 1 wherein each of the sub-display panels comprises a display area and a non-display area on at least one side of the display area;

3. The tiled display panel according to claim 2, wherein a plurality of bonding wires are disposed in the non-display area of each of the sub-display panels;

4. The tiled display panel of claim 3, wherein the binding traces extend vertically from an outer edge of the display area to an outer edge of the non-display area;

5. The tiled display panel according to claim 4, wherein a conductive adhesive is disposed between two adjacent sub-display panels, and the conductive adhesive is used to connect two corresponding bonding wires.

6. The tiled display panel according to claim 4, wherein one end of the connecting lead is disposed on one of the two corresponding bonding wires, and the other end of the connecting lead is disposed on the other of the two corresponding bonding wires.

7. The tiled display panel of claim 6, wherein the line width of the connection lead is less than or equal to the line width of the bonding trace.

8. The tiled display panel of claim 1 wherein the material of the connecting leads is gold or silver.

9. The tiled display panel of claim 1, wherein the sub-display panel is a Mini-LED sub-display panel or a Micro-LED sub-display panel.

10. A display device comprising the tiled display panel of any of claims 1 to 9 and a flip-chip film;