CN113569513A - Waveguide mode-based on-chip multidimensional logic gate design method - Google Patents
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Abstract
The invention discloses a design method of an on-chip multidimensional logic gate based on a waveguide mode, which adopts a reverse design method to set a structural area into an m multiplied by n structural matrix, a nm multiplied by a nm pixel point is arranged at the position corresponding to the structural matrix according to the serial number of an array, the pixel point is endowed with different initial values, then the FDTD algorithm and the initial value endowed by each pixel of the m multiplied by n structural matrix are utilized to respectively calculate the proportion of each mode in the output port of different input modes, the corresponding position in the structural matrix is found according to the serial number in the array of the structural matrix for transformation operation, if the new FOM value after operation is larger than the previous FOM value, the structural change is reserved, meanwhile, the FOM is updated to the FOM of a new structure, otherwise, the reverse design method is not adopted; if the FOM is unchanged, the solution is locally optimal. According to the invention, the refractive index distribution of the device region is continuously changed, so that a local optimal solution or a global optimal solution is finally obtained, the accuracy degree of the structure is greatly improved, and the performance of the silicon-based subwavelength structure is improved.
Description
Technical Field
The invention relates to the technical field of micro-nano photoelectron and quantum information, in particular to a design method of an on-chip multi-dimensional logic gate based on a waveguide mode.
Background
Quantum computing (quantum computing) is a completely new computing method based on the fundamental principle of quantum mechanics and having ultra-strong parallel computing capability. If binary '0' and '1' are used to represent information, the classical bit (bit) for processing information in the classical computer can only be in '0' or '1' at a certain moment, and N bits can only be matched with 2 bits in a single operationN1 of the numbers are operated, and the quantum bit (qubit) in a quantum computer can be at |0>And |1>Arbitrary superposition state (α | 0)>+β|1>) In addition, the N qubits can be operated once to realize the parallel operation of 2N quantities, and the superposition characteristic enables the quantum computer to have obvious advantages over a classical computer when the quantum computer processes certain specific problems such as password deciphering and data searching.
The processor of a general-purpose quantum computer consists of quantum logic gates. The quantum logic gate completes the controlled evolution of the quantum bit through unitary transformation of quantum mechanics, and is the basis for realizing quantum computation.
Among the quantum systems, the light quantum system has been leading in the development of quantum information for decades by virtue of its natural advantages. Photons are a flying qubit, and their ultra-fast propagation speed is very favorable as a carrier for information transmission. The light quantum state has good immunity to environmental noise in the transmission process, and can still maintain the coherence after a long transmission distance and time. Meanwhile, photons have many degrees of freedom for encoding, including photon path, polarization, orbital angular momentum, frequency, time, etc., and in integrated optics, waveguide modes can also be used to encode information. In all quantum systems, the requirements of the light quantum system on hardware are the lowest, and the light quantum system does not need to be operated in vacuum and low-temperature environments, so that the regulation and control difficulty of a quantum state is reduced, and meanwhile, the photon system is most beneficial to principle display and experimental verification.
There are two main current research directions: firstly, linear optical quantum computation of manipulating photons in a free space is simple to operate and mature in technology, most quantum computation schemes are verified in a free space optical system at first at present, but the quantum computation schemes are poor in expandability and stability and are very easy to be disturbed by environmental factors; and secondly, on the basis of the light quantum calculation of an integrated chip, the chip usually uses an optical waveguide to construct a complex photon loop. Although the waveguide chip system is still in the initial stage at present, the waveguide chip system has good expandability, stability and high integration degree, and therefore the waveguide chip system has a wide prospect. Meanwhile, the high-dimensional quantum communication has the following advantages: 1) the information capacity is larger; 2) higher tolerance to noise; 3) the robustness to quantum cloning is enhanced; 4) more significantly violating the localization theory and bell inequality. Therefore, high-dimensional quantum communication has attracted an increasing amount of attention of researchers in recent years.
A Sub-Wavelength Structure (SWS) is an arrayed Structure with a period much shorter than the equivalent Wavelength of the material, i.e., a period of lambda < lambda (2 n)eff) Where λ is the vacuum wavelength, neffIs the equivalent refractive index. Because the period of the medium is far less than the wavelength, only zero-order diffraction exists in the sub-wavelength structure, and the high-order diffraction order of light cannot propagate to the free space and can only be bound in the structure, the medium can be regarded as an anisotropic medium as a whole. A device having a desired function can be realized by etching a design pattern varying according to a sub-wavelength scale on a surface of a Silicon On Insulator (SOI) and filling other materials (e.g., air, Silicon dioxide, etc.).
Because the dielectric constant of the waveguide can be flexibly changed in an ultra-small scale, the silicon-based sub-wavelength structure can efficiently regulate and control the optical field, and a subminiature and high-performance silicon-based photonic device is realized. In the past, when designing silicon-based photonic devices, the design process was "blind" to some extent, which mainly relied on some prior knowledge physical models or effects, and then found the best points of the models that could match the geometric parameters of the desired function by simple parameter adjustment or parameter scanning methods based on experience. The design method of searching the model parameters of the device through parameter adjustment or parameter scanning belongs to forward design. The device model designed by the method is generally simple in structure, generally has a certain theoretical physical model and can be analyzed by an analytical method. Through parameter scanning, a device with a target function can be manually selected from a series of devices with different structure parameters.
However, this conventional design approach takes into account very limited parametric dimensions and does not predict whether good results can be achieved. More importantly, devices with special functions and size requirements cannot be designed in this way. There is therefore a need for further improvements in the design of existing silicon-based subwavelength structures.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method for manufacturing a high-dimensional on-chip multidimensional logic gate based on a waveguide mode, which improves the performance of an optical quantum logic gate.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a method for designing an on-chip multidimensional logic gate based on a waveguide mode comprises the following steps:
a method for designing an on-chip multidimensional logic gate based on a waveguide mode is characterized by comprising the following steps:
step 1: determining the size of the structural region and the initial value of the pixel point: setting the structural area into an m multiplied by n structural matrix by adopting a reverse design method, arranging a nm multiplied by a nm pixel point on the position corresponding to the structural matrix according to the serial number of the array, arranging a round hole with the diameter of d nm at the center of the pixel point position, wherein the round hole is made of Si or SiO2Different initial values are given to different pixel points according to the material;
step 2: calculating the proportion of each mode in the output ports of different input modes by using an FDTD algorithm and an initial value given to each pixel point of an m multiplied by n structural matrix, wherein the input and output modes areIs TEiAnd the FOM constituting the evaluation structure was used, and the FOM expression is as follows:
wherein t isi 1To input TEiTransmittance of target mode after mode, ti 2To input TEiThe transmittance of the latter other modes, α is a balance factor of loss and crosstalk, m is the number of modes, i is 0,1,2, …, m;
and step 3: and finding the corresponding position in the structural matrix according to the sequence number in the structural matrix array to perform structural conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the material of the round hole into SiO by a control program2Then calculating FOM to obtain a new FOM value;
operation 2: if the material of the circular hole in the corresponding position is SiO2Modifying the round hole material into Si through a control program, and then calculating FOM to obtain a new FOM value;
comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the FOM value before conversion, retaining the structure after the structure conversion operation, and updating the FOM to the FOM of the new structure, otherwise, retaining the original structure and the FOM value thereof;
and 4, step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel of a corresponding number sequence of the structural matrix, sequentially comparing and reserving FOM values with large FOM values and the corresponding structural matrix according to the sequence from small to large of 1-mn to obtain a round of optimized FOM and the structural matrix;
and then, taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and performing optimization by analogy, and if the FOM is not changed after the round of optimization, obtaining a local optimal solution.
Preferably, the initial value of the pixel is set to 0 or 1.
Preferably, the value range of m and n in the m × n structural matrix is 10-50;
preferably, a in the pixel of a nm x a nm ranges from 80nm to 220 nm.
Preferably, the diameter d of the circular hole ranges from 60nm to 150 nm.
Preferably, the size of the structural region is 2.5-4.5. mu. m.times.1-2.5. mu.m.
Preferably, the etching depth h of the structure region is 150-250 nm.
The invention has the beneficial technical effects that: the invention adopts a reverse design method, utilizes a plurality of waveguide modes in the multimode waveguide, continuously converts the matrix structure, reserves the FOM value with large value and the corresponding mechanism, finally obtains the local optimal or global optimal solution, obtains the design of the silicon-based sub-wavelength high-dimensional quantum logic gate device with fine structure, and greatly improves the performance of the optical quantum logic gate.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for designing an on-chip multi-dimensional logic gate based on a waveguide mode according to the present invention.
Fig. 2 is a schematic structural diagram of a three-dimensional X-gate according to an embodiment of the invention.
Fig. 3 is a transmission map of a three-dimensional X input TE0 mode according to an embodiment of the present invention.
Fig. 4 is a transmission map of a three-dimensional X input TE1 mode according to an embodiment of the present invention.
Fig. 5 is a transmission map of a three-dimensional X input TE2 mode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments, but the scope of the present invention is not limited to the following embodiments.
Another device design approach that differs from the forward design is the "reverse design". The reverse design refers to a process of designing the refractive index distribution of the device region according to the target function required by us by regarding the device region as a black box.
According to the process characteristics of a common passive SOI device, the refractive index of a device region usually shows two states of being etched or not etched. When the upper cladding layer of the SOI device is air, the material composition of the etched part is air, and the material composition of the non-etched part is silicon.
The overall idea of the reverse design is to set a Figure of merit (FOM) according to the target function of the device, and find a device form that can maximize the FOM through a reverse optimization algorithm. In addition, the morphology of the device often needs to meet certain constraints. Compared with the traditional forward design, the reverse design method opens a larger parameter space, can obtain a very fine structure through optimization calculation, obtains a local optimal or global optimal solution, and fully utilizes the existing high-precision manufacturing process and high-performance calculation capability.
In this embodiment, a reverse design is used to implement the design of the on-chip multidimensional logic gate based on the waveguide mode, and the specific scheme of this embodiment is as follows:
as shown in fig. 1, a method for designing an on-chip multidimensional logic gate based on a waveguide mode includes the following steps:
step 1: determining the size of the structural region and the initial value of the pixel point: and setting the structural area into an m multiplied by n structural matrix by adopting a reverse design method, wherein the value range of m and n in the m multiplied by n structural matrix is 12-50. The position of the structure matrix corresponding to the serial number of the array is provided with a nm multiplied by a nm pixel point, the value range of a is 100 nm-200 nm, the center of the pixel point position is provided with a round hole with the diameter of d nm, the value range of d is 90nm-150nm, and the round hole is made of Si or SiO2Different initial values are assigned to different pixel points of the material, and the initial values of the pixel points are set to be 0 or 1. The initial value assignment of the structure is similar to the asymmetric structure of the mode conversion device, and can accelerate the convergence of iterative calculation.
The size of the structural region is 2.5-4.5 μm multiplied by 1-2.5 μm, and the etching depth h of the structural region is 150-250 nm.
Step 2: the method is characterized in that the FDTD algorithm (FDTD algorithm, full-name time domain difference method, which is a common simulation method of a photonic device) is utilized to respectively calculate the proportion of each mode in the output port of different input modes according to the initial value given by each round hole position of an m multiplied by n structural matrix (the proportion columns of each mode in the output port are different after different modes are input into the input port of the structure matrix, the proportion of each mode in the output port is calculated by a re-integration method, and the method is a method for analyzing mode components which is commonly used when a 3D-FDTD algorithm is utilized to simulate a silicon-based photonic passive device.
The input-output mode is TEi and is used to construct the FOM for evaluating the structure, the FOM expression is as follows:
wherein t isi 1To input TEiTransmittance of target mode after mode, ti 2To input TEiThe transmittance of the latter other mode, α is a balance factor of loss and crosstalk, m is the number of modes, and i is 0,1,2, …, m.
Using TE0 mode input as an example, the target is converted to TE1 mode, so t0 1The transmittance of the TE1 mode after the TE0 mode is inputted, so t0 2The transmittance of the TE0 or TE2 mode after the TE0 mode is input; alpha is a balance factor of loss and crosstalk, and when alpha is close to 0, a lower loss result can be obtained, and when alpha is close to 1, a lower crosstalk result can be obtained.
And step 3: and finding the corresponding position in the structural matrix according to the sequence number in the structural matrix array to perform structural conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the material of the round hole into SiO by a control program2Then recalculating the FOM to obtain a new FOM value;
operation 2: if the material of the circular hole in the corresponding position is SiO2Modifying the round hole material into Si through a control program, and then recalculating FOM to obtain a new FOM value;
the purpose of converting different materials in operation 1 and 2 is to change the material of the circular hole in the pixel, namely the refractive index in the circular hole, so that the distribution of the refractive index in the device is successfully regulated, and the numerical value of the pixel corresponding to the position of the changed circular hole of the material is changed accordingly. The conversion of the material is to control the change of the structural matrix through writing scripts, so that the structure of the device is changed.
Comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the FOM before conversion, keeping the structure conversion operation, and updating the FOM to the FOM with a new structure, otherwise, keeping the FOM unchanged and keeping the original structure;
and 4, step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel of a corresponding number sequence of the structural matrix, and sequentially comparing and reserving a larger FOM and a corresponding structural matrix according to the sequence from small to large of 1-mn to obtain a round of optimized FOM and structural matrix;
because each matrix element of the m multiplied by n structural matrix corresponds to one material (Si or SiO)2) The total number of matrix elements is mn. If the structure matrix is used to obtain the desired structure, 2mn comparisons are required to obtain the desired structure, but the comparison is time-consuming, labor-consuming and difficult to complete, so that the calculation time is greatly saved and the efficiency is improved by adopting the step 4.
And then, taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and performing optimization by analogy, and obtaining a local optimal solution if the FOM is not changed after one round of optimization, wherein the non-change means the FOM between two adjacent rounds, and the value of the FOM is not changed and optimized after one round of optimization, so that the optimal value is already reached.
The method can be applied to design any multidimensional logic gate structure, and the following method is a three-dimensional X gate designed by the method of the embodiment.
As shown in fig. 2, the size of the three-dimensional X-gate structure obtained in this embodiment is 3.6 μm × 1.8 μm, the etching depth h is 220nm, the size of the pixel point is 150nm × 150nm, a circular hole with a diameter of 100nm is formed in the center of the pixel point, and at this time, the reverse design structure region corresponds to a 24 × 12 structure matrix.
When the TE0 mode is input, the TE1 mode is output, the TE1 mode is input, the TE2 mode is output, and the TE2 mode is input, the TE0 mode is output, so that the X-gate operation is realized.
3-5 are transmission diagrams of input TE0 mode, TE1 mode and TE2 mode, respectively, where the loss of the TE0 mode converted into TE1 mode is <1dB and the crosstalk is <22dB in 1540nm-1560nm band; the loss of the TE1 mode converted to the TE2 mode is <1.13dB, and the crosstalk is <21.24 dB; the TE2 mode translates to a loss of <0.73dB for the TE0 mode and a crosstalk of <22.9 dB.
By adopting the reverse design scheme of the invention, the local optimal or global optimal solution is finally obtained by continuously changing the refractive index distribution of the device region, thereby greatly improving the accuracy of the structure and improving the performance of the silicon-based subwavelength structure.
Variations and modifications to the above-described embodiments may occur to those skilled in the art, which fall within the scope and spirit of the above description. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (7)
1. A method for designing an on-chip multidimensional logic gate based on a waveguide mode is characterized by comprising the following steps:
step 1: determining the size of the structural region and the initial value of the pixel point: setting the structural area into an m multiplied by n structural matrix by adopting a reverse design method, arranging a nm multiplied by a nm pixel point on the position corresponding to the structural matrix according to the serial number of the array, arranging a round hole with the diameter of d nm at the center of the pixel point position, wherein the round hole is made of Si or SiO2Different initial values are given to different pixel points according to the material;
step 2: calculating the proportion of each mode in the output ports of different input modes by using FDTD algorithm and the initial value given to each pixel point of the m multiplied by n structural matrixThe input/output mode is TEiAnd the FOM constituting the evaluation structure was used, and the FOM expression is as follows:
wherein t isi 1To input TEiTransmittance of target mode after mode, ti 2To input TEiThe transmittance of the latter other modes, α is a balance factor of loss and crosstalk, m is the number of modes, i is 0,1,2, …, m;
and step 3: and finding the corresponding position in the structural matrix according to the sequence number in the structural matrix array to perform structural conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the material of the round hole into SiO by a control program2Then recalculating the FOM to obtain a new FOM value;
operation 2: if the material of the circular hole in the corresponding position is SiO2Modifying the round hole material into Si through a control program, and then recalculating FOM to obtain a new FOM value;
comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the FOM before conversion, keeping the structure conversion operation, and updating the FOM to the FOM with a new structure, otherwise, keeping the FOM with the original structure;
and 4, step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel point of the corresponding number sequence of the structural matrix, sequentially comparing the sequences from small to large according to 1-mn, and reserving the FOM with the large numerical value FOM in the comparison structure and the corresponding structural matrix to obtain a round of optimized FOM and structural matrix;
and then, taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and performing optimization by analogy, and if the FOM is not changed after the round of optimization, obtaining a local optimal solution.
2. The method of claim 1, wherein the initial value of the pixel is set to 0 or 1.
3. The method according to claim 1, wherein the m and n values in the m x n structural matrix are in the range of 10-50;
4. the method of claim 1, wherein a of the a nm x a nm pixels has a value in the range of 80nm to 220 nm.
5. The method according to claim 1, wherein the diameter d of the circular hole ranges from 60nm to 150 nm.
6. The method of claim 1, wherein the size of the structural region is 2.5-4.5 μm x 1-2.5 μm.
7. The method as claimed in claim 6, wherein the etching depth h of the structural region is 150-250 nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114019606A (en) * | 2022-01-06 | 2022-02-08 | 浙江大学 | Small broadband mode conversion device |
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