CN113569513B - On-chip multidimensional logic gate design method based on waveguide mode - Google Patents
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Abstract
The invention discloses a method for designing a multi-dimensional logic gate on a chip based on a waveguide mode, which adopts a reverse design method to set a structural area into an m multiplied by n structural matrix, wherein a nm multiplied by a nm pixel point is arranged at the position corresponding to the structural matrix according to the serial number of an array, the pixel point is endowed with different initial values, then the ratio of each mode in output ports of different input modes is calculated respectively by utilizing an FDTD algorithm and the initial value endowed by each pixel of the m multiplied by n structural matrix, the corresponding position in the structural matrix is found according to the serial number in the structural matrix array for transformation operation, if the new FOM value after the operation is larger than the previous FOM value, the structural change is reserved, and meanwhile, the FOM is updated into the FOM of the new structure, otherwise; and if the FOM is not changed, the solution is locally optimal. According to the invention, the refractive index distribution of the device region is continuously changed, so that the local optimum or global optimum solution is finally obtained, the precision of the structure is greatly improved, and the performance of the silicon-based sub-wavelength structure is improved.
Description
Technical Field
The invention relates to the technical field of micro-nano photoelectrons and quantum information, in particular to a method for designing an on-chip multidimensional logic gate based on a waveguide mode.
Background
Quantum computing (quantum computation) is a brand new computing mode with ultra-strong parallel computing capability based on quantum mechanics basic principle. If binary "0" and "1" are used"to represent information, classical bits (bits) of information processed in a classical computer can only be at" 0 "or" 1 "at a particular time, and N bits can only be used for 2 in a single operation N 1 of the numbers operates, while a qubit (qubit) in a quantum computer may be at |0>And |1>Is (alpha|0)>+β|1>) Above, a single operation of N qubits enables parallel operations on 2N numbers simultaneously, and this superposition feature gives quantum computers significant advantages over classical computers in dealing with certain specific problems such as password cracking and data searching.
The processor of a general-purpose quantum computer consists of quantum logic gates (quantum logic gate). The quantum logic gate completes the controlled evolution of the quantum bit through the unitary transformation of quantum mechanics, and is the basis for realizing quantum computation.
Among the many quantum systems, the optical quantum system has been in the lead of the development of quantum information for decades by virtue of its natural advantages. Photons are a flying qubit whose ultra-fast propagation speed is very useful as a carrier for information transmission. The light quantum state has good immunity to environmental noise in the transmission process, and can still maintain the coherence after long transmission distance and time. Meanwhile, photons have many degrees of freedom to encode, including photon path, polarization, orbital angular momentum, frequency, time, etc., while waveguide modes can also be used to encode information in integrated optics. Among all quantum systems, the requirement of the optical quantum system on hardware is minimum, and the optical quantum system does not need to operate in a vacuum and low-temperature environment, so that the difficulty in regulating and controlling quantum states is reduced, and meanwhile, the photonic system is most beneficial to principle display and experimental verification.
There are two main categories of research directions at present: firstly, the linear optical quantum calculation for manipulating photons in free space is simple to operate and mature in technology, most quantum calculation schemes are firstly verified in a free space optical system at present, but the linear optical quantum calculation schemes are poor in expandability and stability and are very easy to be disturbed by environmental factors; second, integrated chip-based optical quantum computation, in which optical waveguides are typically used to build complex photonic circuits. Although the waveguide chip system is still in a starting stage at present, the waveguide chip system has good expandability, stability and high integration level, and therefore has wide prospect. Meanwhile, high-dimensional quantum communication has the following advantages: 1) The system has larger information capacity; 2) The noise tolerance is higher; 3) The robustness to quantum cloning is enhanced; 4) More significantly violating the localization theory and bell inequality. Therefore, high-dimensional quantum communication attracts more and more researchers' attention in recent years.
The Sub-wavelength structure (Sub-Wavelength Structure, SWS) is an arrayed structure with a period substantially less than the material equivalent wavelength, i.e. a period lambda < lambda (2 n) eff ) Wherein λ is the vacuum wavelength, n eff Is equivalent refractive index. Because the period is far smaller than the wavelength, only zero-order diffraction exists in the sub-wavelength structure, and no higher-order diffraction order of light can propagate to free space and can only be bound in the structure, the whole structure can be regarded as a layer of anisotropic medium. Devices with targeted functionality can be achieved by etching a design pattern that varies according to the sub-wavelength scale on the surface of a silicon material (Silicon on insulator, SOI) on an insulator and filling with other materials (e.g., air, silicon dioxide, etc.).
The waveguide dielectric constant can be flexibly changed in an ultra-small scale, so that the silicon-based sub-wavelength structure can be used for efficiently regulating and controlling the light field, and an ultra-small and high-performance silicon-based photon device is realized. In the past, when designing silicon-based photonic devices, it has been mainly relied on some prior knowledge of the physical model or effect, and then the best points of these models, which can be matched with the geometric parameters of the desired function, are found empirically by simple parameter adjustment or parameter scanning methods, and this design process is "blind" to some extent. The design method for searching the model parameters of the device through parameter adjustment or parameter scanning belongs to the forward design. The device model designed in this way is generally simple in structure and generally has a certain theoretical physical model that can be analyzed by analytical methods. By means of parameter scanning, one can manually pick out devices with target functions from a series of devices with different structural parameters.
However, the parametric dimensions considered by this conventional design approach are quite limited and it cannot be predicted whether a better result is achieved. More importantly, devices with special functions and dimensional requirements cannot be designed in this way. Therefore, there is a need for further improvements in the design of existing silicon-based sub-wavelength structures.
Disclosure of Invention
In order to solve the technical problems, the invention provides a manufacturing method of a high-dimensional on-chip multi-dimensional logic gate based on a waveguide mode, which improves the performance of a light quantum logic gate.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: an on-chip multidimensional logic gate design method based on waveguide mode, comprising the following steps:
an on-chip multidimensional logic gate design method based on a waveguide mode is characterized by comprising the following steps:
step 1: determining the size of a structural area and the initial value of a pixel point: the structural area is set to be an m multiplied by n structural matrix by adopting a reverse design method, a pixel point with a nm multiplied by a nm is arranged at the position corresponding to the structural matrix according to the serial number of the array, a round hole with a diameter of d nm is arranged at the center of the pixel point, and the round hole is made of Si or SiO 2 Different initial values are given according to different pixel points of the material;
step 2: calculating the proportion of each mode in the output ports of different input modes by using FDTD algorithm and the initial value given by each pixel point of m multiplied by n structural matrix, wherein the input and output modes are TE i And the FOM of this structure was evaluated using its constitution, the FOM expression is as follows:
wherein t is i 1 To input TE i Transmittance of target mode after mode, t i 2 To input TE i Transmittance of other modes, alpha is balance factor of loss and crosstalk, and m is number of modes，i＝0,1,2,…,m；
Step 3: finding the corresponding position in the structure matrix according to the sequence number in the structure matrix array to perform structure conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the round hole material into SiO through a control program 2 Then calculating FOM to obtain new FOM value;
operation 2: if the material of the round hole in the corresponding position is SiO 2 Modifying the round hole material into Si through a control program, and then calculating the FOM to obtain a new FOM value;
comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the previous FOM value, retaining the structure after the structure conversion operation, and updating the FOM into the FOM with the new structure, otherwise, retaining the original structure and the FOM value thereof;
step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel of corresponding number sequences of the structural matrix, sequentially comparing and retaining FOM values with large FOM values and corresponding structural matrixes according to the sequence from 1-mn to large, and obtaining a round of optimized FOM and structural matrixes;
and then taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and advancing the row optimization, wherein if the FOM is unchanged after the round of optimization, the local optimal solution is obtained.
Preferably, the initial value of the pixel is set to 0 or 1.
Preferably, the range of m and n values in the m×n structure matrix is 10-50;
preferably, the value of a in a pixel of a nm x a nm is in the range of 80nm to 220nm.
Preferably, the diameter d of the round hole has a value ranging from 60nm to 150nm.
Preferably, the size of the structural region is 2.5-4.5 μm×1-2.5 μm.
Preferably, the etching depth h of the structural region is 150-250nm.
The beneficial technical effects of the invention are as follows: the invention adopts a reverse design method, utilizes a plurality of waveguide modes in the multimode waveguide to continuously convert the matrix structure, retains the FOM value with large numerical value and the corresponding mechanism, finally obtains the local optimum or global optimum solution, obtains the design of the silicon-based sub-wavelength high-dimensional quantum logic gate device with fine structure, and greatly improves the performance of the optical quantum logic gate.
Drawings
FIG. 1 is a flow chart of steps of a method for designing a multi-dimensional logic gate on a chip based on a waveguide mode according to the present invention.
Fig. 2 is a schematic diagram of a three-dimensional X-gate structure according to an embodiment of the invention.
Fig. 3 is a transmission spectrum of a three-dimensional X-input TE0 mode according to an embodiment of the present invention.
Fig. 4 is a transmission spectrum of a three-dimensional X-input TE1 mode according to an embodiment of the present invention.
Fig. 5 is a transmission spectrum of a three-dimensional X-input TE2 mode according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail with reference to the following examples, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent, but the scope of the present invention is not limited to the following specific examples.
Another device design approach that differs from forward design is "reverse design". Reverse design refers to the process of designing the refractive index profile of the device region for our desired target function, with the device region being considered a "black box".
Depending on the process characteristics of a conventional passive SOI device, the refractive index of the device region typically exhibits both "etched" and "not etched" states. When the upper cladding layer of the SOI device is air, the etched part of the material composition is air, and the non-etched part of the material composition is silicon.
The overall idea of the reverse design is to set a Figure of merit (FOM) according to the target function of the device, and find a device shape that can maximize the FOM through a reverse optimization algorithm. In addition, the morphology of the device is often required to meet certain constraints. Compared with the traditional forward design, the reverse design method opens a larger parameter space, can obtain a very fine structure through optimization calculation, obtains a local optimal or global optimal solution, and fully utilizes the existing high-precision manufacturing process and high-performance computing capability.
The embodiment is to realize the design of the on-chip multidimensional logic gate based on the waveguide mode by utilizing reverse design, and the specific scheme of the embodiment is as follows:
as shown in fig. 1, a method for designing a multi-dimensional logic gate on a chip based on a waveguide mode, the method comprising the steps of:
step 1: determining the size of a structural area and the initial value of a pixel point: and setting the structural area into an m multiplied by n structural matrix by adopting a reverse design method, wherein the range of values of m and n in the m multiplied by n structural matrix is 12-50. The array number is corresponding to the structure matrix, the pixel point with a nm x a nm is arranged at the position, the value range of a is 100nm-200nm, a round hole with a diameter d nm is arranged at the center of the pixel point position, the value range of d is 90nm-150nm, and the round hole is made of Si or SiO 2 Different initial values are assigned to different pixel points of the material, and the initial value of the pixel point is set to 0 or 1. The initial value assignment of the structure is similar to the asymmetric structure of the mode conversion device, so that the convergence of iterative calculation can be quickened.
The size of the structural region is 2.5-4.5 μm×1-2.5 μm, and the etching depth h of the structural region is 150-250nm.
Step 2: the method is a method for analyzing mode components commonly used in simulating a silicon-based photon passive device by using a 3D-FDTD algorithm.
The input/output mode is TEi, and the FOM of the structure is evaluated by using the composition, and the FOM expression is as follows:
wherein t is i 1 To input TE i Transmittance of target mode after mode, t i 2 To input TE i The transmittance of the latter other modes, α is the balance factor of loss and crosstalk, m is the number of modes, i=0, 1,2, …, m.
Taking the TE0 mode input as an example, the target is converted into TE1 mode, so t 0 1 To input the transmittance of TE1 mode after TE0 mode, so t 0 2 The transmittance of TE0 or TE2 mode after inputting TE0 mode; alpha is a balance factor of loss and crosstalk, and when alpha tends to be 0, a lower loss result is obtained, and when alpha tends to be 1, a lower crosstalk result is obtained.
Step 3: finding the corresponding position in the structure matrix according to the sequence number in the structure matrix array to perform structure conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the round hole material into SiO through a control program 2 Then recalculate the FOM to obtain a new FOM value;
operation 2: if the material of the round hole in the corresponding position is SiO 2 Modifying the round hole material into Si through a control program, and then recalculating the FOM to obtain a new FOM value;
the purpose of converting the different materials in operations 1 and 2 is to change the material of the circular hole in the pixel, that is, the refractive index in the circular hole, so that the distribution of the refractive index in the device is successfully more regulated, and the value of the pixel corresponding to the changed circular hole position of the material is also changed. The material conversion is to control the change of the structural matrix by writing script, thus changing the structure of the device.
Comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the previous FOM value, reserving the structure conversion operation, and simultaneously updating the FOM into the FOM with the new structure, otherwise, keeping the FOM unchanged, and reserving the original structure;
step 4: a group of randomly generated 1-mn natural number sequences are sequentially endowed to each pixel of corresponding number sequences of the structural matrix, and larger FOM and corresponding structural matrix are sequentially compared and reserved according to the sequence from 1-mn to large, so that a round of optimized FOM and structural matrix are obtained;
since the m×n structural matrix corresponds to one material (Si or SiO 2 ) The total number of matrix elements is mn. If the structure matrix is needed to be used for obtaining the wanted structure, the structure is needed to be obtained after 2mn comparisons, but the method is time-consuming and labor-consuming and is difficult to be completed, so that the calculation time is greatly saved and the efficiency is improved by adopting the mode of the step 4.
Then, the FOM and the structure matrix of the round are used as the initial FOM and the structure matrix of the next round of optimization, and the row optimization is advanced, if the FOM is not changed after the optimization of a certain round, a local optimal solution is obtained at the moment, wherein the unchanged FOM refers to the FOM between two adjacent rounds, and after the optimization of a round, the value of the FOM is not changed, so that the optimal value is reached.
The method can be applied to designing any logic gate structure with multiple dimensions, and the following is a three-dimensional X gate designed by adopting the method of the embodiment.
As shown in FIG. 2, the three-dimensional X-gate structure obtained in this embodiment has a size of 3.6μm×1.8μm and an etching depth h of 220nm, wherein the size of the pixel is 150nm×150nm, and a circular hole with a diameter of 100nm is formed in the center of the pixel, and the reverse design structure region corresponds to a 24×12 structure matrix.
When the TE0 mode is input, the TE1 mode is output, the TE1 mode is input, the TE2 mode is output, and the TE0 mode is input, so that the X-gate operation is realized.
FIGS. 3-5 are transmission spectra of an input TE0 mode, TE1 mode and TE2 mode, respectively, and under 1540nm-1560nm wave band, the loss of converting TE0 mode into TE1 mode is <1dB, and the crosstalk is <22dB; the loss of converting the TE1 mode into the TE2 mode is <1.13dB, and the crosstalk is <21.24dB; the loss of the TE2 mode converted to TE0 mode is <0.73dB, and the crosstalk is <22.9dB.
By adopting the reverse design scheme of the invention, the refractive index distribution of the device region is changed continuously, so that the local optimum or global optimum solution is finally obtained, the precision of the structure is greatly improved, and the performance of the silicon-based sub-wavelength structure is improved.
Variations and modifications to the above would be obvious to persons skilled in the art to which the invention pertains from the foregoing description and teachings. Therefore, the invention is not limited to the specific embodiments disclosed and described above, but some modifications and changes of the invention should be also included in the scope of the claims of the invention. In addition, although specific terms are used in the present specification, these terms are for convenience of description only and do not constitute any limitation on the invention.
Claims (7)
1. An on-chip multidimensional logic gate design method based on a waveguide mode is characterized by comprising the following steps:
step 1: determining the size of a structural area and the initial value of a pixel point: the structural area is set to be an m multiplied by n structural matrix by adopting a reverse design method, a pixel point with a nm multiplied by a nm is arranged at the position corresponding to the structural matrix according to the serial number of the array, a round hole with a diameter of d nm is arranged at the center of the pixel point, and the round hole is made of Si or SiO 2 Different initial values are given according to different pixel points of the material;
step 2: calculating the proportion of each mode in the output ports of different input modes by using FDTD algorithm and the initial value given by each pixel point of m multiplied by n structural matrix, wherein the input and output modes are TE i And the FOM of this structure was evaluated using its constitution, the FOM expression is as follows:
wherein t is i 1 To input TE i Transmittance of target mode after mode, t i 2 To input TE i Transmittance of the latter other modes, alpha being the balance of loss and crosstalkFactor, m, is the number of modes, i=0, 1,2, …, m;
step 3: finding the corresponding position in the structure matrix according to the sequence number in the structure matrix array to perform structure conversion operation:
operation 1: if the material of the round hole in the corresponding position is Si, modifying the round hole material into SiO through a control program 2 Then recalculate the FOM to obtain a new FOM value;
operation 2: if the material of the round hole in the corresponding position is SiO 2 Modifying the round hole material into Si through a control program and then recalculating the FOM to obtain a new FOM value;
comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the previous FOM value, reserving the structure conversion operation, and meanwhile, updating the FOM into the FOM with the new structure, otherwise, reserving the FOM with the original structure;
step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel point of corresponding number sequences of the structural matrix, sequentially comparing and retaining FOM with large numerical value FOM in the comparison structure and the corresponding structural matrix according to the sequence from 1-mn to large, and obtaining a round of optimized FOM and structural matrix;
and then taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and advancing the row optimization, wherein if the FOM is unchanged after the round of optimization, the local optimal solution is obtained.
2. The method of designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 1, wherein an initial value of a pixel point is set to 0 or 1.
3. The method for designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 1, wherein the m and n values in the m x n structural matrix range from 10 to 50.
4. The method of on-chip multi-dimensional logic gate design based on waveguide mode according to claim 1, wherein the value of a in the pixel of a nm x a nm is in the range of 80nm-220nm.
5. The method for designing the on-chip multidimensional logic gate based on the waveguide mode as recited in claim 1, wherein the diameter d of the round hole is in the range of 60nm-150nm.
6. A method of designing a multi-dimensional logic gate on a chip based on a waveguide mode as claimed in claim 1, wherein the size of the structural region is 2.5-4.5 μm x 1-2.5 μm.
7. The method for designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 6, wherein the etching depth h of the structural region is 150-250nm.
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