CN113542642A - Analog-to-digital converter for locally generating reference voltage of sub-digital-to-analog converter - Google Patents
Analog-to-digital converter for locally generating reference voltage of sub-digital-to-analog converter Download PDFInfo
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Abstract
The invention relates to the field of analog integrated circuit design, and aims to change the mode that a voltage source directly provides reference voltage for a sub-digital-analog converter in an ADC structure in the prior art into a mode of locally generating the reference voltage of the sub-digital-analog converter in each column of ADC, thereby avoiding crosstalk between columns of a readout circuit, reducing noise and improving precision. The invention is an analog-digital converter for locally generating the reference voltage of a sub-digital-analog converter, wherein the input of each sub-digital-analog converter is connected with a digital code output by a corresponding sub-analog-digital converter, and the digital code determines the theoretical reference voltage output by the sub-digital-analog converter; the sampling capacitors and the operational amplifier form a multiplying-by-two amplifying circuit, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the one group of sampling capacitors is connected with the actual reference voltage, namely the output of the sub-digital-to-analog converter. The invention is mainly applied to the design and manufacture occasions of the analog integrated circuit.
Description
Technical Field
The field of analog integrated circuit design, in particular to the field of design of image sensing reading circuits. And more particularly to sub-digital-to-analog converter arrangements in analog-to-digital converters.
Background
Pixels of the image sensor can sense optical signals and output Analog electrical signals, but Digital signals are required to be processed to acquire image information, so that an Analog-to-Digital Converter (ADC) plays a crucial role in the image sensor. The common ADC of the image sensor is mainly divided into a chip-level ADC, a column-level ADC and a pixel-level ADC, wherein the chip-level ADC means that all pixels share one ADC, has higher requirement on the working speed of the ADC and is generally used for a reading circuit of a small-scale pixel array; the column-level ADC means that each column of pixels shares one ADC, the requirement on the speed of the ADC is relatively low, and the design difficulty is relatively small; the pixel level ADC is an ADC integrated with each pixel or several adjacent pixels, and has the advantages of high signal-to-noise ratio, increased chip area and power consumption, and reduced pixel fill factor. There are four main types of column-level ADCs in common use today: a Single-Slope ADC (SS-ADC), an oversampling ADC (sigma-delta ADC), a Successive Approximation ADC (SA ADC), and a cyclic ADC (cyclic ADC). The four ADCs have different working principles and have advantages and disadvantages, wherein the Cyclic ADC has the advantages of higher speed, strong precision expansibility and the like compared with other ADCs, the two-stage parallel Cyclic ADC is adopted to further improve the data conversion speed, the first-stage Cyclic ADC is used for carrying out high-effective bit quantization, the second-stage Cyclic ADC is used for carrying out low-effective bit quantization on the residual voltage of the first stage, the two-stage quantization is carried out simultaneously, and the data conversion speed and the conversion bit number are improved compared with a single-stage ADC.
The structural schematic diagram of a column-level Cyclic ADC is shown in the attached figure 1, and the structure mainly comprises: a sample and hold circuit, a precise two-by-two circuit, a sub-digital-to-analog converter, a summation circuit, a sub-digital-to-analog converter. The working principle is as follows: firstly, a switch 1 is closed, a switch 2 is disconnected, an ADC enters a sampling state, a sample-hold circuit collects an analog voltage Vin to be quantized, then the Vin is sent to a comparator and an accurate multiplication circuit, if the comparator outputs a high level, the most significant digit code is 1, if the comparator outputs a low level, the most significant digit code is 0, and the Vin is multiplied by two and then summed with a reference voltage; then the switch 1 is opened, the switch 2 is closed, the residual difference voltage output by the summing circuit is collected by the sampling holding circuit, comparison and multiplication-by-two summation are carried out, secondary high-order quantization is completed, and the operations on the residual difference voltage are repeated until the lowest order quantization is completed. The column-level Cyclic ADC completes the operation of multiplying two times and amplifying voltage through the switched capacitor circuit and the operational amplifier, and the reference voltage connected with the capacitor is determined according to the digital code of the last conversion result when each bit of data is converted. The schematic diagram of the connection mode between the multi-column Cyclic ADC and the reference voltage is shown in fig. 2, the reference voltage of the Cyclic ADC has two conditions, namely a high reference voltage VR + and a low reference voltage VR-, under the condition that the array of the readout circuit is large, the reference voltage is simultaneously connected with the sample-and-hold circuits of the multi-column ADC, and the capacitors in the sample-and-hold circuits of the multi-column ADC are charged and discharged at the same time, which causes noise, instability and crosstalk between columns of the readout circuit to increase. In order to solve the above problems, it is necessary to change the way in the prior art that a voltage source directly provides a reference voltage for the sub-digital-to-analog converter in the ADC structure, and to locally generate the reference voltage for the sub-digital-to-analog converter in each column of the ADC, thereby avoiding crosstalk between columns of the readout circuit, reducing noise, and improving accuracy.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to change the mode that a voltage source directly provides reference voltage for the sub-digital-to-analog converter in the ADC structure in the prior art into a mode of locally generating the reference voltage of the sub-digital-to-analog converter in each column of the ADC, thereby avoiding crosstalk between columns of a reading circuit, reducing noise and improving precision. The technical scheme includes that the analog-digital converter locally generates sub digital-to-analog converter reference voltage, the input of each sub digital-to-analog converter is connected with a digital code output by a corresponding sub analog-to-digital converter, and the digital code determines the theoretical reference voltage output by the sub digital-to-analog converter; the sampling capacitors and the operational amplifier form a multiplying-by-two amplifying circuit, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the one group of sampling capacitors is connected with the actual reference voltage, namely the output of the sub-digital-to-analog converter.
And the capacitor 1+ and the capacitor 1-are sampling capacitors of an accurate multiplication two-circuit of the Cyclic ADC, wherein one end of the capacitor 1+ is connected with a non-inverting input end of the operational amplifier, the other end of the capacitor 1+ is connected with an output 2 of the sub-digital-to-analog converter, one end of the capacitor 1-is connected with an inverting input end of the operational amplifier, and the other end of the capacitor 1-is connected with an output 1 of the sub-digital-to-analog converter.
The logic control circuit in the sub-analog-digital converter determines the magnitude of reference voltage in the current analog-digital conversion period according to digital codes output by the sub-analog-digital converter, a comparator in the sub-analog-digital converter judges the magnitude relation between actual reference voltage and theoretical reference voltage output by the sub-analog-digital converter, if the voltage of a sampling end of a sampling capacitor is smaller than the reference voltage required by the conversion, a switch connecting a column current source and the sampling capacitor is closed, a switch connecting a power ground and the sampling capacitor is disconnected, and the sampling capacitor is charged by a current source; if the current voltage of the sampling end of the sampling capacitor is larger than the reference voltage required by the conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor discharges to the ground, the charging current and the discharging current are equal in magnitude, namely the charging and discharging speeds of the two sampling capacitors are the same, and therefore the common-mode voltage of the sampling capacitor is guaranteed to be stable.
The sub-digital-to-analog converter is composed of a four-input comparator, a logic control circuit, switches 1-4, a power ground, a current source 1 and a current source 2, wherein the input of the logic control circuit is connected with the output of the preceding stage sub-digital-to-analog converter, the output of the logic control circuit is a theoretical reference voltage, and the theoretical reference voltage is connected with the input end of the comparator; the current source 1 is connected to the output 1 of the sub-digital-to-analog converter through the switch 1, and the power ground is also connected to the output 1 of the sub-digital-to-analog converter through the switch 3, and the current source 2 is connected to the output 2 of the sub-digital-to-analog converter through the switch 2, and the power ground is also connected to the output 2 of the sub-digital-to-analog converter through the switch 4; the on-off of the switches 1-4 is controlled by the output signals of the four-input comparator, one pair of input ends of the four-input comparator are respectively connected with the output 1 and the output 2 of the sub-digital-to-analog converter, namely the actual digital-to-analog conversion result, and the other pair of input ends of the four-input comparator are respectively connected with the theoretical reference voltage vref1 and the reference voltage vref2 output by the logic control circuit.
The invention has the characteristics and beneficial effects that:
the reading circuit described by the invention improves the traditional Cyclic ADC, adopts a current source to charge and discharge the capacitor of the Cyclic ADC, and the sub-digital-to-analog converters of each column of ADCs are mutually independent and have no interference, so that the problem of reduced ADC column consistency caused by insufficient driving capability of reference voltage when the array of the reading circuit based on the column parallel Cyclic ADC is larger can be solved, and the result of analog-to-digital conversion is ensured to have high enough precision.
Description of the drawings:
fig. 1 is a schematic diagram of a column-level Cyclic ADC.
FIG. 2 is a schematic diagram of the connection between a multi-column Cyclic ADC and a reference voltage.
Fig. 3 is a schematic diagram of the structure of the sub-digital-to-analog converter described in the present invention.
FIG. 4 is a schematic diagram of a Cyclic ADC using the sub-DAC described in the present invention.
Detailed Description
The invention provides a Cyclic ADC sub-digital-analog converter structure locally generating reference voltage, which is characterized in that a current source is used for charging sampling capacitors of each row of reading circuits respectively, and the charging is stopped when the actual reference voltage reaches a theoretical value, so that the problem of poor ADC row consistency caused by insufficient charging driving capability of a voltage source on a plurality of rows of sampling capacitors at the same time can be avoided.
When the array of the Cyclic ADC reading circuit is large, the reference voltage needs to be charged and discharged to the sampling capacitor of each row of ADC accurate multiplication two circuits at the same time in each data conversion process, the capacitance value generated by the parallel connection of each row of capacitors is large, the voltage value of the reference voltage is limited, the row consistency of the reading circuit is poor due to insufficient voltage driving capability, in order to avoid the problem that the error of an analog-to-digital conversion result is large due to the insufficient charging and discharging of the reference voltage to the capacitors, the mode of generating the reference voltage by adopting a voltage source in the prior art is changed into the mode of locally generating the reference voltage by a current source, the working principle schematic diagram is shown in figure 3, the structural schematic diagram of the Cyclic ADC adopting the sub-digital-analog converter shown in figure 3 is shown in figure 4, a capacitor 1+ and a capacitor 1-are the sampling capacitor of the Cyclic ADC accurate multiplication two circuits, wherein one end of the capacitor 1+ is connected with the in-phase input end of an operational amplifier, the other end of the capacitor 1-is connected with the output 2 of the sub-digital-to-analog converter, one end of the capacitor is connected with the inverting input end of the operational amplifier, and the other end of the capacitor is connected with the output 1 of the sub-digital-to-analog converter. The working process of the sub-digital-to-analog converter is as follows: the logic control circuit determines the reference voltage in the current analog-digital conversion period according to the digital code output by the sub analog-digital converter; the comparator judges the magnitude relation of the actual reference voltage and the theoretical reference voltage output by the sub digital-to-analog converter, four input ends of the four-input comparator are respectively connected with the voltage of the sampling ends of the two sampling capacitors, namely the actual reference voltage and the two theoretical reference voltages output by the logic control circuit, when the voltage difference of the two sampling capacitors reaches the difference value of the two theoretical reference voltages, the output level of the comparator is overturned, and the overturning level controls all switches to be switched off; if the voltage of the sampling end of the sampling capacitor is less than the reference voltage required by the conversion, the switch for connecting the column current source and the sampling capacitor is closed, the switch for connecting the power ground and the sampling capacitor is disconnected, and the sampling capacitor is charged by the current source; if the current voltage of the sampling end of the sampling capacitor is larger than the reference voltage required by the conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor discharges to the ground, the charging current and the discharging current are equal in magnitude, namely the charging and discharging speeds of the two sampling capacitors are the same, and therefore the common mode value of the actual reference voltage is guaranteed to be stable. The mode of locally generating the reference voltage does not need a voltage source to participate in the dynamic process of charging and discharging the capacitor, and the coupling effect between ADC columns cannot be generated.
The structure shown in figure 3 adopts a four-input comparator, which has the advantages that each row of reading circuit only needs one comparator, the layout area is small, two-input comparators can be used for replacing the four-input comparator, the sampling end-to-ground voltage and the single-end reference voltage of two sampling capacitors are respectively compared, the power consumption of the two-input comparators is similar to that of the four-input comparator, the two-input comparator has the advantages that the charging and discharging currents with the same size are not needed, and the working principle is simple.
Firstly, the device or the module connected with the input end and the output end of the sub digital-to-analog converter is explained: the input of each sub-digital-to-analog converter is connected with a digital code output by a corresponding sub-analog-to-digital converter, and the digital code determines the theoretical reference voltage output by the sub-digital-to-analog converter; the sampling capacitors and the operational amplifier form a multiplication-two amplifying circuit in the Cyclic ADC, and when the Cyclic ADC works, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the sampling capacitors is connected with actual reference voltage, namely the output of the sub-digital-analog converter. The internal structure and working principle of the sub-digital-to-analog converter are explained next: the sub-digital-to-analog converter is composed of a four-input comparator, a logic control circuit, switches 1-4, a power ground, a current source 1 and a current source 2, wherein the input of the logic control circuit is connected with the output of the preceding stage sub-digital-to-analog converter, the output of the logic control circuit is a theoretical reference voltage, and the theoretical reference voltage is connected with the input end of the comparator; the current source 1 is connected to the output 1 of the sub-digital-to-analog converter through the switch 1, and the power ground is also connected to the output 1 of the sub-digital-to-analog converter through the switch 3, and the current source 2 is connected to the output 2 of the sub-digital-to-analog converter through the switch 2, and the power ground is also connected to the output 2 of the sub-digital-to-analog converter through the switch 4; the on-off of the switches 1-4 is controlled by the output signal of the four-input comparator, a pair of input ends of the four-input comparator are respectively connected with the output 1 and the output 2 of the sub-digital-to-analog converter, namely the actual digital-to-analog conversion result, the other pair of input ends of the four-input comparator are respectively connected with the theoretical reference voltage vref1 and the reference voltage vref2 output by the logic control circuit, the four-input comparator compares the theoretical value and the actual value of the reference voltage, when the actual reference voltage is less than the theoretical reference voltage, the switch connected with the current source is conducted, charging the sampling capacitor of the second-stage multiplying amplifying circuit, turning on the switch connected to the power ground when the actual reference voltage is greater than the theoretical reference voltage, discharging the sampling capacitor with the same charging current and discharging current, the charging and discharging speeds of the two sampling capacitors are the same, so that the common-mode value of the actual reference voltage output by the sub-digital-to-analog converter can be kept stable.
FIG. 1 represents: the invention provides an innovative structure of a neutron digital-to-analog converter shown in figure 1, and provides an overall structural schematic diagram of a Cyclic ADC (analog-to-digital converter), which illustrates the main modules of the Cyclic ADC and the connection mode among the modules.
FIG. 2 represents: the multi-column Cyclic ADC is connected with a reference voltage VR + and a reference voltage VR-in work, and because the sampling capacitor of the Cyclic ADC is directly connected with the reference voltage, the reference voltage is equivalent to charge and discharge of a plurality of capacitors connected in parallel, the driving capability of the reference voltage is limited, and the precision of the Cyclic ADC is reduced.
FIG. 3 represents: the specific structure of the sub-digital-to-analog converter provided by the invention is in a dashed line frame, and the input end and the output end of the sub-digital-to-analog converter are outside the dashed line frame.
The working principle of the invention is as follows: the Cyclic ADC adopting the sub-digital-to-analog converter provided by the invention is shown in figure 4, a capacitor 1+ and a capacitor 1-are sampling capacitors of an accurate two-by-two circuit of the Cyclic ADC, wherein one end of the capacitor 1+ is connected with a non-inverting input end of an operational amplifier, the other end of the capacitor 1+ is connected with an output 2 of the sub-digital-to-analog converter, one end of the capacitor 1-is connected with an inverting input end of the operational amplifier, and the other end of the capacitor 1-is connected with an output 1 of the sub-digital-to-analog converter. The working process of the sub-digital-to-analog converter is as follows: the logic control circuit determines the size of a reference voltage in the current analog-digital conversion period according to a digital code output by the sub analog-digital converter, the comparator judges the size relation between the actual reference voltage output by the sub analog-digital converter and the theoretical reference voltage, if the voltage of the sampling end of the sampling capacitor is less than the reference voltage required by the conversion, a switch connecting the column current source and the sampling capacitor is closed, a switch connecting the power ground and the sampling capacitor is opened, and the sampling capacitor is charged by the current source; if the current voltage of the sampling end of the sampling capacitor is larger than the reference voltage required by the conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor discharges to the ground, the charging current and the discharging current are equal in magnitude, namely the charging and discharging speeds of the two sampling capacitors are the same, and therefore the common-mode voltage of the sampling capacitor is guaranteed to be stable. The mode of locally generating the reference voltage does not need a voltage source to participate in the dynamic process of charging and discharging the capacitor, and the coupling effect between ADC columns cannot be generated.
In order to more intuitively express the implementation conditions, advantages, and the like of the present invention, embodiments of the present invention are described below with reference to examples. The reading circuit described in the present invention is applied to a TOF image sensor with a 1920-column and 1080-row pixel array, the frame frequency of the TOF image sensor is 300FPS (Frames per Second), the quantization bit number is 10 bits, the clock frequency is 250MHz (megahertz), a Cyclic ADC encoded by RSD (Redundant bit) is adopted, the single-ended input voltage range of the Cyclic ADC is 1.05V (volt) -2.25V, the input voltage common-mode value is 1.65V, the ADC quantization range is-1.2V- +1.2V, the reference voltage of the Cyclic ADC is a high reference voltage VR +/2.25V, and the low reference voltage VR- + 1.05V, respectively. The operational amplifier in the Cyclic ADC adopts a folded cascode operational amplifier structure, the comparator in the sub-analog-digital converter adopts a dynamic latch comparator structure, and the threshold voltage of the comparator is +0.3V and-0.3V. The data conversion time of each column of reading circuits is 3us (microseconds), the conversion time of each bit of the Cyclic ADC is 300ns (nanoseconds), and if the input voltage of the non-inverting terminal of the Cyclic ADC is 2V and the input voltage of the inverting terminal of the Cyclic ADC is 1.3V, the difference of the input voltages is 0.7V. The structure of the Cyclic ADC is shown in figure 4, voltages collected by a capacitor 1+, a capacitor 1-, a capacitor 2+ and a capacitor 2-are respectively 2V and 1.3V within 0-300 ns, and a 1.5-bit digital code output by the sub-analog-digital converter is 10 of a binary system; the Cyclic ADC enters the next quantization period within 300-600 ns, at the moment, a capacitor 2+ and a capacitor 2-acquire the output voltage of the operational amplifier, two polar plates of the capacitor 1+ and the capacitor 1-are respectively connected with the input end of the operational amplifier and the reference voltage, the reference voltages required to be connected of the capacitor 1+ and the capacitor 1-are respectively 2.25V and 1.05V according to the digital code obtained in the previous quantization period, a logic circuit controls the capacitor 1+ to be connected with a column current source for charging, the capacitor 1-is connected with a power ground for discharging, the charging and discharging speeds of the capacitor 1+ and the capacitor 1-are the same, the common mode voltage is kept at 1.65V, when the voltages of the capacitor 1+ and the capacitor 1-are respectively charged and discharged to reach 2.25V and 1.05V through charging and discharging, the output level of the four-input comparator is inverted, all switches connected with the column current source and the ground are turned off, the charging and discharging of the sampling capacitor is stopped, the output voltage of the operational amplifier is changed into 0.2V after being multiplied by two and subtracted by 1.2V, and the voltages to earth of the capacitor 2+ and the capacitor 2-are 1.75V and 1.55V respectively; within a time period of 600 ns-900 ns, the positions of two groups of sampling capacitors, namely a capacitor 1+, a capacitor 1-and a capacitor 2+ and a capacitor 2-are exchanged, at the moment, the capacitor 1+ and the capacitor 1-acquire the output voltage of the operational amplifier, the capacitor 2+ and the capacitor 2-are connected with the input end of the operational amplifier and the reference voltage, because-0.3V is less than 0.2V and less than 0.3V, the reference voltage required to be connected between the capacitor 2+ and the capacitor 2-is 1.65V, at the moment, the capacitor 2+ is connected with a power ground to discharge, the capacitor 2-is connected with a column current source to charge, the charging and discharging speeds of the capacitor 1+ and the capacitor 1-are the same, the common mode voltage is kept at 1.65V, when the voltages of the capacitor 1+ and the capacitor 1-are charged and discharged to 1.65V, the output levels of the four-input comparator are inverted, all switches connected with the column current source and the ground are turned off, the sampling capacitors are stopped to charge and discharge the sampling capacitors, the output voltage of the operational amplifier is changed into 0.4V by multiplying two and subtracting 0V reference voltage; then the operational amplifier circuit multiplies the residual voltage output by the operational amplifier by two, amplifies and compares until finishing the 10-bit quantization. The sampling capacitor of the Cyclic ADC is charged by the column-level current source in the conversion process, the charging time of the column-level current source is controlled by the comparator according to the voltages at two ends of the capacitor and the reference voltage which should be accessed in the conversion, the reference voltage of each column of ADC is locally generated, and the columns are mutually independent, so that the problems of coupling and crosstalk caused by the fact that all rows share the reference voltage and the reference voltage is insufficient in driving capability are avoided, and the reading circuit is guaranteed to have higher precision.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. An analog-digital converter for locally generating a reference voltage of a sub-digital-analog converter is characterized in that the input of each sub-digital-analog converter is connected with a digital code output by a corresponding sub-analog-digital converter, and the digital code determines the theoretical reference voltage output by the sub-digital-analog converter; the sampling capacitors and the operational amplifier form a multiplying-by-two amplifying circuit, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the one group of sampling capacitors is connected with the actual reference voltage, namely the output of the sub-digital-to-analog converter.
2. The analog-to-digital converter for locally generating reference voltages of sub-digital-to-analog converters as claimed in claim 1, wherein the capacitor 1+ and the capacitor 1-are sampling capacitors of a precise two-by-two circuit of a Cyclic ADC, wherein one end of the capacitor 1+ is connected to the non-inverting input terminal of the operational amplifier, the other end is connected to the output 2 of the sub-digital-to-analog converter, one end of the capacitor 1-is connected to the inverting input terminal of the operational amplifier, and the other end is connected to the output 1 of the sub-digital-to-analog converter.
3. The analog-to-digital converter for locally generating reference voltage of a sub-digital-to-analog converter according to claim 1, wherein a logic control circuit in the sub-analog-to-digital converter determines the magnitude of the reference voltage in the current analog-to-digital conversion period according to the digital code output by the sub-analog-to-digital converter, a comparator in the sub-analog-to-digital converter determines the magnitude relation between the actual reference voltage and the theoretical reference voltage output by the sub-digital-to-analog converter, if the voltage of the sampling end of the sampling capacitor is less than the reference voltage required by the conversion, a switch connecting the column current source and the sampling capacitor is closed, a switch connecting the power ground and the sampling capacitor is opened, and the sampling capacitor is charged by the current source; if the current voltage of the sampling end of the sampling capacitor is larger than the reference voltage required by the conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor discharges to the ground, the charging current and the discharging current are equal in magnitude, namely the charging and discharging speeds of the two sampling capacitors are the same, and therefore the common-mode voltage of the sampling capacitor is guaranteed to be stable.
4. The analog-to-digital converter for locally generating the reference voltage of the sub-digital-to-analog converter according to claim 1 or 3, wherein the sub-digital-to-analog converter is composed of a four-input comparator, a logic control circuit, switches 1 to 4, a power ground, a current source 1 and a current source 2, the input of the logic control circuit is connected with the output of the preceding sub-analog-to-digital converter, the output of the logic control circuit is a theoretical reference voltage, and the theoretical reference voltage is connected with the input end of the comparator; the current source 1 is connected to the output 1 of the sub-digital-to-analog converter through the switch 1, and the power ground is also connected to the output 1 of the sub-digital-to-analog converter through the switch 3, and the current source 2 is connected to the output 2 of the sub-digital-to-analog converter through the switch 2, and the power ground is also connected to the output 2 of the sub-digital-to-analog converter through the switch 4; the on-off of the switches 1-4 is controlled by the output signals of the four-input comparator, one pair of input ends of the four-input comparator are respectively connected with the output 1 and the output 2 of the sub-digital-to-analog converter, namely the actual digital-to-analog conversion result, and the other pair of input ends of the four-input comparator are respectively connected with the theoretical reference voltage vref1 and the reference voltage vref2 output by the logic control circuit.
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