CN113541974A

CN113541974A - Multi-channel high-frequency digital signal synchronous processing device

Info

Publication number: CN113541974A
Application number: CN202110730494.9A
Authority: CN
Inventors: 刘盛利; 宋皓杰; 张艳如
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2021-10-22
Anticipated expiration: 2041-06-30
Also published as: CN113541974B

Abstract

The multi-channel high-frequency digital signal synchronous processing device disclosed by the invention has the advantages of multiple channels, high speed, easiness in expansion and convenience in debugging. The invention is realized by the following technical scheme: the control circuit is connected with an LRM connector and message transmission outside through a discrete line, controls the power supply conversion circuit to be electrified and controlled by a RapidIO physical layer, enables the versions of 1-4 DSPs to work, controls the version management of the DSPs and the acquisition of temperature and voltage, uses a network line and the DSPs to exchange data by the Ethernet circuit, receives the data by the network exchange circuit, distributes the data to the DSPs for program loading and updating, debugs the DSP signals by the Ethernet circuit, receives input differential signals by the processing circuit, continuously transmits multi-channel high-frequency digital signal synchronous processing data to a USB endpoint receiving cache of hardware equipment, and then transmits the data to an upper computer, and USB external equipment directly accesses the data cache area to transmit the byte number and the address of the cache area of the data.

Description

Multi-channel high-frequency digital signal synchronous processing device

Technical Field

The invention relates to a multi-channel high-frequency digital signal synchronous processing device which is widely applied to the fields of aviation, communication and the like.

Background

With the rapid development of electronic technology, digital signal processing technology and automation, the acquisition of signals is shifted from mechanization to intellectualization and is continuously developed towards automation and intellectualization, signal monitoring equipment is also developed towards miniaturization, multifunctionalization and low power consumption, and the sampling frequency and resolution ratio are gradually improved. As the complexity of the detection and control devices increases, the requirements and standards for the signal processing device modules increase. In many signal processing devices, it is desirable to be able to process as many signal channels as possible in real time and at high speed. The acquisition monitoring device adopting the high-performance micro control chip, the high-precision AD chip and the matched front-end signal conditioning circuit is widely applied. The data transmission between the PC upper computer application program and the external hardware equipment is realized by writing related equipment driving programs through the peripheral hardware equipment. Since the signal processing apparatus needs to process a large amount of signals, it has a relatively high demand on the performance of the microcontroller in terms of data processing capability, processing speed, and the like. If microcontrollers with different performance are selected, the peripheral devices and circuits also have performance indicators that match them. The maximum channel number of the signals which can be collected by the tasks and indexes of the signal collecting device is 16; the amplitude range of the input signal is dozens of microvolts to dozens of millivolts; the frequency range of the collected signals is below 100 Hz; the bit number of the A/D conversion chip is 16 bits. Data transmission between the microcontroller and the upper computer PC is usually realized by a USB bus. The microcontroller controls the A/D conversion chip to collect signals through the SPI bus and transmits data to the microcontroller through the SPI. Since the interconnection between DSPs or between a DSP and a host is typically made using HPI (HostPortInterface) or PCI. Their main disadvantages are: the bandwidth is small; a plurality of signal lines; master-slave mode interface, not supporting peer-to-peer transmission. Additionally, the DSP cannot directly perform backplane transmission.

DSP is a professional basic course oriented to electronic information discipline, and its basic concept and basic analysis method have penetrated the fields of information and communication engineering, circuits and devices, integrated circuit engineering, biomedical engineering, physics electronics, navigation, guidance and control, electromagnetic field and microwave technology, underwater acoustic engineering, electrical engineering, power engineering, aeronautical engineering, environmental engineering, etc. Digital signal processing is a ubiquitous problem, and information science has penetrated all fields of modern natural science and social science. Before and after the digital signal processing, some auxiliary circuits are needed, which form a device together with the digital signal processor. High-speed real-time signal processing is a special branch of signal processing. The method is mainly characterized by high-speed processing and real-time processing, and is widely applied to the key fields of industry, aviation and communication, such as radar signal processing, communication base station signal processing and the like. The high-speed digital signal processing technology is an information processing technology which takes a DSP as a core and has the characteristics of high speed and real time. Its essence is the transformation and extraction of information. The high-speed real-time signal processing technology includes, in addition to the core high-speed DSP technology, many peripheral technologies, such as peripheral device technologies like ADC and DAC, and device bus technology. With the development and application of Digital Signal Processors (DSPs) in various fields of signal processing; DSP applications have evolved in various aspects of computer, communication, and digital video and audio technologies. The DSP is a programmable chip specially used for digital signal processing, is a microprocessor especially suitable for digital signal processing operation, and is mainly used for rapidly realizing various digital signal processing algorithms in real time. The essence of signal processing is the transformation and extraction of information, which is extracted from various noisy, noisy environments and transformed into a form that is convenient for human or machine use. The digital signal processing unit is actually a computer that performs calculations on binary digital signals according to instructions. Amplitude modulation can be achieved, for example, by multiplying the acoustic wave signal with a high frequency sine wave signal. In practice, the digital signal is often converted back to an analog signal to perform its function. For example, radio is an electromagnetic wave that is radiated outward through an antenna, and in this case, the electromagnetic wave is only an analog signal. Analog signals are encountered in most science and engineering. The theory and implementation of analog signal processing have been studied in the past. The analog signal processing has the defects of difficult high precision, great influence by environment, poor reliability, inflexibility and the like. In a sense, signal processing is similar to the process of "sand panning" in that it does not increase the amount of information (i.e., does not increase the gold content), but extracts the information (i.e., gold) from various noisy, noisy environments (i.e., scattered in sand) and converts it to a usable form (e.g., gold bars, etc.). Without such a transformation, the information, although present, is not available, just as gold scattered in sand cannot be directly used. There are a number of classification approaches for DSPs. The DSP is divided into a fixed-point processor (such as ADSP218x/9x/BF5xx of ADI, TMS320C62/C64 of TI) and a floating-point processor (such as SHARC/Tiger SHARC device of ADI, TMS320C67 of TI) according to data type classification. The radar signal processing device has high requirements on a DSP (digital signal processor), and a high-end DSP with 32 bits is usually used; and the floating-point DSP can better meet the requirement of the radar signal on large dynamic range. Although the DSP has many chip series and different instruction devices, the main features of the DSP are similar, such as fast operation speed, powerful chip functions and few peripheral devices. However, they also have the problem that development and programming are more complicated than that of a single chip microcomputer. Therefore, although the single-chip microcomputer is powerful, the single-chip microcomputer needs to be popularized in a large scale and enter the industrial and consumption fields occupied by the traditional single-chip microcomputer. Currently, the current practice is. The general DSP signal processing device has few signal processing paths and low speed, and is difficult to meet the requirements of high-speed and large-capacity data processing. Different applications of DSPs also differ. Early DSPs were fixed-point, and their cost was low enough to handle most of the digital signal processing, but in some cases, such as radar-sonar signal processing, the dynamic range of data was large, and data overflow or underflow occurred in fixed-point processing, and in severe cases, processing could not be performed. The floating-point DSP solves the problem, expands the dynamic range of data of 38385of 32-bit floating-point number of 1536dB, is only provided with larger access space, and is mainly oriented to the floating-point DSP, such as a C compiler of ADSP2106x, and directly compiles a C program and then puts the compiled program on the DSP to run, thereby simplifying the process of compiling the program. In order to break through the limitation of data processing and take the use requirements of platforms such as an airborne platform, a ship-borne platform and an aircraft-borne platform into consideration, the signal processing device can be flexibly and widely applied to different fields such as radar, satellite communication and data links, the volume power consumption of the signal processing device needs to be reduced by improving the integration level, and the barrier of generalization of multiple platforms is broken through the compatibility design.

High-speed signal processing is widely applied to various fields, and along with rapid development of scientific technology, the performance requirements on a signal processing device are higher and higher. In the field, the research and industrialization of China are started late, most domestic manufacturers rely on import equipment, the price is high, the function flexibility is insufficient, and the existing signal processing device has the defects of few processing channels, small dynamic receiving range, poor flexibility and pertinence and the like. In a traditional analog receiver, an analog quadrature mixer is difficult to achieve a strict 90-degree phase difference, and I/Q two-path amplifier filters are almost impossible to achieve the same. Some existing high-speed processing cards are limited in application scenes, must be used with a whole set of equipment, and have the defects of few processing channels, low processing speed, poor flexibility and pertinence and the like.

Disclosure of Invention

Aiming at the problems, the invention provides a multi-channel high-frequency digital signal synchronous processing device which has multiple channels, high speed, easy expansion and convenient debugging and accurate and reliable signal processing, so as to solve the problems of few channels, low speed, inconvenient debugging, long design period, incapability of multiplexing and expanding, insufficient reliability verification and the like in the traditional signal processing.

The above object of the present invention can be achieved by a multichannel high frequency digital signal synchronous processing apparatus comprising: the encapsulation is in the box body 3 of upper and lower apron 5, with multichannel signal processing daughter card 2 mutual data's multichannel signal processing support plate 4 and through the LRM connector of discrete line to external connection PC host computer, its characterized in that: digital signal processors DSP1, DSP2, DSP3 and DSP4 which are communicated with an Ethernet circuit, a network switching circuit and a control circuit are arranged on the multichannel signal processing daughter card 2 and the multichannel signal processing carrier plate 4, wherein the DSP1 and the DSP2 form the multichannel signal processing daughter card 2, and the DSP3 and the DSP4 are communicated with the Ethernet circuit, the network switching circuit, the control circuit and the power supply conversion circuit to form the multichannel signal processing carrier plate 4; the Ethernet circuit is externally connected with functional equipment through the SGMII and LRM connector, and transmits communication data through the SGMII and 1-4 Digital Signal Processors (DSP) through a serial link; the network switching circuit carries out the communication between the boards based on the open interconnection technical standard RapidIO protocol architecture of the data packet exchange, the RapidIO protocol architecture establishes the basis with the packet format, the interconnection topological structure and the serial RapidIO physical layer specification-the interconnection architecture for the standard sRIO function of the baseband, and the transmission layer is externally connected with the LRM connector and the 1-4 digital signal processors DSP for transmitting serial differential analog signals by defining the logic layer of the operation protocol and defining the packet exchange, routing and addressing mechanism; the control circuit controls the power supply conversion circuit to be powered on and version controlled through a RapidIO physical layer defining electrical characteristics, link control and error correction retransmission, enables versions of 1-4 DSPs to work independently and/or all to be powered on to work independently and other chips, controls version management and temperature and voltage acquisition of the 4 DSPs, an Ethernet circuit uses a network cable and 1-4 DSPs to exchange data, the network exchange circuit receives the data, distributes the data to 1-4 DSPs for program loading and updating, the Ethernet circuit debugs 1-4 DSP signals, a processing circuit receives input differential signals, then transmits multi-channel high-frequency digital signal synchronous processing data to a USB endpoint receiving buffer of hardware equipment in an interrupt mode and then transmits the data to an upper computer, the USB external device directly accesses the data buffer area, and the byte number and the buffer area address of the transmission data are stored.

Compared with the prior art, the invention has the beneficial effects that:

multiple channels, high speed and easy expansion. The invention adopts the LRM connector which is externally connected with the PC host through the discrete line pair, and the Ethernet circuit, the network switching circuit, the control circuit and the power supply switching circuit which are used for transmitting and communicating data between the signal processing circuit and the microcontroller, and comprises 32 paths of signal processing, thereby having high speed, easy expansion and easy large-scale integration. Each signal may operate at a frequency of 1 GHz. The 16-path signal processing adopts the design of the daughter card 2, the 16-path signal processing adopts the design of the carrier plate 4, the power consumption is low, the precision is high, the reliability is high, the flexibility is high, and only the 16-path signal processing of the carrier plate 4 can be used. The problems that the traditional signal processing channel is few, the speed is low, the debugging is inconvenient, the design period is long, the multiplexing cannot be realized, the expansion cannot be realized, the reliability verification is insufficient and the like are solved.

Multiple channels and high speed. The invention adopts a signal processing circuit comprising a digital signal processor DSP1, a DSP2, a DSP3 and a DSP4, wherein each DSP comprises 8 cores, each core can work independently, and 4 DSPs can process 32 paths of data simultaneously. The DSP1 and the DSP2 form a multi-channel signal processing daughter card 2, and the DSP3, the DSP4, the Ethernet circuit, the network switching circuit, the control circuit and the power switching circuit form a multi-channel signal processing carrier board 4; the network switch circuit may distribute external data to the 4 DSPs for program load updates. The ethernet circuit is used to debug 4 DSPs. The control circuit is used for controlling the power-on of other chips, version management of 4 DSPs and acquisition of temperature and voltage, the power supply conversion circuit provides voltage required by other chips, 32-channel signal processing can be provided, and the power supply conversion circuit is high in reliability, easy to expand and adaptive to different signal processing platforms. The integration level is high, the dependable performance. The invention exchanges data through serial link SGMII and 4 digital signal processors DSP; the network switching circuit is externally connected with an LRM connector and 4 Digital Signal Processor (DSP) interactive data through an SRIO (serial differential input/output) of a RapidIO standard transmitted by adopting a serial differential analog signal; data can be sent to any processor which is interconnected through the SRIO switch by using SRIO (SerialRapidIO), so that load balance of each processor is achieved, and the overall processing capacity of the device is more effectively utilized. The problems of small bandwidth, more signal lines, master-slave mode interfaces and no support of peer-to-peer transmission can be effectively solved, and the interconnection performance of the wireless base station is greatly improved. The flexibility of baseband processing may be further enhanced by SRIO switch device interconnection. Since SRIO implements the interconnection between most devices, even DSP can be supported for direct backplane transmission. Flexible point-to-point peer-to-peer interconnection and exchange interconnection, and meets the limitation of the device on the number of pins and the requirement on backboard transmission; most of the peripheral devices are manufactured in the chip with high integration, so that the number of the peripheral devices is reduced, and the failure rate is reduced.

The invention adopts the control circuit to externally connect the LRM connector through the discrete line, can independently and completely enable the versions of 4 DSPs to work through version control, and the power supply conversion circuit can independently and completely power up the 4 DSPs through power-up control; the control circuit can independently control the power-on independent work of the 4 DSPs, control the power-on of other chips, version management of the 4 DSPs and acquisition of temperature and voltage, the Ethernet circuit can exchange data with the 4 DSPs by using a network cable, and the network exchange circuit receives the data and distributes the data to the 4 DSPs. The method and the device realize the operations of the communication of an upper computer application program and external USB hardware equipment DSP, the conversion and storage of signals, the display of original waveforms and the like, and complete the hardware design and the construction and the software design process of the signal processing device. The LRM is independent from other modules in the function of the device and does not interfere with other modules on the installation structure, so when the device has a fault, the fault location and elimination can be directly carried out at the module level, and the module replacement can complete the fault repair work. Because LRM module and other module function mutual independence, when the inside trouble that breaks down of LRM module, start its intelligent inner structure self-checking device, carry out second grade maintenance to it, can reduce troubleshooting time greatly, reduce the replacement module cost. The integrated transmission of various signals such as radio frequency, difference, light, power supply and the like can be realized simultaneously, and the radio frequency signal transmitted by the radio frequency contact piece in the LRM modular electric connector reaches 40GHz and reaches the millimeter wave frequency band.

The invention continuously transmits the multichannel high-frequency digital signal synchronous processing data to the USB endpoint receiving buffer memory of the hardware equipment by using an interrupt mode, and then transmits the data to the upper computer, and the USB external equipment directly accesses the data buffer memory region and transmits the byte number and the address of the buffer memory region. The combination of high precision and multiple channels is realized, and more choices are brought to the analysis and processing of signals. The upper computer application program can complete tasks only through code conversion under the condition that the physical address of the external hardware device connecting port and signals needed by controlling the external hardware device are not known, the processing speed is higher than that of analog signals by more than 60%, and the radio frequency output power is 0.5-5W and can be adjusted through software. Therefore, the complexity of hardware equipment is avoided, and a programming interface with a unified standard is provided for a user.

Drawings

The patent is further described below with reference to the drawings and examples.

FIG. 1 is an exploded view of the multi-channel high frequency digital signal synchronous processing device of the present invention;

FIG. 2 is a schematic diagram of the circuit of FIG. 1;

FIG. 3 is a functional block diagram of the power conversion circuit of the present invention;

fig. 4 is a schematic block diagram of voltage and temperature detection of the DSP of fig. 1.

In the figure: the device comprises an upper cover plate 1, a multichannel signal processing daughter card 2, a box body 3, a multichannel signal processing carrier 4 and a lower cover plate 5.

The technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

Refer to fig. 1 and 2. In a preferred embodiment described below, a multichannel high-frequency digital signal synchronous processing apparatus includes: and a multichannel signal processing carrier board 4 which is packaged in a box body 3 of an upper cover board 5 and a lower cover board 5 and interacts data with the multichannel signal processing daughter card 2, and an LRM connector which is externally connected with a PC host through discrete lines, wherein: digital signal processors DSP1, DSP2, DSP3 and DSP4 which are communicated with an Ethernet circuit, a network switching circuit and a control circuit are arranged on the multichannel signal processing daughter card 2 and the multichannel signal processing carrier plate 4, wherein the DSP1 and the DSP2 form the multichannel signal processing daughter card 2, and the DSP3 and the DSP4 are communicated with the Ethernet circuit, the network switching circuit, the control circuit and the power supply conversion circuit to form the multichannel signal processing carrier plate 4; the Ethernet circuit is externally connected with functional equipment through the SGMII and LRM connector, and transmits communication data through the SGMII and 1-4 Digital Signal Processors (DSP) through a serial link; the network switching circuit carries out the communication between the boards based on the open interconnection technical standard RapidIO protocol architecture of the data packet exchange, the RapidIO protocol architecture establishes the basis with the packet format, the interconnection topological structure and the serial RapidIO physical layer specification-the interconnection architecture for the standard sRIO function of the baseband, and the transmission layer is externally connected with the LRM connector and the 1-4 digital signal processors DSP for transmitting serial differential analog signals by defining the logic layer of the operation protocol and defining the packet exchange, routing and addressing mechanism; the control circuit controls the power supply conversion circuit to be powered on and version controlled through a RapidIO physical layer defining electrical characteristics, link control and error correction retransmission, enables versions of 1-4 DSPs to work independently and/or all to be powered on to work independently and other chips, controls version management and temperature and voltage acquisition of the 4 DSPs, an Ethernet circuit uses a network cable and 1-4 DSPs to exchange data, the network exchange circuit receives the data, distributes the data to 1-4 DSPs for program loading and updating, the Ethernet circuit debugs 1-4 DSP signals, a processing circuit receives input differential signals, then transmits multi-channel high-frequency digital signal synchronous processing data to a USB endpoint receiving buffer of hardware equipment in an interrupt mode and then transmits the data to an upper computer, the USB external device directly accesses the data buffer area, and the byte number and the buffer area address of the transmission data are stored.

The Ethernet circuit debugs 1-4 DSP signals, inputs the difference signal into the processing circuit, then uses the interrupt mode to synchronously process the data of the multi-channel high-frequency digital signal, continuously transmits the data to the USB endpoint receiving buffer memory of the hardware device, and transmits the data to the upper computer, the USB external device directly accesses the data buffer memory, transmits the byte number and the buffer memory address of the data, and completes the processing of 16-32 channels of input signals.

As shown in fig. 3. The power conversion circuit includes: the power supply of the multichannel signal processing daughter card 212V and the power supply of the multichannel signal processing carrier plate 412V, the 12V power supply of the multichannel signal processing daughter card 2 respectively outputs 2 paths of 1.1V to the DSP1 and the DSP2 for use through the LTM4650, and respectively outputs 2 paths of 1.0V and 2 paths of 1.8V to the DSP1 and the DSP2 for use through the LTM 4644. The 12V power supply of the multi-channel signal processing daughter card 4 respectively outputs 2 paths of 1.1V to DSP3 and DSP4 through LTM4650 for use, 2 paths of 1.0V and 2 paths of 1.8V are respectively output through LTM4644 for use by DSP3 and DSP4, and 2 paths of 1.0V are respectively output through LTM4650 for use by DSP3 and DSP 4; the other LTM4650 outputs 2 paths of 1.0V to the exchange chip and the control chip respectively. The second LTM4644 outputs 3 paths of 1.2V, 2.5V and 3.3V to the Ethernet chip, and the third LTM4644 outputs 4 paths of 1.2V, 3.3V, 1.8V and 3.3V to the exchange chip and the control chip.

The DSP1 and the DSP2 form a multi-channel signal processing daughter card 2, and the DSP3 and the DSP4 are communicated with an Ethernet circuit, a network switching circuit, a control circuit and a power supply conversion circuit to form a multi-channel signal processing carrier board 4.

As shown in fig. 4. Preferably, the temperature of the DSP is detected through a sensor LC423, the I2C bus is used for detecting the temperature through a reporting signal control circuit, the voltage is detected through an ADC acquisition circuit of the control circuit, and the voltage is reported to the signal control circuit after the voltage is acquired.

The foregoing is only a preferred embodiment for implementing a multi-channel high frequency digital signal synchronous processing device, and it is to be understood that the invention is not limited to the form disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the concept as described herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A multi-channel high-frequency digital signal synchronous processing device, comprising: encapsulate in the box body 3 of upper and lower apron (5), with multichannel signal processing daughter card (2) mutual data multichannel signal processing support plate (4) and through the LRM connector of discrete line external connection PC host computer, its characterized in that: digital signal processors DSP1, DSP2, DSP3 and DSP4 which are communicated with an Ethernet circuit, a network switching circuit and a control circuit are arranged on the multichannel signal processing daughter card (2) and the multichannel signal processing carrier board (4), the Ethernet circuit is externally connected with functional equipment through an SGMII connector and an LRM connector, and communication data are transmitted through the SGMII connector and 1-4 digital signal processors DSP; the network switching circuit carries out the communication between the boards based on the open interconnection technical standard RapidIO protocol architecture of the data packet exchange, the RapidIO protocol architecture establishes the basis with the packet format, the interconnection topological structure and the serial RapidIO physical layer specification-the interconnection architecture for the standard sRIO function of the baseband, and the transmission layer is externally connected with the LRM connector and the 1-4 digital signal processors DSP for transmitting serial differential analog signals by defining the logic layer of the operation protocol and defining the packet exchange, routing and addressing mechanism; the control circuit controls the power supply conversion circuit to be powered on and version controlled through a RapidIO physical layer defining electrical characteristics, link control and error correction retransmission, enables versions of 1-4 DSPs to work independently and/or all to be powered on to work independently and other chips, controls version management and temperature and voltage acquisition of the 4 DSPs, an Ethernet circuit uses a network cable and 1-4 DSPs to exchange data, the network exchange circuit receives the data, distributes the data to 1-4 DSPs for program loading and updating, the Ethernet circuit debugs 1-4 DSP signals, a processing circuit receives input differential signals, then transmits multi-channel high-frequency digital signal synchronous processing data to a USB endpoint receiving buffer of hardware equipment in an interrupt mode and then transmits the data to an upper computer, the USB external device directly accesses the data buffer area, and the byte number and the buffer area address of the transmission data are stored.

2. The multi-channel high-frequency digital signal synchronous processing device according to claim 1, characterized in that: the Ethernet circuit debugs 1-4 DSP signals, inputs the difference signal into the processing circuit, then uses the interrupt mode to synchronously process the data of the multi-channel high-frequency digital signal, continuously transmits the data to the USB endpoint receiving buffer memory of the hardware device, and transmits the data to the upper computer, the USB external device directly accesses the data buffer memory, transmits the byte number and the buffer memory address of the data, and completes the processing of 16-32 channels of input signals.

3. The multi-channel high-frequency digital signal synchronous processing device according to claim 2, characterized in that: the power conversion circuit includes: the power supply of the multi-channel signal processing daughter card 212V and the power supply of the multi-channel signal processing carrier board 412V are respectively connected with the 12V power supply of the multi-channel signal processing daughter card (2) through the LTM4650, 2 paths of 1.1V are respectively output to the DSP1 and the DSP2 for use, and 2 paths of 1.0V and 2 paths of 1.8V are respectively output to the DSP1 and the DSP2 for use through the LTM 4644.

4. The multi-channel high-frequency digital signal synchronous processing device according to claim 3, characterized in that: the 12V power supply of the multi-channel signal processing carrier board (4) respectively outputs 2 paths of 1.1V to DSP3 and DSP4 through LTM4650 for use, 2 paths of 1.0V and 2 paths of 1.8V are respectively output through LTM4644 for use by DSP3 and DSP4, and 2 paths of 1.0V are respectively output through LTM4650 for use by DSP3 and DSP 4.

5. The multi-channel high-frequency digital signal synchronous processing device according to claim 4, characterized in that: the other LTM4650 outputs 2 paths of 1.0V to the exchange chip and the control chip respectively, the second LTM4644 outputs 3 paths of 1.2V, 2.5V and 3.3V to the Ethernet chip respectively, and the third LTM4644 outputs 4 paths of 1.2V, 3.3V, 1.8V and 3.3V to the exchange chip and the control chip respectively.

6. The multi-channel high-frequency digital signal synchronous processing device according to claim 1, characterized in that: the DSP temperature detection detects the temperature through a sensor LC423, an I2C bus is used for detecting the voltage through a reporting signal control circuit and an ADC acquisition circuit carried by the control circuit, and the voltage is reported to the signal control circuit after the voltage is acquired.

7. The multi-channel high-frequency digital signal synchronous processing device according to claim 1, characterized in that: the DSP1 and the DSP2 form a multi-channel signal processing daughter card (2), and the DSP3 and the DSP4 are communicated with an Ethernet circuit, a network switching circuit, a control circuit and a power supply conversion circuit to form a multi-channel signal processing carrier board (4).