CN113540293A

CN113540293A - Preparation method of solar cell

Info

Publication number: CN113540293A
Application number: CN202111074338.8A
Authority: CN
Inventors: 于琨; 刘长明; 张昕宇
Original assignee: Jinko Solar Haining Co Ltd
Current assignee: Jinko Solar Haining Co Ltd
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2021-10-22
Anticipated expiration: 2041-09-14
Also published as: CN113540293B

Abstract

The application provides a preparation method of a solar cell, which comprises the following steps: placing the silicon chip in a reaction furnace, and enabling the temperature of a furnace mouth to be a first temperature, the temperature of a furnace body to be a second temperature, wherein the first temperature is lower than the second temperature; adjusting the pressure in the furnace to a first preset pressure, and introducing a silicon source and an oxygen source into the reaction furnace along a furnace mouth; adjusting the air pressure in the furnace to a second preset air pressure, starting the plasma source, exciting the oxygen source into oxygen plasma, exciting the silicon source into silicon plasma, and depositing the oxygen plasma on the silicon wafer after reacting with the silicon plasma; and introducing inert gas into the reaction furnace. According to the preparation method of the solar cell, the uniformity of the tunneling oxide layer is improved, the overall cell efficiency can be improved, and the power generation efficiency is further improved.

Description

Preparation method of solar cell

Technical Field

The invention relates to the technical field of photovoltaics, in particular to a preparation method of a solar cell.

Background

The solar module refers to a power generation device which converts solar energy into direct current electric energy by utilizing the photovoltaic effect of a photovoltaic semiconductor material, and the core of the solar module is a solar cell.

The TOPCon (Tunnel Oxide Passivated Contact) solar cell in the existing back passivation Contact technology still has a space for improvement, and the efficiency can be further improved.

Disclosure of Invention

In view of the above, the present application provides a method for manufacturing a solar cell, which improves cell efficiency in mass production.

The application provides a preparation method of a solar cell, which comprises the following steps:

placing a silicon wafer in a reaction furnace, and enabling the temperature of a furnace mouth to be a first temperature and the temperature of a furnace body to be a second temperature, wherein the first temperature is lower than the second temperature;

adjusting the pressure in the furnace to a first preset pressure, and introducing a silicon source and an oxygen source into the reaction furnace along the furnace opening;

adjusting the air pressure in the furnace to a second preset air pressure, starting a plasma source, exciting the oxygen source to become an oxygen plasma, exciting the silicon source to become a silicon plasma, and depositing the oxygen plasma on the silicon wafer after reacting with the silicon plasma;

and introducing inert gas into the reaction furnace.

After adopting above-mentioned technical scheme, beneficial effect is: the uniformity of the tunneling oxide layer is improved, the conversion efficiency of the solar cell is further improved, and the concentration of the cell efficiency is improved.

In one possible design, the reaction furnace further comprises a furnace tail, and the temperature of the furnace tail is a third temperature;

the third temperature is greater than the second temperature; or, the third temperature is equal to the second temperature.

In one possible design, the reaction furnace further comprises a furnace tail, and the temperature in the reaction furnace is gradually increased along the direction from the furnace opening to the furnace tail.

In one possible design, the difference between the temperature of the furnace mouth and the temperature of the furnace tail is between 5 ℃ and 15 ℃, and the temperature in the reaction furnace rises uniformly along the direction from the furnace mouth to the furnace tail.

In one possible design, the second temperature is 170 ℃ to 230 ℃.

In one possible design, after the silicon wafer is placed in the reaction furnace, the temperature of the furnace mouth is enabled to be a first temperature, the temperature of the furnace body is enabled to be a second temperature, and the first temperature is lower than the second temperature, the rest steps are repeated, so that the silicon plasma and the oxygen plasma are deposited on the silicon wafer for multiple times.

In one possible design, the first predetermined air pressure is 10Pa to 100 Pa; and/or the presence of a gas in the gas,

the second predetermined air pressure is 30Pa-120 Pa.

In one possible design, the silicon source is at least one of trisdimethylaminosilane, tetraethoxysilane or ethyl orthosilicate; and/or the oxygen source is at least one of ozone and oxygen.

In one possible design, the wafer is subjected to an alkali polishing process prior to being placed in the reaction furnace.

In one possible design, the silicon wafer has a reflectivity of 50% to 55% after being subjected to an alkali polishing treatment.

Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application will be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a reaction furnace provided in an embodiment of the present application;

fig. 3 is a schematic diagram of a silicon wafer for testing the thickness of a tunneling oxide layer by a nine-point method according to an embodiment of the present application.

Reference numerals:

1-a reaction furnace;

11-furnace mouth;

12-furnace tail;

13-a first temperature zone;

14-a second temperature zone;

15-a third temperature zone;

2-graphite boat;

3-silicon chip.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Detailed Description

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be noted that the terms "upper", "lower", "left", "right", and the like used in the embodiments of the present application are described in terms of the angles shown in the drawings, and should not be construed as limiting the embodiments of the present application. In addition, in this context, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on "or" under "the other element or be indirectly on" or "under" the other element via an intermediate element.

For clarity and conciseness of the following description of the various embodiments, a brief introduction to related concepts or technologies is first presented:

atomic layer deposition: atomic layer deposition is a method (technique) for forming a deposited film by alternately pulsing a vapor phase precursor into a reactor and chemisorbing and reacting on a deposition substrate. When precursors reach the surface of the deposition substrate, they chemisorb and undergo surface reactions on the surface. An inert gas purge of the ald reactor is required between precursor pulses. Therefore, whether the deposition reaction precursor material can be chemically adsorbed on the surface of the material to be deposited is the key to realizing the atomic layer deposition. As can be seen from the surface adsorption characteristic of the gas-phase substance on the substrate material, any gas-phase substance can be physically adsorbed on the surface of the material, but the gas-phase substance must have certain activation energy to realize the chemical adsorption on the surface of the material, so whether the atomic layer deposition can be realized or not, and the selection of a proper reaction precursor substance is important.

Gas adsorption: gas adsorption can be classified into physical adsorption and chemical adsorption according to the difference in adsorption force. Physical adsorption is that gas molecules are attracted by van der waals force and attached to the surface of an adsorbent, is similar to the liquefaction process of gas, and is characterized by weaker adsorption, smaller adsorption heat, unstable adsorption and easier desorption, but generally has no selectivity to the adsorbed gas, the lower the temperature is, the larger the adsorption capacity is, multilayer adsorption can be formed, and the air suction effect of a molecular sieve adsorption pump and a low-temperature pump belongs to physical adsorption.

The chemical adsorption is realized by forming adsorption chemical bonds between atoms on the surface of a solid and gas molecules, is similar to the chemical reaction, and compared with physical adsorption, the chemical adsorption has the characteristics of strong adsorption, large adsorption heat, stability, difficult desorption, selective adsorption, increase of gas molecules subjected to chemical adsorption at higher temperature, only clinging to the surface to form single-layer adsorption (physical adsorption can also be formed on the chemically adsorbed molecules), and the air suction effect of a getter in a sputtering ion pump and an electron tube comprises the chemical adsorption.

Specific examples of the structure of the method for manufacturing a solar cell according to the embodiments of the present application will be described below.

The TOPCon battery in the solar battery realizes rear surface passivation by means of a tunneling effect, and the TOPCon battery adopts ultrathin silicon oxide and doped polycrystalline silicon to passivate the rear surface of crystalline silicon and realize selective carrier transportation, so that the efficiency of the crystalline silicon solar battery is improved.

The existing TOPCon battery back surface structure may be: the semiconductor substrate, the tunneling silicon oxide layer, the doped polycrystalline silicon layer and the rear surface passivation layer are sequentially arranged from inside to outside. When the tunneling oxide Layer is prepared on a batch of silicon wafers by using the conventional LPCVD (Low Pressure Chemical Vapor Deposition) or PE-ALD (Plasma Enhanced Atomic Layer Deposition), it is difficult to ensure that the average thickness values of the tunneling oxide layers on the silicon wafers are consistent and the thickness values of the tunneling oxide layers on the silicon wafers are consistent, and the difference in the thickness of the tunneling oxide Layer causes the doped polysilicon Layer and the rear surface passivation Layer to have lower uniformity, thereby affecting the conversion efficiency of the solar cell.

Specifically, in the preparation process of the solar cell, a tunneling oxide layer is required to be prepared on a silicon wafer, the thickness of the tunneling oxide layer is usually 0.8 nm-1.3 nm, and the uniformity of the tunneling oxide layer has a relatively obvious influence on the photoelectric conversion efficiency. Referring to fig. 2, in the conventional PE-ALD process, silicon wafers are often placed in batches in a graphite boat 2 located in a reaction furnace 1, and one end of the graphite boat 2 near a furnace tail 12 is connected to a power line, which extends out from the furnace tail 12 of the reaction furnace 1 and is connected to an external power source. Although the graphite boat 2 has good conductivity, the main body still has a certain resistance, and when the external power supply is turned on to energize the graphite boat 2, the voltage and current values of the end of the graphite boat 2 close to the furnace opening 11 (i.e. the end of the graphite boat 2 far away from the power line) are smaller than those of the end of the graphite boat 2 close to the furnace tail 12 (i.e. the end of the graphite boat 2 close to the power line) under the resistance action of the graphite boat 2. After the silicon source and the oxygen source are introduced into the furnace, the silicon source and the oxygen source are excited into silicon plasma and oxygen plasma under the ionization action of the electrified graphite boat 2, and because the voltage and the current value of one end, close to the furnace opening 11, of the graphite boat 2 are smaller than those of one end, close to the furnace tail 12, of the graphite boat 2, the silicon plasma and the oxygen plasma ionized from the silicon source and the oxygen source close to one end of the furnace opening 11 are less in quantity, and the silicon plasma and the oxygen plasma ionized from the silicon source and the oxygen source close to one end of the furnace tail 12 are more in quantity.

And the silicon plasma and the oxygen plasma excited by ionization can gather on the silicon wafer under the action of gas adsorption and react, and finally the silicon plasma and the oxygen plasma are deposited into a tunneling oxide layer. Because the silicon plasma and the oxygen plasma ionized from the silicon source and the oxygen source near one end of the furnace opening 11 are less in quantity, and the silicon plasma and the oxygen plasma ionized from the silicon source and the oxygen source near one end of the furnace tail 12 are more in quantity, the thickness of the tunneling oxide layer deposited on the silicon wafer has certain difference under the premise of the same other conditions, and the difference mainly shows that the tunneling oxide layer on the silicon wafer near one end of the furnace opening 11 is thinner, and the tunneling oxide layer on the silicon wafer near one end of the furnace tail 12 is thicker; and the thicknesses of the doped polysilicon layer and the rear surface passivation layer of all the subsequent silicon wafers on the surface of the tunneling oxide layer are consistent, so that the defects of different conversion efficiencies of the solar cells and low concentration of the cell efficiency are caused when the solar cells form a solar cell string to be manufactured into a solar module, and the module efficiency cannot reach the highest value.

In view of this, in order to improve the consistency of the thickness values of the tunneling oxide layers on the silicon wafers and reduce the difference between the silicon wafers, the present application provides a method for manufacturing a solar cell, where the method includes the following steps, please refer to fig. 1:

s01, placing the silicon wafer in a reaction furnace;

the silicon wafer (also referred to as a silicon substrate) may be subjected to the following pre-treatment to deposit the tunnel oxide layer more uniformly, for example: the used silicon wafer material is an n-type monocrystalline silicon wafer with the resistivity of 1 ohm to 3 ohm, the n-type monocrystalline silicon wafer is sequentially subjected to ultrasonic cleaning in acetone, isopropanol, ethanol and deionized water for 5min to remove organic pollutants on the surface, then a hydrobromic acid aqueous solution is used for removing natural oxides on the surface, then a silicon substrate is placed in a 75 ℃ ammonium sulfide aqueous solution (20%) for passivation for 20 min, the silicon substrate is placed in a 10% hydrofluoric acid (HF) solution after being cleaned by the deionized water, finally the deionized water is used for leaching, the silicon substrate is dried by high-purity nitrogen, and then the cleaned monocrystalline silicon wafer is placed in a reaction furnace;

or acid washing is adopted to remove BSG, and the acid washing material is specifically selected as follows: the concentration of HF acid is less than 4%; the concentration of HNO3 is 40% -50%, the concentration of H2SO4 is 15% -30%, and then 5% -15% by mass of alkaline solution is adopted to clean the rear surface of a semiconductor substrate (namely a silicon wafer) SO as to remove porous silicon; dripping micro-droplets of the alkali solution to the rear surface of the semiconductor substrate in a spraying mode to perform roughening treatment, and then pre-cleaning with hydrofluoric acid with the mass fraction of 5% -10%; and finally, polishing the rear surface of the semiconductor substrate by using polishing liquid, wherein the polishing temperature is 70-80 ℃, the polishing time is less than 260s, and the polishing liquid comprises 1-15% by mass of NaOH, 1-15% by mass of KOH and 0.5-2.5% by mass of additives.

S02, enabling the temperature of the furnace mouth to be a first temperature, the temperature of the furnace body to be a second temperature, and enabling the first temperature to be lower than the second temperature;

the temperature of each part of the reaction furnace can be independently adjusted, after the graphite boat with the silicon wafers is placed in the reaction furnace, the temperature of the furnace mouth is adjusted to be the first temperature, the temperature of the furnace body is the second temperature, and the first temperature is lower than the second temperature. The second temperature may be 170-230 ℃.

Specifically, it can be understood that both the silicon plasma and the oxygen plasma excited by ionization will gather on the silicon wafer and react under the action of gas adsorption, and finally deposit as a tunneling oxide film layer, because the temperature of the furnace mouth is different from that of the furnace body, the activity degree of the silicon plasma and the oxygen plasma in different areas of the reaction furnace is different, and it can be understood that the higher the temperature is, the higher the activity degree of the silicon plasma and the oxygen plasma is, the less the silicon plasma and the oxygen plasma adsorbed on the silicon wafer are. The temperature of the furnace mouth is adjusted to be lower than that of the furnace body, so that more silicon plasmas and oxygen plasmas are adsorbed on the silicon wafer close to one side of the furnace mouth, consistency of thickness values of tunneling oxide layers deposited in the silicon wafers is high, difference among the silicon wafers is reduced, and when the silicon wafers are connected in series to form a solar cell string to be manufactured into a component, conversion efficiency of the whole solar component is improved.

S03, adjusting the pressure in the furnace to a first preset pressure, and introducing a silicon source and an oxygen source into the reaction furnace along the furnace mouth;

the first predetermined air pressure value can be 10Pa-100Pa, and when the second predetermined air pressure is lower, the uniformity of the tunneling oxide layer deposited on the monolithic silicon wafer can be improved, so that the difference between the maximum thickness value of the tunneling oxide layer on the monolithic silicon wafer and the minimum thickness value of the tunneling oxide layer is smaller than 0.15 nm.

And introducing a silicon source and an oxygen source into the reaction furnace along the furnace mouth, wherein the silicon source can be at least one of tris (dimethylamino) silicon wan (TOMAS), tetraethoxysilane or ethyl orthosilicate, and the oxygen source can be at least one of ozone and oxygen.

The silicon source and the oxygen source can be stored in the source bottle and taken out from the source bottle by nitrogen with the flow rate of 220 mL/min. The temperature of the source bottle can be 60-100 ℃, preferably, the temperature of the source bottle can be 80 ℃, and under the condition that other process conditions are not changed, the single-cycle deposition rate of the silicon oxide film is increased along with the increase of the temperature of the source bottle. When the temperature of the source bottle is increased from 45 ℃ to 80 ℃, the single-cycle deposition rate of the film is increased from 0.08nm to 0.11 nm. The silicon source carried by the nitrogen is increased along with the increase of the temperature of the source bottle, and the silicon source attached to the surface of the silicon wafer is increased along with the increase of the temperature of the source bottle, so that the single-cycle deposition rate of the film is improved. Then the temperature of the source bottle is increased to 95 ℃, and the single-cycle deposition rate of the film has no obvious change. This is because the silicon source attached to the surface of the silicon wafer is saturated during the single cycle process, and the single cycle deposition rate of the thin film cannot be increased even if the flow rate of the silicon source is increased.

S04, adjusting the pressure in the furnace to a second preset pressure, starting the plasma source, exciting the oxygen source into oxygen plasma, exciting the silicon source into silicon plasma, and depositing the oxygen plasma on the silicon wafer after reacting with the silicon plasma;

the second predetermined pressure may be 30Pa to 120Pa to allow the deposition process to react more fully.

Plasma-enhanced atomic layer deposition (PE-ALD) is an extension of ALD technology, and a large number of active radicals are generated by introducing plasma, so that the reaction activity of a precursor substance is enhanced, the selection range and application requirements of ALD on the precursor source are expanded, the reaction period time is shortened, the requirement on the deposition temperature of a sample is reduced, and low-temperature and even normal-temperature deposition can be realized. The method is particularly suitable for the deposition of thin films on temperature-sensitive materials and flexible materials. In addition, the introduction of the plasma can further remove impurities in the thin film, and lower resistivity, higher compactness and the like can be obtained. In addition, the plasma can also clean the reaction chamber and perform surface activation treatment on the substrate, and the like, and the oxidation effect is better, so that the uniformity of the tunneling oxide layer is better.

The plasma source may excite the oxygen source into an oxygen plasma and the silicon source into a silicon plasma in the following manner.

Specifically, the plasma source may be composed of a graphite boat, a radio frequency power supply and a matcher, wherein after the oxygen source and the silicon source are fed into the quartz tube by the gas feeding system, the radio frequency power supply energizes the graphite boat so that the oxygen source becomes an oxygen plasma and the silicon source becomes a silicon plasma, and the oxygen plasma and the silicon plasma are adsorbed and deposited on the silicon wafer to finally form the tunneling oxide layer.

And S05, introducing inert gas into the reaction furnace.

The inert gas can be argon gas and the like, and the inert gas is introduced to blow away by-products generated in the reaction, unreacted oxygen source and silicon source from the reaction furnace.

In one embodiment, after the silicon wafer is placed in the reaction furnace, the above steps S03-S05 may be repeated, so that the film layer is deposited on the silicon wafer layer by layer, and finally the tunneling oxide layer with a predetermined thickness is obtained. Because a layer-by-layer deposition mode is adopted, the thickness of the tunneling oxide layer on the silicon chip can be adjusted by adjusting the number of times of repeating the steps S03-S05, and the number of times of repeating can be 20-30. The deposition mode is high in precision and good in stability, and the thickness of the tunneling oxide layer can be uniform, so that the photoelectric conversion efficiency of the solar cell is guaranteed.

In one embodiment, the reaction furnace further comprises a furnace tail, and the temperature of the furnace tail is a third temperature. The third temperature is greater than the second temperature or the third temperature is equal to the second temperature.

In this embodiment, the reaction furnace further includes a furnace tail, the reaction furnace is generally divided into a furnace opening partition, a furnace body partition and a furnace tail partition, the temperature of each partition can be independently adjusted, the reason is similar to the reason for setting the difference between the first temperature and the second temperature, and the difference between the third temperature and the second temperature is set to enable more silicon plasmas and oxygen plasmas to be adsorbed on the silicon wafer close to the furnace opening, so as to ensure that the consistency of the thickness values of the tunneling oxide layers deposited on the silicon wafers is high, thereby reducing the difference between the silicon wafers, and improving the overall conversion efficiency of the solar module after the silicon wafers are connected in series to form the solar cell string.

If the graphite boat is electrified, the difference between the quantities of oxygen plasma and silicon plasma ionized on the silicon wafers in the furnace body and the furnace tail subarea is not large, namely the quantities of the plasmas adsorbed on the silicon wafers at the furnace body and the furnace tail are not obviously different, the third temperature can be equal to the second temperature, and the thickness of the tunneling oxide layer deposited on the silicon wafers at all positions in the reaction furnace in the subsequent reaction can be ensured to be consistent.

In one embodiment, the reaction furnace further comprises a furnace tail, and the temperature in the reaction furnace is gradually increased along the direction from the furnace opening to the furnace tail.

The reaction furnace also comprises a furnace tail, the reaction furnace can be divided into a plurality of subareas along the direction from the furnace opening to the furnace tail, the temperature of each subarea can be independently controlled, and the temperature of each subarea is gradually increased along the direction from the furnace opening to the furnace tail in the reaction furnace by adjusting the temperature of each subarea. It can be understood that the above arrangement is also intended to adjust the temperature of each position of the reaction furnace so that more silicon plasma and oxygen plasma are adsorbed on the silicon wafer near the furnace opening and less silicon plasma and oxygen plasma are adsorbed on the silicon wafer near the furnace tail. And the consistency of the thickness values of the tunneling oxide layers deposited in the silicon wafers is high, so that the difference between the silicon wafers is reduced, and the overall conversion efficiency of the solar cell is improved when the silicon wafers are connected in series to form the solar cell.

In one embodiment, the difference between the temperature of the furnace mouth and the temperature of the furnace tail is 5-15 ℃, and the temperature in the reaction furnace is uniformly increased along the direction from the furnace mouth to the furnace tail.

Specific examples are given below:

referring to fig. 2, the reaction furnace includes five temperature zones arranged along the direction from the furnace opening 11 to the furnace tail 12, which are the furnace opening 11, the first temperature zone 13, the second temperature zone 14, the third temperature zone 15 and the furnace tail 12, the five temperature zones are arranged in sequence, the length of each temperature zone is 34-52cm, the temperature of the temperature zone close to the furnace tail 12 is the highest, the temperature of the five temperature zones along the direction from the furnace opening 11 to the furnace tail 12 is gradually increased, the temperature of the latter temperature zone is increased compared with the temperature of the former temperature zone, and specifically, the temperature increase rate may be 2-4 ℃/m.

The first embodiment is as follows:

adjusting the temperature of each temperature zone of the reaction furnace, wherein the furnace mouth: 167 ℃, first temperature zone: 168 ℃, second temperature zone: 169 ℃, third temperature zone: 170 ℃, furnace tail: 171 deg.C. After the preparation method of the solar cell is applied to the silicon wafer for 20 times of cyclic deposition, the average thickness values of the tunneling oxide layer on the silicon wafer in each temperature zone are respectively as follows: 1.06nm, 1.12nm, 1.08nm, 1.05nm, 1.10 nm.

It can be seen from the above data that the difference between the maximum value of the average tunnel oxide thickness in the five temperature zones and the minimum value of the average tunnel oxide thickness in the five temperature zones is 0.07 nm.

Example two:

furnace mouth: 147 ℃, first temperature zone: 149 ℃, second temperature zone: 150 ℃, third temperature zone: 151 ℃, furnace tail: 153 ℃. After the preparation method of the solar cell is applied to the silicon wafer for 20 times of cyclic deposition, the average thickness values of the tunneling oxide layer on the silicon wafer in each temperature zone are respectively as follows: 1.12nm, 1.18nm, 1.24nm, 1.20nm and 1.19 nm.

It can be seen from the above data that the difference between the maximum value of the average tunnel oxide thickness in the five temperature zones and the minimum value of the average tunnel oxide thickness in the five temperature zones is 0.12 nm.

Example three:

furnace mouth: 150 ℃, first temperature zone: 150 ℃, second temperature zone: 150 ℃, third temperature zone: 150 ℃, furnace tail: at 150 ℃. After the preparation method of the solar cell is applied to the silicon wafer for 20 times of cyclic deposition, the average thickness values of the tunneling oxide layer on the silicon wafer in each temperature zone are respectively as follows: 1.09nm, 1.10nm, 1.24nm, 1.20nm, 1.31 nm.

It can be seen from the above data that the difference between the maximum value of the average tunnel oxide thickness in the five temperature zones and the minimum value of the average tunnel oxide thickness in the five temperature zones is 0.22 nm.

Under the temperature distribution of the first embodiment and the second embodiment, the tunneling oxide layer thickness uniformity of each silicon wafer is better, and the difference is small.

Under the temperature distribution of the third embodiment, the tunneling oxide layer thickness uniformity of each silicon wafer is poor, and the difference is large.

In one embodiment, before the silicon wafer is placed in a reaction furnace, alkali polishing is carried out on the silicon wafer, the reflectivity of the silicon wafer after the alkali polishing is 50% -55%, and then the surface of the silicon wafer after the polishing is subjected to tunneling oxide layer preparation.

Specifically, the BSG may be removed by acid washing before polishing, and the acid washing material may be specifically selected as follows: the concentration of HF acid is less than 4%; the concentration of HNO3 is 40-50%, and the concentration of H2SO4 is 15-30%.

In the next step, 5-15% by mass of alkali solution is adopted to clean the rear surface of the semiconductor substrate (namely a silicon wafer) so as to remove porous silicon;

dripping micro-droplets of the alkali solution to the rear surface of the semiconductor substrate in a spraying mode to perform roughening treatment, and then pre-cleaning with hydrofluoric acid with the mass fraction of 5% -10%;

polishing the rear surface of the semiconductor substrate by using polishing liquid, wherein the polishing temperature is 70-80 ℃, the polishing time is less than 260s, and the polishing liquid comprises 1-15% by mass of NaOH, 1-15% by mass of KOH and 0.5-2.5% by mass of additives;

removing organic components in the etching solution by adopting a mixed solution of 5-15% by mass of potassium hydroxide and 15-40% by mass of hydrogen peroxide;

and (4) carrying out water washing and drying treatment on the polished semiconductor substrate.

The difference between the maximum thickness value of the tunneling oxide layer and the minimum thickness value of the tunneling oxide layer can be smaller than 0.15nm through the processing. Referring to fig. 3, the difference can be obtained by a nine-point method: dividing the silicon wafer 3 into 3 × 3 nine grids with approximately equal size, randomly taking a point in each grid to measure the thickness value of the tunneling oxide layer at the point, selecting the maximum value and the minimum value from the obtained nine thickness values of the tunneling oxide layer, and obtaining the following result after calculating the difference: a difference between a maximum thickness value of the tunnel oxide layer and a minimum thickness value of the tunnel oxide layer.

The same rate of the crystalline phase structure on the surface of the silicon wafer subjected to the alkali polishing treatment can reach eighty percent, and the uniformity of the tunneling oxide layer can be improved during the subsequent preparation of the tunneling oxide layer.

In some embodiments, the borosilicate glass layer on the front surface of the semiconductor substrate may need to be protected, such as by a mask, during the back surface polishing process.

In the specific embodiment, as the boron concentration of the rear surface of the semiconductor substrate is lower, the etching efficiency can be effectively improved by adopting the alkaline solution for etching. The alkali solution contains organic base and/or inorganic base, wherein the inorganic base can be NaOH, KOH, Ga (OH)2 and NH3.H2O, and the organic base can be triethylamine, nitrophenol, pyridine, quinine, colchicine, etc. The additive in the polishing solution can be a buffer solution composed of sodium sulfonate, maleic anhydride, alkyl glycoside and the like.

Specifically, the polishing temperature may be 70 ℃, 72 ℃, 74 ℃, 75 ℃, 78 ℃, 79 ℃, 80 ℃ or the like, and the polishing time may be 250s, 240s, 230s, 220s, 200s, 180s, 160s, 140s, 120s, 100s, 80s or the like, but may be other values within the above range.

In some embodiments, the semiconductor substrate has a polishing weight reduction of less than 0.3 g.

After the above treatment, the reflectivity of the rear surface of the silicon wafer is 50% -55%.

The basic structure of the N-type passivated contact battery is given as follows, and comprises the following components:

the silicon substrate comprises a silicon substrate, a first passivation layer positioned on the front surface of the silicon substrate, a tunneling silicon oxide layer positioned on the rear surface of the silicon substrate, a doped polycrystalline silicon layer positioned on the surface of the tunneling silicon oxide layer and a second passivation layer positioned on the surface of the doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer and the silicon substrate have doping elements with the same conductivity type.

The basic preparation process of the N-type passivated contact battery comprises the following steps:

and (3) double-sided texturing, reacting alkali liquor and an additive at 75-85 ℃, removing a cutting damage layer of the original silicon wafer, preparing a pyramid-shaped textured surface, and reducing the surface reflectivity to be below 12% after texturing.

Diffusing a boron emitter, and performing boron source diffusion on an N-type silicon wafer, wherein the common method is low-pressure diffusion of tubular equipment, and the temperature is generally 980-1022 ℃; borosilicate glass, BSG for short, is generally present on the surface of the silicon wafer.

Preparing an ultrathin tunneling oxide layer, removing BSG on the back surface (non-diffusion surface) of the silicon wafer, namely removing redundant BSG on the back surface, and flattening the back surface. The reflectivity after back polishing is generally more than 35%; the tunneling oxide layer can be prepared by various methods, for example, the preparation of the ultrathin silicon oxide is carried out by adopting a PE-ALD (plasma-assisted atomic layer deposition) mode, the thickness of the prepared ultrathin silicon oxide is generally less than 2nm, and the preparation temperature is generally lower than 700 ℃.

The polysilicon doping can be performed by LPCVD or PECVD, and is classified into intrinsic doping and in-situ doping. Annealing is required after doping, the annealing temperature is generally 900-1000 ℃, and crystallization of the doped polysilicon is promoted to form crystals with higher quality.

And (3) double-sided passivation, wherein the front and back of the silicon wafer is passivated by silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride.

And (3) preparing an electrode, namely preparing a battery electrode on the front side and the back side by adopting a silk screen mode, and forming a conductive electrode by high-temperature sintering. In addition, N-type cells typically require photo-annealing to increase the level of hydrogen passivation in the body.

Testing and sorting: and subdivision is performed according to the color, efficiency and other parameters, so that the consistency of the components is ensured.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for manufacturing a solar cell, comprising:

and introducing inert gas into the reaction furnace.

2. The method of claim 1, wherein the reaction furnace further comprises a furnace tail, and the temperature of the furnace tail is a third temperature;

the third temperature is greater than the second temperature; or the like, or, alternatively,

the third temperature is equal to the second temperature.

3. The method of claim 1, wherein the reaction furnace further comprises a furnace tail, and the temperature in the reaction furnace gradually increases along a direction from the furnace opening to the furnace tail.

4. The method of claim 3, wherein the difference between the temperature of the furnace mouth and the temperature of the furnace tail is between 5 ℃ and 15 ℃, and the temperature in the reaction furnace is uniformly increased along the direction from the furnace mouth to the furnace tail.

5. The method of claim 1, wherein the second temperature is 170 ℃ to 230 ℃.

6. The method according to claim 1, wherein after the silicon wafer is placed in a reaction furnace so that the temperature of the furnace opening is a first temperature and the temperature of the furnace body is a second temperature, and the first temperature is lower than the second temperature, the remaining steps are repeated so that the silicon plasma and the oxygen plasma are deposited on the silicon wafer a plurality of times.

7. The method according to claim 1, wherein the first predetermined gas pressure is 10Pa to 100 Pa; and/or the presence of a gas in the gas,

the second predetermined air pressure is 30Pa-120 Pa.

8. The method of claim 1, wherein the silicon source is at least one of trisdimethylaminosilane, tetraethoxysilane or ethyl orthosilicate; and/or the presence of a gas in the gas,

the oxygen source is at least one of ozone and oxygen.

9. The method of claim 1, wherein the silicon wafer is subjected to an alkali polishing treatment before being placed in the reaction furnace.

10. The method for manufacturing a solar cell according to claim 9, wherein the silicon wafer has a reflectance of 50% to 55% after alkali polishing.