CN113540273B - 一种高速高增益的雪崩光电探测器及制备方法 - Google Patents
一种高速高增益的雪崩光电探测器及制备方法 Download PDFInfo
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Abstract
本公开提供了一种高速高增益的雪崩光电探测器及其制备方法,其芯片包括由上至下设置的三级台阶;其中:第一级台阶,包括由上至下依次设置的P电极、第一欧姆接触层、第一吸收层和第二吸收层上部;第二级台阶,包括由上至下依次设置的第二吸收层下部、过渡层、第一电荷层、倍增层、第二电荷层、渡越层和第二欧姆接触层上部;第三级台阶,包括由上至下依次设置的第二欧姆接触层下部和绝缘衬底;所述三级台阶的水平投影面积依次增大。所述芯片倍增层采用超薄InAlAs材料。所述三级台阶芯片倒扣键合在基片上。
Description
技术领域
本公开涉及探测器技术领域,具体涉及一种高速高增益的雪崩光电探测器。
背景技术
随着人们对信息传递日益增长的需要,对光通讯的传输速度和传输距离有了更高的要求。半导体光电探测器作为光通讯中重要的接收器件,起着举足轻重的作用。与PIN型探测器相比,雪崩光电探测器因其内部对光电流的增益,提高了对光信号探测的响应度。因此,高速高增益的APD被越来越多地应用于光通讯中。评价APD性能的主要指标有3dB带宽、暗电流、响应度和增益带宽积等。
常用的高速APD采用分离吸收电荷倍增的SAGCM结构。要想提高APD响应速度,需减小耗尽区长度来减小载流子渡越时间。单位增益下响应度与带宽相互制约,要想提高APD单位增益下的响应度,通常应增加本征吸收层的厚度,但本征吸收区完全耗尽后,使载流子渡越时间延长,限制APD带宽。光生载流子在倍增区的碰撞电离时间随着增益的提高而增加,在高增益下碰撞电离时间逐渐成为限制器件3dB带宽的主要因素。
此外,高增益下限制APD带宽的主要因素是倍增区的雪崩增益时间,倍增区越薄,APD的增益带宽积越大。但薄倍增区需要更高的电场强度引发雪崩倍增,会使器件的隧穿电流增大,严重时发生隧道击穿。因此,要想获得高速、高增益的雪崩光电探测器,应解决增益带宽积与暗电流、带宽与响应度之间的矛盾。
发明内容
针对现有技术存在的上述缺陷,提供了一种高速高增益的雪崩光电探测器,克服现有技术存在的缺点和不足,提高APD的带宽和响应度。
一种高速高增益的雪崩光电探测器,其芯片包括由上至下设置的三级台阶;其中:
第一级台阶,包括由上至下依次设置的P电极、第一欧姆接触层、第一吸收层和第二吸收层上部;
第二级台阶,包括由上至下依次设置的第二吸收层下部、过渡层、第一电荷层、倍增层、第二电荷层、渡越层和第二欧姆接触层上部;
第三级台阶,包括由上至下依次设置的第二欧姆接触层下部和绝缘衬底;
所述第二欧姆接触层下部连接有N电极;
所述第三级台阶的水平投影面积大于第二级台阶的水平投影面积;所述第二级台阶的水平投影面积大于第一级台阶的水平投影面积。
可选地,所述倍增层的组成材料为本征InAlAs。
可选地,所述第二吸收层的组成材料为本征InGaAs,过渡层的组成材料为本征InAlGaAs,第一电荷层的组成材料为P型掺杂的InAlAs,第二电荷层的组成材料为N型掺杂的InAlAs,渡越层的组成材料为本征InAlAs。
可选地,所述第一吸收层的组成材料为P型掺杂的InGaAs。
可选地,所述第一欧姆接触层的组成材料为P型InGaAs;所述第二欧姆接触层的组成材料为N型InGaAlAs;所述绝缘衬底的组成材料为本征InP。
可选地,其特征在于,所述P电极的组成材料为金属Ti和Au,所述N电极的组成材料为金属Au、Ge、Ni和Au。
可选地,所述绝缘衬底下方设置有增透膜,增透膜所用材质为SiNx。
可选地,所述芯片下方设置有基片,所述芯片倒扣键合于基片上。
可选地,所述基片的组成材料为Al2O3陶瓷。
可选地,一种高速高增益的雪崩光电探测器的制备方法,包括以下几个步骤:
S1采用外延生长工艺,在绝缘衬底上生长第二欧姆接触层、渡越层、第二电荷层、倍增层、第一电荷层、过渡层、第二吸收层、第一吸收层和第一欧姆接触层;
S2采用光刻工艺,在外延正面光刻出P电极图形,带胶溅射P电极,采用剥离工艺制备P电极;
S3采用光刻工艺,在外延正面光刻第一台阶图形;采用湿法腐蚀工艺,对第一台阶以外的外延材料进行腐蚀,腐蚀至第二吸收层中心时停止,形成第一台阶;
S4采用光刻工艺,在外延正面光刻出第二台阶图形,此图形半径稍大于第一台阶;采用湿法腐蚀工艺,腐蚀至第二欧姆接触层2停止,形成第二台阶;
S5采用光刻工艺,在外延正面光刻出第三台阶图形,采用湿法腐蚀工艺,腐蚀进绝缘衬底停止,形成第三台阶;
S6采用复合钝化层钝化的工艺,在外延正面生长复合钝化层作保护,以减小器件的表面漏电流;
S7采用光刻工艺,在外延正面光刻N电极窗口和P电极窗口的图形;采用湿法腐蚀工艺,腐蚀掉N电极窗口和P电极窗口处的复合钝化层,形成N电极和P电极窗口;
S8采用光刻工艺,重新光刻出N电极窗口,带胶溅射,溅射材料为Au、Ge、Ni和Au,之后剥离出N电极;
S9采用光刻工艺,在外延正面光刻出电极引线窗口,带胶溅射,溅射材料为Ti和Au,之后剥离出电极引线;
S10采用快速退火合金工艺,使半导体器件和金属间形成良好的欧姆接触;
S11对绝缘衬底背面进行减薄抛光,采用等离子体化学气相沉积工艺,在减薄抛光后的表面生长SiNx,作增透膜;
S12采用光刻工艺,在增透膜上光刻出对准标记窗口,对准标记为圆环结构,尺寸大于探测器正面第二台阶,且中心位置与第二台阶中心对齐,在后续使用过程中起到定位入射光位置的作用,采用等离子体刻蚀工艺,刻蚀掉对准标记处的SiNx;
S13采用溅射工艺,在陶瓷基片正面溅射金属Ti和Au;
S14采用光刻工艺,在金属Ti和Au表面光刻出微带线窗口;采用湿法腐蚀工艺,将微带线以外的Ti和Au腐净;
S15采用光刻工艺,在陶瓷衬底正面光刻出键合点窗口;采用溅射工艺,带胶溅射金属In,剥离形成金属In键合点;
S16采用热熔焊接工艺,将陶瓷衬底上金属In键合点分别与探测器芯片正面键合点对准焊接,完成芯片的倒扣键合。
从上述技术方案可以看出,本发明中所公开的一种高速高增益的雪崩光电探测器,APD芯片采用三级台阶结构,减小了倍增区边缘电场的强度,从而在减小由杂质和缺陷引起的暗电流的同时,有效地抑制了边缘击穿,使得碰撞电离过程集中于倍增层中心,提高了APD的可靠性。
本发明中所公开的一种高速高增益的雪崩光电探测器,其采用分离吸收、过渡、P型电荷、倍增、N型电荷、渡越的SAGCMCT结构,较常规SAGCM结构,新引入的N型电荷层和渡越层处于耗尽状态,可以减小APD的结电容,提高APD带宽,同时,由于倍增电子的漂移速度比倍增空穴的漂移速度快,可以保证倍增电子的漂移时间小于倍增空穴的漂移时间,使APD总的渡越时间不变,器件带宽不受渡越时间影响。
本发明中所公开的一种高速高增益的雪崩光电探测器,其倍增层选用小于0.12μm的超薄本征InAlAs作为组成材料,InAlAs与吸收层的InGaAs材料晶格匹配,减小了由晶格失配带来的暗电流和载流子堆积,且由于InAlAs比InP有更低的离化率,同等厚度下可以获得更高的增益带宽积和更低的过剩噪声,解决了增益带宽积与暗电流间的矛盾。
本发明中所公开的一种高速高增益的雪崩光电探测器,其采用背入射结构制备的APD,从探测器芯片背面入射的光被吸收区第一次吸收后,经P电极反射,被吸收区二次吸收,从而提高APD的响应度;由于高速APD采用台面结构,背入射结构可以避免台面上开入射窗口,有利于有源区面积的减小,从而提高APD带宽;P电极可完全覆盖P欧姆接触层,减小了欧姆接触电阻,从而提高APD带宽。
附图说明
图1示意性示出了根据本公开实施例的雪崩光电探测器的剖面示意图;
图2示意性示出了根据本公开实施例的雪崩光电探测器的俯视图;
图3示意性示出了根据本公开实施例的雪崩光电探测器制备完N电极引线后和相应的键合辅助支撑台连接的结构示意图;
图4示意性示出了根据本公开实施例的微带线和金属In键合点的结构示意图;
图5示意性示出了根据本公开实施例的雪崩光电探测器的制备流程图;
图中,绝缘衬底-1、第二欧姆接触层-2、渡越层-3、第二电荷层-4、倍增层-5、第一电荷层-6、过渡层-7、第二吸收层-8、第一吸收层-9、第一欧姆接触层-10、P电极-11、N电极-12、增透膜-13、第一台阶-14、第二台阶-15、第三台阶-16、N电极窗口-17、N电极引线-18、N电极台-19、键合辅助支撑台-20、第三金属In键合点-21、第一金属In键合点-22、第二金属In键合点-23、微带线-24。
具体实施方式
以下,将参照附图来描述本公开的实施例。但是应该理解,这些描述只是示例性的,而并非要限制本公开的范围。在下面的详细描述中,为便于解释,阐述了许多具体的细节以提供对本公开实施例的全面理解。然而,明显地,一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本公开的概念。
在此使用的术语仅仅是为了描述具体实施例,而并非意在限制本公开。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在,但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
本公开的实施例提供一种高速高增益的雪崩光电探测器。
图1~图2示意性给出了根据本公开实施例的雪崩光电探测器的结构图,其芯片包括由上至下设置的三级台阶;其中:
第一级台阶14,包括由上至下依次设置的P电极11、第一欧姆接触层10、第一吸收层9和第二吸收层8上部;
第二级台阶,包括由上至下依次设置的第二吸收层8下部、过渡层7、第一电荷层6、倍增层5、第二电荷层4、渡越层3至第二欧姆接触层2上部;
第三级台阶,包括由上至下依次设置的第二欧姆接触层2下部和绝缘衬底1;
所述第二欧姆接触层2下部连接有N电极12;
所述第三级台阶的水平投影面积大于第二级台阶的水平投影面积;所述第二级台阶的水平投影面积大于第一级台阶的水平投影面积。
如图1所示,APD芯片采用三级台阶结构。第一台阶起到限制器件有源区的作用。且由于第一台阶14尺寸小于第二台阶15,倍增区电场被集中于其中心区域,减小了其边缘电场的强度,从而在减小由杂质和缺陷引起的暗电流的同时,有效地抑制了边缘击穿,使得碰撞电离过程集中于倍增层5中心区域,提高了APD的可靠性。第三台阶起到电学隔离的作用。
如图1所示,采用分离吸收、过渡、P型电荷、倍增、N型电荷、渡越的SAGCMCT结构,较常规SAGCM结构,新引入的N型电荷层和渡越层处于耗尽状态,可以减小APD的结电容,提高APD带宽,同时,由于倍增电子的漂移速度比倍增空穴的漂移速度快,可以保证倍增电子的漂移时间小于倍增空穴的漂移时间,使APD总的渡越时间不变,器件带宽不受渡越时间影响。制备的SAGCMCT结构的APD,单位增益下的3dB带宽约24GHz,5倍增益下的3dB带宽约20GHz。
所述倍增层5的组成材料为超薄的本征InAlAs材料。
由于InAlAs比InP有更低的离化率,同等厚度下可以获得更高的增益带宽积和更低的过剩噪声,解决了增益带宽积与暗电流间的矛盾。
所述第二吸收层8的组成材料为本征InGaAs,过渡层7的组成材料为本征InAlGaAs,第一电荷层6的组成材料为P型掺杂的InAlAs,第二电荷层4的组成材料为N型掺杂的InAlAs,渡越层3的组成材料为本征InAlAs。
通过设计第一电荷层6和第二电荷层4的掺杂浓度,可以实现对倍增层5的电场强度和厚度的控制,使碰撞电离过程集中发生在倍增层5内,在减小隧穿电流的同时,提高增益带宽积,解决了增益带宽积与隧穿电流之间的矛盾。本实施例中所述第一电荷层6的掺杂浓度为5.7×1017cm-3;第二电荷层4的掺杂浓度为5.0×1017cm-3。
此外由于倍增层5的材料InAlAs与第二吸收层8的InGaAs材料晶格匹配,可以减小由晶格失配带来的暗电流和载流子堆积。
如图1所示,所述第二吸收层8与第一欧姆接触层10之间设置有第一吸收层9,所述第一吸收层9的组成材料为梯度掺杂的P型InGaAs。
如图1所示,吸收区采用部分掺杂结构,可以在总吸收层厚度不变,即对应的量子效率不变的情况下,减小了光生电子进入倍增区的渡越时间,以及碰撞电离产生的倍增空穴的渡越时间,从而提高APD的带宽。
如图1所示,所述P电极11的组成材料为Ti和Au。
如图1所示,所述P电极11所用材料为Ti和Au,以第一欧姆接触层10向外分别设置厚度合适的Ti和Au;由于Ti和Au均为金属,具有较高的反射率,因此P电极11同时具有反射镜的效果。本实施例中Ti的厚度为30nm,Au的厚度为200nm。
如图1所示,采用背入射结构制备的APD,从探测器芯片背面入射的光被吸收区第一次吸收后,经P电极11反射,被吸收区二次吸收,从而提高APD的响应度;由于高速APD采用台面结构,背入射结构可以避免在台面上开入射窗口,有利于有源区面积的减小,从而提高APD带宽;P电极11可完全覆盖P欧姆接触层,减小了欧姆接触电阻,从而提高APD带宽。本实施例中通过上述技术方案制备的背入射三级台阶结构的SAGCMCT-APD,单位增益下的响应度约0.55A/W;5倍增益下的3dB带宽约20GHz,最大增益带宽积达到210GHz,可以应用于高速、高灵敏度的光信号探测。
如图1所示,所述绝缘衬底1下方设置有增透膜13,增透膜13所用材质为SiNx;所述增透膜13上设置有光入射标记,所述标记为圆环结构,其圆心与芯片正面的有源区圆心对准,直径略大于有源区。本实施例中所述增透膜13的折射率为1.85,厚度为210nm。
本实施例中所述第一电荷层6和第二电荷层4的厚度均为70nm;所述过渡层7的厚度为30nm;所述渡越层3、第一吸收层9和第二吸收层8的厚度均为0.3μm;所述倍增层5的厚度为0.12μm,在0.9倍击穿电压下暗电流仅为6.7nA的同时,增益带宽积可达210GHz。
所述第一欧姆接触层10的组成材料为P型InAlAs;所述第二欧姆接触层2的组成材料为N型InA1As;所述绝缘衬底1的组成材料为本征InP。
所述芯片下方设置有基片,所述芯片倒扣键合于基片上,通过光被二次吸收提高器件的响应度。
所述基片的组成材料为Al2O3陶瓷。
所述基片包括图3所示的部分结构和图4所示的结构。
图3示意性给出了根据本公开实施例的雪崩光电探测器制备N电极引线后和键合辅助支撑台连接的结构图。
图4示意性给出了以及微带线和金属In键合点的结构图。
如图2、图3和图4所示,所述雪崩光电探测器芯片第二欧姆接触层2的台阶平台上开设有N电极窗口17,N电极窗口17内设置有N电极引线18,所述N电极12通过N电极引线18连接至N电极台19,所述绝缘衬底1上连接有键合辅助支撑台20;所述键合辅助支撑台20上方连接倒扣键合基片;所述倒扣键合基片的组成材料为Al2O3陶瓷;倒扣键合基片上设置有微带线24;所述微带线24的组成材料为Ti和Au。
如图2、图3和图4所示,所述微带线24包括第一微带线24和第二微带线24;所述第一微带线24一端连接P电极11,另一端连接倒扣键合基片,所述第二微带线24一端连接N电极台19,另一端连接倒扣键合基片。
进一步地,如图2、图3和图4所示,所述第一微带线24与P电极11之间设置有4μm厚的铟,对铟进行热熔焊接工艺,使其连接第一微带线24和P电极11,从而将探测器芯片倒扣键合到基片上,此焊接点为第一金属In键合点22。
如图2、图3和图4所示,所述第二微带线24与N电极台19之间设置有4μm厚的铟,对铟进行热熔焊接工艺,使其连接第二微带线24和N电极台19,从而将探测器芯片倒扣键合到基片上,此焊接点为第二金属In键合点23。
如图2、图3和图4所示,所述键合辅助支撑台20与基片之间设置有4μm厚的铟,对铟进行热熔焊接工艺,使其连接基片和键合辅助支撑台20,从而将探测器芯片倒扣键合到底座上,此焊接点为第三金属In键合点21。
如图2、图3和图4所示,所述P电极11、N电极台19和键合辅助支撑台20共同作用,提高键合成功率和稳定性,背入射APD芯片与陶瓷绝缘基片1相连接,提供了一种有效的芯片散热方式,且有利于后续的封装处理。
本发明实施例还提供一种高速高增益的雪崩光电探测器的制备方法,如图5所示,方法包括以下几个步骤:
S1采用外延生长工艺,在绝缘衬底1上生长第二欧姆接触层2、渡越层3、第二电荷层4、倍增层5、第一电荷层6、过渡层7、第二吸收层8、第一吸收层9和第一欧姆接触层10;
S2采用光刻工艺,在外延正面光刻出P电极11图形,带胶溅射P电极11,采用剥离工艺制备P电极11;
S3采用光刻工艺,在外延正面光刻第一台阶14图形;采用湿法腐蚀工艺,对第一台阶14以外的外延材料进行腐蚀,直至第二吸收层8中心时停止,形成第一台阶14;
S4采用光刻工艺,在外延正面光刻出第二台阶15图形,此图形半径稍大于第一台阶14;采用湿法腐蚀工艺,腐蚀至第二欧姆接触层22停止,形成第二台阶15;
S5采用光刻工艺,在外延正面光刻出第三台阶16图形,采用湿法腐蚀工艺,腐蚀进绝缘衬底1停止,形成第三台阶16;
S6采用复合钝化层钝化的工艺,在外延正面生长共一定厚度的复合钝化层作保护,以减小器件的表面漏电流;
S7采用光刻工艺,在外延正面光刻N电极窗口17和P电极11窗口的图形;采用湿法腐蚀工艺,腐蚀掉N电极窗口17和P电极11窗口处的复合钝化层,形成N电极12和P电极11窗口;
S8采用光刻工艺,重新光刻出N电极窗口17,带胶溅射,溅射材料为Au、Ge、Ni和Au,之后剥离出N电极12;
S9采用光刻工艺,在外延正面光刻出电极引线窗口,带胶溅射,溅射材料为Ti和Au,之后剥离出电极引线;
S10采用快速退火合金工艺,使半导体器件和金属间形成良好的欧姆接触;
S11对绝缘衬底11背面进行减薄抛光,采用等离子体化学气相沉积工艺,在减薄抛光后的表面生长SiNx,作增透膜13;
S12采用光刻工艺,在增透膜13上光刻出对准标记窗口,对准标记为圆环结构,尺寸大于探测器正面第二台阶15,且中心位置与第二台阶15中心对齐,在后续使用过程中起到定位入射光位置的作用,采用等离子体刻蚀工艺,刻蚀掉对准标记处的SiNx;
S13采用溅射工艺,在陶瓷基片正面溅射金属Ti和Au;
S14采用光刻工艺,在金属Ti和Au表面光刻出微带线窗口24;采用湿法腐蚀工艺,将微带线以外的Ti和Au腐净;
S15采用光刻工艺,在陶瓷衬底正面分别光刻出第一金属In键合点22、第二金属In键合点23和第三金属In键合点21的窗口;采用溅射工艺,带胶溅射金属In,剥离形成金属In键合点;
S16采用热熔焊接工艺,将陶瓷衬底上的第一金属In键合点22、第二金属In键合点23和第三金属In键合点21的分别与探测器芯片正面的P电极11、N电极台19和键合辅助支撑台20对准焊接,完成芯片的倒扣键合。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种高速高增益的雪崩光电探测器,其特征在于,其芯片包括由上至下设置的三级台阶;其中:
第一级台阶,包括由上至下依次设置的P电极、第一欧姆接触层、第一吸收层和第二吸收层上部,其中,所述第一吸收层的组成材料为P型掺杂的InGaAs;
第二级台阶,包括由上至下依次设置的第二吸收层下部、过渡层、第一电荷层、倍增层、第二电荷层、渡越层和第二欧姆接触层上部,其中,所述第二吸收层的组成材料为本征InGaAs,所述过渡层的组成材料为本征InAlGaAs,所述第二欧姆接触层的组成材料为N型InGaAlAs;
第三级台阶,包括由上至下依次设置的第二欧姆接触层下部和绝缘衬底;
所述第二欧姆接触层下部连接有N电极;
所述第三级台阶的水平投影面积大于第二级台阶的水平投影面积;所述第二级台阶的水平投影面积大于第一级台阶的水平投影面积。
2.根据权利要求1所述的雪崩光电探测器,其特征在于,所述倍增层的组成材料为本征InAlAs。
3.根据权利要求1所述的雪崩光电探测器,其特征在于,第一电荷层的组成材料为P型掺杂的InAlAs,第二电荷层的组成材料为N型掺杂的InAlAs,渡越层的组成材料为本征InAlAs。
4.根据权利要求1所述的雪崩光电探测器,其特征在于,所述第一欧姆接触层的组成材料为P型InGaAs;所述绝缘衬底的组成材料为本征InP。
5.根据权利要求1所述的雪崩光电探测器,其特征在于,所述P电极的组成材料为金属Ti和Au,所述N电极的组成材料为金属Au、Ge、Ni和Au。
6.根据权利要求1所述的雪崩光电探测器,其特征在于,所述绝缘衬底下方设置有增透膜,增透膜所用材质为SiNx。
7.根据权利要求1所述的雪崩光电探测器,其特征在于,所述芯片下方设置有基片,所述芯片倒扣键合于基片上。
8.根据权利要求7所述的雪崩光电探测器,其特征在于,所述基片的组成材料为Al2O3陶瓷。
9.一种高速高增益的雪崩光电探测器的制备方法,其特征在于,包括以下几个步骤:
S1采用外延生长工艺,在绝缘衬底上生长第二欧姆接触层、渡越层、第二电荷层、倍增层、第一电荷层、过渡层、第二吸收层、第一吸收层和第一欧姆接触层,其中,所述第一吸收层的组成材料为P型掺杂的InGaAs,第二吸收层的组成材料为本征InGaAs,所述过渡层的组成材料为本征InAlGaAs,第二欧姆接触层的组成材料为N型InGaAlAs;
S2采用光刻工艺,在外延正面光刻出P电极图形,带胶溅射P电极,采用剥离工艺制备P电极;
S3采用光刻工艺,在外延正面光刻第一台阶图形;采用湿法腐蚀工艺,对第一台阶以外的外延材料进行腐蚀,腐蚀至第二吸收层中心时停止,形成第一台阶;
S4采用光刻工艺,在外延正面光刻出第二台阶图形,此图形半径稍大于第一台阶;采用湿法腐蚀工艺,腐蚀至第二欧姆接触层2停止,形成第二台阶;
S5采用光刻工艺,在外延正面光刻出第三台阶图形,采用湿法腐蚀工艺,腐蚀进绝缘衬底停止,形成第三台阶;
S6采用复合钝化层钝化的工艺,在外延正面生长复合钝化层作保护,以减小器件的表面漏电流;
S7采用光刻工艺,在外延正面光刻N电极窗口和P电极窗口的图形;采用湿法腐蚀工艺,腐蚀掉N电极窗口和P电极窗口处的复合钝化层,形成N电极和P电极窗口;
S8采用光刻工艺,重新光刻出N电极窗口,带胶溅射,溅射材料为Au、Ge、Ni和Au,之后剥离出N电极;
S9采用光刻工艺,在外延正面光刻出电极引线窗口,带胶溅射,溅射材料为Ti和Au,之后剥离出电极引线;
S10采用快速退火合金工艺,使半导体器件和金属间形成良好的欧姆接触;
S11对绝缘衬底背面进行减薄抛光,采用等离子体化学气相沉积工艺,在减薄抛光后的表面生长SiNx,作增透膜;
S12采用光刻工艺,在增透膜上光刻出对准标记窗口,对准标记为圆环结构,尺寸大于探测器正面第二台阶,且中心位置与第二台阶中心对齐,在后续使用过程中起到定位入射光位置的作用,采用等离子体刻蚀工艺,刻蚀掉对准标记处的SiNx;
S13采用溅射工艺,在陶瓷基片正面溅射金属Ti和Au;
S14采用光刻工艺,在金属Ti和Au表面光刻出微带线窗口;采用湿法腐蚀工艺,将微带线以外的Ti和Au腐净;
S15采用光刻工艺,在陶瓷衬底正面光刻出键合点窗口;采用溅射工艺,带胶溅射金属In,剥离形成金属In键合点;
S16采用热熔焊接工艺,将陶瓷衬底上金属In键合点分别与探测器芯片正面键合点对准焊接,完成芯片的倒扣键合。
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