CN113540093A

CN113540093A - Semiconductor structure and forming method thereof

Info

Publication number: CN113540093A
Application number: CN202110795362.4A
Authority: CN
Inventors: 刘藩东; 华文宇; 骆中伟
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2021-10-22
Anticipated expiration: 2041-07-14
Also published as: CN113540093B

Abstract

A semiconductor structure and a method of forming the same, comprising: the array substrate comprises a first substrate and a second substrate, wherein the first substrate comprises a plurality of active regions which are arrayed along a first direction and a second direction, the first direction and the second direction form an acute included angle, and the projection of each active region on the surface of the first substrate is rhombic, circular or elliptical; a first isolation layer between adjacent active regions; the word line gate structures are positioned in the first substrate and the first isolation layer and are mutually independent; a plurality of bit line structures, each bit line structure being located on 1 column of active regions arranged in the second direction; and the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate. The semiconductor structure can improve the performance of the dynamic random access memory and reduce the process difficulty of forming the dynamic random access memory.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor Memory, and the main action principle is to represent whether a binary bit (bit) is 1 or 0 by using the amount of charges stored in a capacitor.

A basic memory cell of a Dynamic Random Access Memory (DRAM) is composed of a transistor and a storage capacitor, and a memory array is composed of a plurality of memory cells. Therefore, the size of the memory chip area depends on the area size of the basic memory cell.

The existing dynamic random access memory is still to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of a dynamic random access memory and reduce the process difficulty of forming the dynamic random access memory.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the array substrate comprises a first substrate and a second substrate, wherein the first substrate comprises a plurality of active regions which are arrayed along a first direction and a second direction, the first direction and the second direction form an acute included angle, the projection of each active region on the surface of the first substrate is a rhombus, a circle or an ellipse, and the diagonal line of the rhombus is parallel to or perpendicular to the first direction; a first isolation layer between adjacent active regions; the word line grid structures are arranged along a first direction and extend along a third direction, each word line grid structure penetrates through 2 adjacent rows of active regions in the first direction along the third direction, and the third direction is perpendicular to the first direction; a plurality of bit line structures, each bit line structure being located on 1 column of active regions arranged in the second direction; and the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate.

Optionally, the method further includes: and the second isolation structures are positioned in the first substrate, are positioned between adjacent word line gate structures, penetrate through 1 row of active regions along the third direction, and are lower than the first isolation layer in the direction vertical to the surface of the first substrate.

Optionally, the first substrate includes a first side and a second side opposite to each other, the bit line structure is located on the first side, the capacitor structure is located on the second side, and the second side exposes a bottom surface of the second isolation structure.

Optionally, the first doped region is located on the first surface of each active region, and each bit line structure is electrically connected to the first doped regions of 1 column of active regions arranged in the second direction.

Optionally, a top surface of the second isolation structure in a direction toward the first surface is higher than half of a height of the word line gate structure.

Optionally, each 2 capacitor structures are located on the second surface of the 1 active region, and in the first direction, the 2 capacitor structures are respectively located on two sides of the second isolation structure penetrating through the 1 active region.

Optionally, the second doped region is located on the second surface of each active region, in the first direction, the second doped region is located on two sides of the second isolation structure, in a direction perpendicular to the second surface, the depth of the second doped region is smaller than the height of the second isolation structure, and each capacitor structure is electrically connected to the second doped region on one of the two sides of the second isolation structure.

Optionally, a projection of the capacitor structure on the second surface at least partially coincides with the second doped region.

Optionally, the first substrate includes a first side and a second side opposite to each other, the capacitor structure is located on the first side, the bit line structure is located on the first side, and the first side exposes a top surface of the second isolation structure.

Optionally, the first doped region is located on the second surface of each active region, and each bit line structure is electrically connected to the first doped regions of 1 column of active regions arranged in the second direction.

Optionally, a bottom surface of the second isolation structure in a direction toward the second surface is lower than one half of a height of the word line gate structure.

Optionally, each 2 capacitor structures are located on the first surface of the 1 active region, and in the first direction, the 2 capacitor structures are located on two sides of the second isolation structure penetrating through the 1 active region.

Optionally, the second doped region is located on the first surface of each active region, in the first direction, the second doped region is located on two sides of the second isolation structure, in a direction perpendicular to the first surface, the depth of the second doped region is smaller than the height of the second isolation structure, and each capacitor structure is electrically connected to the second doped region on one of the two sides of the second isolation structure.

Optionally, a projection of the capacitor structure on the first surface is at least partially overlapped with the second doped region.

Optionally, the method further includes: a first conductive structure located on each first doped region.

Optionally, the method further includes: a second conductive structure located between each capacitive structure and the second doped region.

Optionally, the acute included angle between the first direction and the second direction ranges from 25 degrees to 65 degrees.

Optionally, in the third direction, adjacent active regions have a first spacing between centers of projections of the first substrate surface, the first spacing is less than 2 times T1, and the T1 is a maximum spacing between centers and edges of projections of the active regions on the first substrate surface in the third direction.

Optionally, in the first direction, adjacent active regions have a second spacing between centers of projections of the first substrate surface, the second spacing is less than 2 times T2, and the T2 is a maximum spacing between centers and edges of the projections of the active regions on the first substrate surface in the first direction.

Optionally, a top surface of the word line gate structure is lower than a top surface of the first isolation layer, and the semiconductor structure further includes: and the covering dielectric layer is positioned on the top surface of the word line gate structure and is also positioned in the first isolation layer.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate comprises a plurality of active regions arrayed along a first direction and a second direction, the first direction and the second direction form an acute included angle, the projection of each active region on the surface of the first substrate is a rhombus, a circle or an ellipse, and the diagonal of the rhombus is parallel to or perpendicular to the first direction; forming a first isolation layer between adjacent active regions; forming a plurality of mutually independent word line grid structures in the first substrate and the first isolation layer, wherein the word line grid structures are arranged along a first direction and extend along a third direction, each word line grid structure penetrates through 2 adjacent rows of active regions in the first direction along the third direction, and the third direction is perpendicular to the first direction; after the word line gate structure is formed, 1 bit line structure is formed on each row of active regions arranged along the second direction; after the word line grid structure is formed, a plurality of capacitor structures are formed on a plurality of active regions, and the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate.

Optionally, a plurality of methods for forming the word line grid structure include: forming a plurality of first grooves in the plurality of active regions and the first isolation layer, wherein the plurality of first grooves are distributed along a first direction and extend along a third direction, the depth of each first groove is smaller than the height of the first isolation layer, and the inner wall surface of each first groove exposes the first isolation layer and 2 rows of active regions adjacent to each other in the first direction; and forming a plurality of word line gate structures in the plurality of first grooves.

Optionally, the top surface of the word line gate structure is lower than the top surface of the first isolation layer, and the method for forming the semiconductor structure further includes: after forming a plurality of word line gate structures, forming a covering dielectric layer in the first groove, wherein the covering dielectric layer is positioned on the top surfaces of the word line gate structures.

Optionally, the first substrate includes a first side and a second side opposite to each other, the bit line structure is located on the first side, and the capacitor structure is located on the second side.

Optionally, the method further includes: after forming the word line gate structure and before forming the bit line structure, a first doped region is formed at a first side of each active region.

Optionally, the method further includes: providing a second substrate; bonding the first substrate and the second substrate after forming the bit line structure, wherein the first surface faces to the surface of the second substrate.

Optionally, the method further includes: after the first substrate and the second substrate are bonded, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; and after the first substrate is planarized from the second surface of the first substrate, forming a plurality of second isolation structures in the first substrate, wherein the second isolation structures are exposed from the second surface, the height of each second isolation structure is smaller than that of the first isolation layer in the direction perpendicular to the second surface, the second isolation structures are positioned between the adjacent word line gate structures, and each second isolation structure penetrates through 1 row of active regions along the third direction.

Optionally, the method further includes: after the second isolation structure is formed and before a plurality of capacitor structures are formed, a second doped region is formed on the second surface of each active region, the second doped regions are located on two sides of the second isolation structure in the first direction, and the depth of the second doped region is smaller than the height of the second isolation structure in the direction perpendicular to the second surface.

Optionally, the first substrate includes a first side and a second side opposite to each other, the capacitor structure is located on the first side, and the bit line structure is located on the second side.

Optionally, the method further includes: after the word line grid structures are formed and before the capacitor structures are formed, a plurality of second isolation structures are formed in the first substrate, the second isolation structures are exposed out of the first surface, the height of each second isolation structure is smaller than that of the corresponding first isolation layer in the direction perpendicular to the first surface, the second isolation structures are located between the adjacent word line grid structures, and each second isolation structure penetrates through 1 row of active regions in the third direction.

Optionally, the method further includes: after the second isolation structure is formed and before the capacitor structure is formed, a second doped region is formed on the first surface of each active region, the second doped regions are located on two sides of the second isolation structure in the first direction, and the depth of the second doped region is smaller than the height of the second isolation structure in the direction perpendicular to the first surface.

Optionally, the method further includes: providing a second substrate; and bonding the first substrate and the second substrate after the capacitor structure is formed, wherein the first surface faces to the surface of the second substrate.

Optionally, the method further includes: after the first substrate and the second substrate are bonded, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; after planarizing the first substrate from the second side of the first substrate, and prior to forming the bit line structures, a first doped region is formed at the second side of each active region.

Optionally, the method further includes: first conductive structures are formed on each of the first doped regions prior to forming the bitline structures.

Optionally, the method further includes: and before forming the capacitor structure, forming a second conductive structure on the second doped region on each side of the second isolation structure along the first direction.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the semiconductor structure provided by the technical scheme of the invention, on one hand, the bit line structure and the capacitor structure are respectively positioned on two opposite surfaces of the first substrate, and meanwhile, the word line gate structure is positioned in the first substrate, so that the wiring of the semiconductor structure is simpler, and the distance between the bit line structure and the capacitor structure is larger, so that the parasitic capacitance generated by the wiring, the parasitic capacitance generated between the bit line structure and the capacitor structure and the like are reduced, and the difficulty in manufacturing the capacitor of the memory is reduced. On the other hand, the space in the direction perpendicular to the surface of the first substrate can be efficiently utilized through the shape of the projection of the active region on the surface of the first substrate, the arrangement mode of the active regions and the position and arrangement mode of the word line gate structure, so that the area occupied in the direction along the surface of the first substrate is greatly saved, the density of the memory array unit is effectively improved, the storage capacity is improved, and the performance of the semiconductor structure is improved. In addition, each bit line structure is positioned on 1 row of active regions arranged in the second direction, and the first direction and the second direction form an acute included angle, so that the distance between adjacent bit line structures can be increased, the parasitic capacitance of the bit line structures is reduced, the performance of the semiconductor structure is improved, and the manufacturing difficulty of the capacitor of the memory is reduced.

In the method for forming the semiconductor structure provided by the technical scheme of the invention, on one hand, the space in the direction vertical to the surface of the first substrate can be efficiently utilized through the projection shape of the active region on the surface of the first substrate, the arrangement mode of the active regions and the position and arrangement mode of the word line gate structure, so that the area required to be occupied in the direction along the surface of the first substrate is greatly saved, the density of the memory array unit is effectively improved, the memory capacity is improved, and the performance of the semiconductor structure is improved. On the other hand, the projection shape of the active regions on the surface of the first substrate and the arrangement mode of the active regions can enable the active regions to be distributed in the first substrate in a uniform grid mode, so that the stop positions of the planarization process performed on the surface of the first substrate in each area of the first substrate can be close to or the same in the process of forming the bit line structure or the capacitor structure on one of two opposite surfaces of the first substrate, and therefore the uniformity of the characteristics of each area of the semiconductor structure is good, and the performance of the semiconductor structure is improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment;

fig. 2 to 21 are schematic structural diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the invention;

fig. 22 to 31 are schematic structural views of steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, the existing dynamic random access memory has yet to be improved. The analysis will now be described with reference to specific examples.

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment.

Please refer to fig. 1, which includes: a substrate 100; a word line gate structure 101 located within the substrate 100; a source doped region 103 and a drain doped region 102 in the substrate 100 at two sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 through the source plug 104; and a capacitor structure 107 electrically connected to the drain doped region 102 through the capacitor plug 106.

The forming process of the semiconductor structure comprises the following steps: the source doping region 103 and the drain doping region 102 are formed, the word line gate structure 101 is formed in the substrate 100, the source plug 104 and the bit line structure 105 are formed, the capacitor plug 106 is formed, and the capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are on the horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor and are located above the substrate in the fabrication process.

On one hand, the capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105, so that the overall process complexity is high, and extremely high requirements are imposed on the photolithography process and the alignment. On the other hand, the channel direction of the transistor extends along the direction of the surface of the substrate 100, and therefore, the source doped region 103, the drain doped region 102 and the channel in the transistor occupy a large amount of the surface area of the substrate 100, resulting in low integration and low storage capacity of the dynamic random access memory.

In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, in which a bit line structure and a capacitor structure are respectively located on two opposite surfaces of a first substrate, and a word line gate structure is located in a first isolation layer and the first substrate, thereby simplifying wiring and reducing parasitic capacitance. Meanwhile, the space in the direction perpendicular to the surface of the first substrate can be efficiently utilized through the shape of the active regions on the surface of the first substrate, the arrangement mode of the active regions, the position and arrangement mode of the word line gate structures and the position and arrangement mode of the bit line structures, so that the area occupied in the direction along the surface of the first substrate is greatly saved, the density of the memory array units is effectively improved, the memory capacity is improved, and the performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 21 are schematic structural diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 2 and 3, fig. 2 is a schematic top view along a direction M in fig. 3, and fig. 3 is a schematic cross-sectional view along a direction a1-a2 in fig. 2, providing a first substrate 200.

The material of the first substrate 200 is a semiconductor material.

Specifically, the material of the first substrate 200 includes silicon.

In other embodiments, the material of the first substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

The first substrate 200 includes: the active regions 201 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y form an acute included angle α.

In the present embodiment, a projection 2011 of each active region 201 on the surface of the first substrate 200 is a diamond shape, and a diagonal line of the diamond shape is parallel or perpendicular to the first direction X.

In some other embodiments, the projection of each active region on the first substrate surface is circular or elliptical.

In this embodiment, the acute included angle α between the first direction X and the second direction Y is in a range of 25 degrees to 65 degrees.

The first substrate 200 has opposite surfaces.

Specifically, the first substrate 200 includes a first side 203 and a second side 204 opposite to each other.

It is to be understood that only a partial region of the first substrate 200 is schematically illustrated in fig. 2 and 3. Therefore, in fig. 2 and 3, the active region 201 located at the edge of the part of the region is shown only as a part of the entire active region 201.

Referring to fig. 4 and 5, fig. 4 is a schematic top view along the direction M in fig. 5, and fig. 5 is a schematic cross-sectional view along the direction a1-a2 in fig. 4, wherein a first isolation layer 210 is formed between adjacent active regions 201.

The material of the first isolation layer 210 includes silicon oxide or a low K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In this embodiment, the method of forming the first isolation layer 210 includes: forming a first isolation groove mask layer (not shown) on the first surface 203, wherein the first isolation groove mask layer exposes the first surface 203 between the adjacent active regions 201; etching the first substrate 200 by using the first isolation groove mask layer as a mask to form a first isolation groove (not shown) between the active regions 201; forming a first isolation material layer (not shown) on the first surface 203 in the first isolation groove; the first layer of isolation material is planarized until the first side 203 is exposed.

In this embodiment, the etching process for forming the first isolation groove includes at least one of a dry etching process and a wet etching process.

In this embodiment, the process of forming the first isolation material layer includes: at least one of a chemical vapor deposition process (CVD), a flowable chemical vapor deposition process (FCVD), a physical vapor deposition Process (PVD), and a spin-on process.

In this embodiment, the process of planarizing the first isolation material layer includes a Chemical Mechanical Polishing (CMP) process.

Next, a plurality of mutually independent word line grid structures are formed in the first substrate 200 and the first isolation layer 210, the word line grid structures are arranged along the first direction X and extend along the third direction Z, each word line grid structure penetrates through 2 adjacent rows of active regions in the first direction X along the third direction Z, and the third direction Z is perpendicular to the first direction X. Please refer to fig. 6 to fig. 10 for specific steps of forming a plurality of word line gate structures.

Referring to fig. 6 to 8, fig. 6 is a schematic top view structure along the direction M in fig. 7, fig. 7 is a schematic cross-sectional structure along the direction B1-B2 in fig. 6, fig. 8 is a schematic perspective view of the active regions and a portion of the first grooves in fig. 6, and a plurality of first grooves 211 are formed in the active regions 201 and the first isolation layer 210.

The first grooves 211 are arranged along the first direction X and extend along the third direction Z.

The first recesses 211 provide space for subsequently forming word line gate structures.

The depth D1 of the first grooves 211 is smaller than the height H1 of the first isolation layer 210 in the direction perpendicular to the first face 203, and the inner wall surface of each first groove 211 exposes the first isolation layer 210 and 2 rows of active regions 201 adjacent in the first direction X.

It should be understood that fig. 8 only schematically shows 1 active region 201 in fig. 6, and a portion of the first recess 211 in the active region 201.

In this embodiment, the method for forming the plurality of first grooves 211 includes: forming a first groove mask layer (not shown) on the first surface 203 and the first isolation layer 210, wherein the first groove mask layer exposes a part of the first surface 203 and a part of the top surface of the first isolation layer 210; and etching the first substrate 200 and the first isolation layer 210 by using the first groove mask layer as a mask.

Referring to fig. 9 and 10, fig. 9 is a schematic top view along the direction M in fig. 10, and fig. 10 is a schematic cross-sectional view along the direction B1-B2 in fig. 9, wherein a plurality of word line gate structures 220 are formed in the first grooves 211.

The plurality of word line gate structures 220 are independent of one another.

The word line grid structure 220 is located in the first substrate 200 and the first isolation layer 210, the word line grid structures 220 are arranged along the first direction X and extend along the third direction Z, and each word line grid structure 220 penetrates through 2 adjacent rows of active regions 201 on the first direction X along the third direction Z.

For ease of understanding, fig. 9 schematically shows: projections 2011 of 2 rows of active regions 201 that are adjacent in the first direction X.

In this embodiment, the top surface of the word line gate structure 220 is lower than the top surface of the first isolation layer 210.

In this embodiment, the word line gate structure 220 includes: a gate electrode (not shown) located in the first recess 211; a gate dielectric layer (not shown) between the gate and the first substrate 200.

In the present embodiment, the material of the gate dielectric layer includes silicon oxide or a low K (K less than 3.9) material.

In other embodiments, the material of the gate dielectric layer comprises a high-K material (K greater than 3.9) comprising aluminum oxide or hafnium oxide.

In this embodiment, the gate is a single layer. The material of the gate is, for example, polysilicon or a metal material.

In other embodiments, the gate is a composite gate, the gate includes a first gate and a second gate on a top surface of the first gate, and the first gate and the second gate are made of different materials. The material of the first gate electrode comprises a metal material, and the second gate electrode structure comprises polysilicon. Because the grid comprises the first grid and the second grid which are made of different materials, the threshold voltage of the word line grid structure can be adjusted by adjusting the volume ratio of the first grid and the second grid so as to meet different device design requirements. Wherein the metal material comprises tungsten.

In this embodiment, the method for forming the word line gate structure 220 includes: forming a gate dielectric film (not shown) on the surface of the first substrate 200 exposed by the first recess 211 and the first surface 203; after forming a gate dielectric film, forming a gate material layer (not shown) in the first recess 211, on the first surface 203, and on the surface of the first isolation layer 210, wherein the gate material layer fills the first recess 211; and etching the gate material layer and the gate dielectric film until the top surfaces of the gate material layer and the gate dielectric film are lower than the top surface of the first isolation layer 210.

In the present embodiment, T3 is greater than WB (shown in fig. 13), the T3 is the maximum distance between the edges of the projection 2011 in the vertical direction along the second direction Y, and the WB bit line structures 250 have a line width in the vertical direction along the second direction Y. Therefore, short circuit risks between adjacent bit line structures are reduced, and reliability of the semiconductor structure is improved.

In the present embodiment, the centers of the adjacent projections 2011 have a first distance W1 in the third direction Z, the first distance W1 is smaller than 2 times T1, and the T1 is the maximum distance between the center of the projection 2011 and the edge of the projection 2011 in the third direction Z.

Since the first distance W1 is less than 2 times T1, that is, the active regions 201 are alternately arranged in the third direction Z, the utilization efficiency of the surface of the first substrate 200 is further improved, and thus, the integration of the semiconductor structure can be better improved.

In the present embodiment, the centers of the adjacent projections 2011 have a second spacing W2 therebetween in the first direction X, and the second spacing W2 is greater than the width WZ of the word line gate structure 220 in the first direction X.

Specifically, the centers of adjacent projections 2011 are not located within the projection of any wordline gate structure 220 on the first side 203. Thereby, it is ensured that there is no contact between the word line gate structures 220 adjacent in the first direction X.

In this embodiment, the second distance W2 is also smaller than 2 times T2, and the T2 is the maximum distance between the center of the projection 2011 and the edge of the projection 2011 in the first direction X.

Since the second pitch W2 is also smaller than 2 times T2, that is, the active regions 201 are alternately arranged in the first direction X, the utilization efficiency of the surface of the first substrate 200 is further improved, and thus the integration of the semiconductor structure can be better improved.

With continued reference to fig. 9 and 10, after forming a plurality of word line gate structures 220, a capping dielectric layer 230 is formed in the first recess 211, wherein the capping dielectric layer 230 is located on the top surface of the word line gate structures 220.

The capping dielectric layer 230 serves to protect the word line gate structure 220 in a subsequent process and reduce damage to the word line gate structure 220 in the subsequent process, and serves to insulate the word line gate structure 220 from a subsequently formed bit line structure, so as to meet a circuit design requirement of the memory.

In addition, since the cover dielectric layer 230 is located in the first groove 211, the inner space of the first substrate 200 is effectively utilized, thereby further improving the integration level of the semiconductor structure, reducing the influence of the position of the cover dielectric layer 230 on the positions of other semiconductor structures, and facilitating the simplification of the circuit layout of the semiconductor structure.

The process for forming the capping dielectric layer 230 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In the present embodiment, the material of the capping dielectric layer 230 includes a dielectric material, which includes silicon oxide or a low K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

Referring to fig. 11 and 12, fig. 11 is a schematic top view along the direction M in fig. 12, and fig. 12 is a schematic cross-sectional view along the direction B1-B2 in fig. 11, wherein after forming the capping dielectric layer 230, a first doped region U1 is formed on the first surface 203 of each active region 201.

In this embodiment, the method for forming the first doped region U1 includes: after the cover dielectric layer 230 is formed, an ion implantation process is performed on the first surface 203 to implant dopant ions into the first substrate 200, so as to form the first doped region U1.

Wherein the doping ions comprise N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

Referring to fig. 13 and 14, fig. 13 is a schematic top view along the direction M in fig. 14, fig. 14 is a schematic cross-sectional view along the direction B1-B2 in fig. 13, and after forming the first doped region U1, 1 bit line structure 250 is formed on each row of active regions 201 arranged along the second direction Y.

Because 1 bit line structure 250 is formed on each row of active regions 201 arranged along the second direction Y, and an acute included angle α is formed between the second direction Y and the first direction X, the distance between adjacent bit line structures 250 is increased, thereby reducing the parasitic capacitance of the bit line structures 250 and improving the performance of the semiconductor structure.

In the present embodiment, the bit line structure 250 is located on the first surface 203. And, each bit line structure 250 is electrically connected to the first doping regions U1 of the 1 column of active regions 201 arranged in the second direction Y.

The material of the bitline structure 250 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In the present embodiment, the first conductive structure 240 is formed on each of the first doped regions U1 before the bit line structure 250 is formed.

The first conductive structure 240 is used to electrically connect the bit line structure 250 and the first doped region U1.

The process window size for forming the bit line structure 250 can be increased by the first conductive structure 240. Specifically, the first conductive structure 240 has high structural flexibility, and therefore, by adjusting the structure of the first conductive structure 240, for example, by shifting the projection of the first conductive structure 240 on the first surface 203 with respect to the projection of the first doped region U1 on the first surface 203, or by making the projection range of the first conductive structure 240 on the first surface 203 exceed the range of the first doped region U1, the position limitation of the bit line structure 250 and the size limitation of the line width WB can be reduced, and the size of the process window for forming the bit line structure 250 is increased.

In addition, the bit line structure 250 is raised by the first conductive structure 240, and thus, a distance between the bit line structure 250 and the word line gate structure 220 is increased, thereby improving insulation reliability between the bit line structure 250 and the word line gate structure 220, and reducing parasitic capacitance between the word line gate structure 220 and the bit line structure 250.

In other embodiments, the first conductive structure is not formed, and the bit line structure is in direct contact with the first doped region. Thus, the process steps are reduced and the manufacturing efficiency is improved.

In the present embodiment, the first conductive structure 240 is a conductive plug. The material of the first conductive structure 240 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum, or silicon.

In the present embodiment, the method of forming the first conductive structure 240 includes: forming a lower first dielectric layer (not shown) on the surfaces of the first isolation layer 210, the capping dielectric layer 230 and the first doped region U1; forming a first mask layer (not shown) on the surface of the lower first dielectric layer, wherein part of the surface of the lower first dielectric layer is exposed by the first mask layer; etching the lower first dielectric layer by using the first mask layer as a mask until the surface of the first doping region U1 is exposed, and forming a plurality of first conductive openings (not shown) in the lower first dielectric layer; forming a first conductive structure material layer (not shown) in the first conductive opening and on the surface of the lower first dielectric layer, wherein the surface of the first conductive structure material layer is higher than the surface of the lower first dielectric layer; and flattening the first conductive structure material layer until the surface of the lower first medium layer is exposed.

In this embodiment, the etching process for forming the first conductive opening includes at least one of a dry etching process and a wet etching process. The process of forming the first conductive structure material layer includes a metal plating process, a chemical vapor deposition process, and the like. The process for planarizing the first conductive structure material layer includes a chemical mechanical polishing process.

In the present embodiment, the method for forming the bit line structure 250 includes: forming a middle layer first dielectric layer on the first conductive structure 240 and the surface of the lower layer first dielectric layer; forming a second mask layer (not shown) on the surface of the middle layer first dielectric layer, wherein the second mask layer exposes a part of the surface of the middle layer first dielectric layer; etching the middle layer first dielectric layer by using the second mask layer as a mask until the top surface of the first conductive structure 240 is exposed, and forming a plurality of bit line openings (not shown) in the middle layer first dielectric layer; forming a bit line material layer (not shown) in the bit line opening and on the surface of the middle layer first dielectric layer, wherein the surface of the bit line material layer is higher than the surface of the middle layer first dielectric layer; and flattening the bit line material layer until the surface of the middle layer first medium layer is exposed.

In this embodiment, the etching process for forming the bit line opening includes at least one of a dry etching process and a wet etching process. The process of forming the bit line material layer includes a metal plating process, a chemical vapor deposition process, and the like. The process for planarizing the bit line material layer includes a chemical mechanical polishing process.

In this embodiment, after the bit line structure 250 is formed, an upper first dielectric layer is formed on the surface of the middle first dielectric layer and the surface of the bit line structure 250.

In this embodiment, the process for forming the lower first dielectric layer, the middle first dielectric layer and the upper first dielectric layer includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

The lower layer first dielectric layer, the middle layer first dielectric layer and the upper layer first dielectric layer form a first dielectric layer 260, and the first dielectric layer 260 surrounds the first conductive structures 240 and the bit line structures 250.

Note that the first dielectric layer 260 is not shown in fig. 13 for ease of understanding the location of the bit line structure 250.

In this embodiment, the material of the first dielectric layer 260 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

Referring to fig. 15 and 16, fig. 15 is a schematic top view along the direction N in fig. 16, and fig. 16 is a schematic cross-sectional view along the direction C1-C2 in fig. 15, providing a second substrate 300.

In this embodiment, the second substrate 300 has a logic circuit (not shown) therein. The logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

In other embodiments, the second substrate does not have logic circuitry therein.

With continued reference to fig. 15 and 16, after the first dielectric layer 260 is formed, the first substrate 200 and the second substrate 300 are bonded, with the first side 203 facing the surface of the second substrate 300.

The logic circuit is electrically connected to the word line gate structure 220 and the bit line structure 250, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220 and the bit line structure 250, respectively, to control writing and reading of the memory.

With continued reference to fig. 15 and 16, after bonding the first substrate 200 and the second substrate 300, the first substrate 200 is planarized from the second side 204 until the bottom surface of the first isolation layer 210 is exposed.

In the present embodiment, the process of planarizing the first substrate 200 from the second side 204 includes a chemical mechanical polishing process.

Referring to fig. 17 and 18, fig. 17 is a schematic top view along a direction N in fig. 18, fig. 18 is a schematic cross-sectional view along a direction C1-C2 in fig. 17, after the first substrate 200 is planarized from the second side 204, a plurality of second isolation structures 270 are formed in the first substrate 200, and the second side 204 exposes bottom surfaces of the second isolation structures 270.

In a direction perpendicular to the second face 204, a height H2 of the second isolation structure 270 is less than a height H1 of the first isolation layer 210 (as shown in fig. 8).

The second isolation structures 270 are located between adjacent word line gate structures 220, and each second isolation structure 270 penetrates through 1 row of the active regions 201 along the third direction Z.

The second isolation structure 270 is used to separate adjacent second doping regions formed subsequently, so as to insulate the adjacent second doping regions.

In the present embodiment, the top surface of the second isolation structure 270 in the direction towards the first surface 203 is higher than half of the height of the word line gate structure 220. Accordingly, leakage current between adjacent word line gate structures 220 is further reduced, and reliability of the semiconductor structure is improved.

In the present embodiment, the material of the second isolation structure 270 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In this embodiment, the method for forming the second isolation structure 270 includes: forming a third mask layer (not shown) on the second surface 204, wherein the third mask layer exposes partial surfaces of the active regions 201 and partial bottom surfaces of the first isolation layers 210; etching the first substrate 200 by using the third mask layer as a mask, and forming a plurality of second isolation openings (not shown) in the first substrate 200; forming a second isolation material layer (not shown) in the second isolation opening, on the bottom surface of the first isolation layer 210 and on the second side 204 of the active region 201, the second isolation material layer having a surface higher than the bottom surface of the first isolation layer 210; the second isolation material layer is planarized until the bottom surface of the first isolation layer 210 and the second surface 204 of the active region 201 are exposed.

In this embodiment, the process of forming the second isolation material layer includes a deposition process or a spin coating process, for example, a chemical vapor deposition process or a physical vapor deposition process. The process for planarizing the second isolation material layer includes a chemical mechanical polishing process and the like.

Referring to fig. 19, fig. 19 is the same as the view direction of fig. 17, and after the second isolation structures 270 are formed, second doped regions U2 are formed on the second side 204 of each active region 201.

In the first direction X, the second doped region U2 is located at two sides of the second isolation structure 270, and the depth of the second doped region U2 is smaller than the height H2 of the second isolation structure 270 in the direction perpendicular to the second plane 204 (as shown in fig. 18).

In this embodiment, the method for forming the second doped region U2 includes: after the second isolation structure 270 is formed, an ion implantation process is performed on the second side 204 to implant dopant ions into the first substrate 200 to form the second doped region U2. The doping ions comprise N-type ions or P-type ions.

In the present embodiment, the second isolation structure 270 is formed before the second doped region U2.

In other embodiments, the second isolation structure is formed after the second doped region is formed.

Referring to fig. 20 and 21, fig. 20 is a schematic top view along the direction N in fig. 21, fig. 21 is a schematic cross-sectional view along the direction C1-C2 in fig. 20, after forming the second doped region U2, a plurality of capacitor structures 280 are formed on a plurality of active regions 201, and the capacitor structures 280 and the bit line structures 250 are respectively located on two opposite surfaces of the first substrate 200.

Specifically, the plurality of capacitor structures 280 in this embodiment are located on the second surface 204.

On one hand, since the bit line structure 250 and the capacitor structure 280 are formed on two opposite surfaces (the first surface 203 and the second surface 204) of the first substrate 200, and the word line grid structure 220 is formed in the first isolation layer 210 and the first substrate 200, the positions of the capacitor structure 280, the word line grid structure 220 and the bit line structure 250 do not need to be mutually avoided, so that the wiring manner of the word line grid structure 220 and the bit line structure 250 can be simplified, the degree of freedom of the arrangement position of the capacitor structure 280 is improved, and the difficulty of the manufacturing process is reduced.

On the other hand, the plurality of active regions 201 can be distributed in the first substrate 200 in a uniform grid pattern by the shape of the projection 2011 of the active regions 201 and the arrangement of the plurality of active regions 201, and therefore, in the process of planarizing the first substrate 200 from the second surface 204, the stop positions of the respective regions of the first substrate 200 are easily approached or the same, which is advantageous for making the uniformity of the characteristics of the respective regions of the semiconductor structure good, and improving the performance of the semiconductor structure.

Furthermore, the shape of the projection 2011 of the active region 201, the arrangement mode of the active regions 201, and the position and arrangement mode of the word line gate structure 220 can efficiently utilize the space in the direction perpendicular to the surface of the first substrate 200, thereby greatly saving the area occupied in the direction along the surface of the first substrate 200, effectively improving the density of the memory array unit, and improving the storage capacity to improve the performance of the semiconductor structure.

In this embodiment, each 2 capacitor structures 280 are located on the second surface 204 of 1 active region 201, and in the first direction X, the 2 capacitor structures 280 are respectively located on two sides of the second isolation structure 270 penetrating through the 1 active region 201.

Specifically, each capacitor structure 280 is electrically connected to the second doped region U2 on one of two sides of the second isolation structure 270. Thereby, the storage capacity of the memory is further increased.

In this embodiment, a projection of the capacitor structure 280 on the second surface 204 is at least partially overlapped with the second doped region U2.

Since the projection of the capacitor structure 280 on the second surface 204 at least partially coincides with the second doped region U2, the capacitor structure 280 and the second doped region U2 can be electrically connected, so that the freedom of the arrangement position and the structure shape of the capacitor structure 280 is large, and the capacitor structure 280 can have a larger volume to increase the capacity of the memory.

In this embodiment, the capacitor structure 280 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

The material of the dielectric layer comprises: high-K materials such as titanium oxide, zirconium oxide, hafnium oxide, and the like.

In the present embodiment, before the capacitor structure 280 is formed, a second conductive structure 281 is formed on the second doped region U2 on each side of the second isolation structure 270 along the first direction X.

The second conductive structure 281 is used to electrically connect the capacitor structure 280 and the second doped region U2.

The process window size for forming the capacitor structure 280 can be increased by the second conductive structure 281. Specifically, the structure flexibility of the second conductive structure 281 is high, and therefore, by adjusting the structure of the second conductive structure 281, for example, making the projection of the second conductive structure 281 on the second surface 204 offset from the projection of the second doped region U2 on the second surface 204, or making the projection range of the second conductive structure 281 on the second surface 204 exceed the range of the second doped region U2, etc., the flexibility of the arrangement manner of the capacitor structure 280 can be further improved, and the limitation on the shape structure of the capacitor structure 280 can be reduced. Thus, the process window size for forming the capacitor structure 280 is increased. In addition, the risk of open circuit between the capacitor structure 280 and the second doped region U2 is also reduced by the second conductive structure 281.

In particular, the projection of the capacitive structure 280 on the second side 204 at least partially coincides with the projection of the second conductive structure 281 on the second side 204. The capacitive structure 280 may be offset in any direction with respect to the second conductive structure 281.

In this embodiment, the second conductive structure 281 is a conductive plug. The material of the second conductive structure 281 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In other embodiments, the second conductive structure is not formed, and the capacitor structure is in direct contact with the second doped region. Thus, the process steps are reduced and the manufacturing efficiency is improved.

In this embodiment, the method of forming the second conductive structure 281 includes: forming a second dielectric layer 290 on the second side 204; forming a plurality of second conductive structure openings (not shown) in the second dielectric layer 290, wherein the second conductive structure openings expose a portion of the surface of the second doped region U2; the second conductive structure openings are filled with the material of the second conductive structure 281.

In this embodiment, the material of the second dielectric layer 290 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In the present embodiment, after the capacitor structures 280 are formed, a conductive layer 282 is formed between the capacitor structures 280. The conductive layer 282 is made of material with good conductivity and good filling capability, such as SiG and tungsten.

Note that the conductive layer 282 is not shown in fig. 20 for ease of understanding.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 20 and fig. 21, the semiconductor structure includes:

a first substrate 200, where the first substrate 200 includes a plurality of active regions 201 (as shown in fig. 2) arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y form an acute included angle α, a projection 2011 (as shown in fig. 2) of each active region 201 on a surface of the first substrate 200 is a diamond, and a diagonal of the diamond is parallel to or perpendicular to the first direction X;

a first isolation layer 210 positioned between adjacent active regions 201;

the word line grid structures 220 are located in the first substrate 200 and the first isolation layer 210 and are independent of each other, the word line grid structures 220 are arranged along a first direction X and extend along a third direction Z, each word line grid structure 220 penetrates through 2 adjacent rows of active regions 201 in the first direction X along the third direction Z, and the third direction Z is perpendicular to the first direction X;

a plurality of bit line structures 250, each bit line structure 250 being located on 1 column of active regions 201 arranged in the second direction Y;

a plurality of capacitor structures 280 are positioned on the plurality of active regions 201, and the capacitor structures 280 and the bit line structures 250 are positioned on two opposite surfaces of the first substrate 200, respectively.

On one hand, since the bit line structure 250 and the capacitor structure 280 are respectively located on two opposite surfaces of the first substrate 200, and the word line gate structure 220 is located in the first isolation layer 210 and the first substrate 200, the semiconductor structure is simpler to wire, and the distance between the bit line structure 250 and the capacitor structure 280 is larger, so that parasitic capacitance generated by wire routing, parasitic capacitance generated between the bit line structure 280 and the capacitor structure 280, and the like are reduced, thereby reducing the difficulty in manufacturing the capacitor of the memory.

On the other hand, the shape of the projection 2011 of the active region 201 on the surface of the first substrate 200, the arrangement manner of the active regions 201, and the position and arrangement manner of the word line gate structure 220 can efficiently utilize the space in the direction perpendicular to the surface of the first substrate 200, so that the area required to be occupied in the direction along the surface of the first substrate 200 is greatly saved, thereby effectively improving the density of the memory array unit, improving the storage capacity, and improving the performance of the semiconductor structure.

In addition, each bit line structure 250 is located on 1 row of active regions 201 arranged in the second direction Y, and the first direction X and the second direction Y form an acute included angle α, so that the distance between adjacent bit line structures 250 can be increased, thereby reducing the parasitic capacitance of the bit line structures 250, improving the performance of the semiconductor structure, and reducing the difficulty in manufacturing the capacitor of the memory.

The material of the first substrate 200 is a semiconductor material.

Specifically, the material of the first substrate 200 includes silicon.

Specifically, the first substrate 200 includes a first side 203 and a second side 204 opposite to each other, the bit line structure 250 is located on the first side 203, the capacitor structure 280 is located on the second side 204, and the second side 204 exposes the bottom surface of the first isolation layer 210.

In the present embodiment, T3 (shown in fig. 9) is larger than WB (shown in fig. 13), the T3 is the maximum distance between the edges of the projection 2011 in the vertical direction along the second direction Y, and the WB bit line structures 250 have a line width in the vertical direction along the second direction Y. Therefore, short circuit risks between adjacent bit line structures are reduced, and reliability of the semiconductor structure is improved.

In the present embodiment, the centers of the adjacent projections 2011 have a first distance W1 in the third direction Z (as shown in fig. 9), the first distance W1 is smaller than 2 times T1 (as shown in fig. 9), and the T1 is the maximum distance between the center of the projection 2011 and the edge of the projection 2011 in the third direction Z.

In the present embodiment, the centers of the adjacent projections 2011 have a second spacing W2 in the first direction X (as shown in fig. 9), and the second spacing W2 is greater than the width WZ of the word line gate structure 220 in the first direction X (as shown in fig. 9).

In the present embodiment, the second distance W2 is also smaller than 2 times T2 (as shown in fig. 9), and the T2 is the maximum distance between the center of the projection 2011 and the edge of the projection 2011 in the first direction X.

In this embodiment, the word line gate structure 220 includes: a gate (not shown) located in the first recess 211 (shown in fig. 6-8); a gate dielectric layer (not shown) between the gate and the first substrate 200.

In the present embodiment, the material of the first isolation layer 210 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In the present embodiment, the material of the bit line structure 250 includes a metal including one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In this embodiment, the semiconductor structure further includes: the first doping region U1 is located at the first side 203 of each active region 201, and each bit line structure 250 is electrically connected to the first doping regions U1 of 1 column of active regions 201 arranged in the second direction Y.

The first doping region U1 has doping ions therein. The doped ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a capping dielectric layer 230 on the top surface of the word line gate structure 220, wherein the capping dielectric layer 230 is further located in the first isolation layer 210.

In this embodiment, the semiconductor structure further includes: a first conductive structure 240 located on each first doped region U1.

In other embodiments, the bit line structure and the first doped region do not have the first conductive structure therebetween, and the bit line structure is in direct contact with the surface of the first doped region.

In this embodiment, the semiconductor structure further includes: a first dielectric layer 260 surrounding each first conductive structure 240 and each bitline structure 250.

The material of the first dielectric layer 260 comprises a dielectric material comprising silicon oxide or a low K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, the semiconductor structure further includes: a plurality of second isolation structures 270 located in the first substrate 200, wherein the second side 204 exposes a bottom surface of the second isolation structures 270.

In a direction perpendicular to the second face 204, a height H2 (shown in fig. 18) of the second isolation structure 270 is less than a height H1 (shown in fig. 8) of the first isolation layer 210.

In this embodiment, the semiconductor structure further includes: a second doped region U2 located at the second side 204 of each active region 201.

The second doping region U2 has doping ions therein. The doped ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In the present embodiment, each capacitor structure 280 is electrically connected to the second doped region U2 on one of the two sides of the second isolation structure 270. Thereby, the storage capacity of the memory is further increased.

In particular, the projection of the capacitor structure 280 on the second surface 204 at least partially coincides with the second doped region U2.

In this embodiment, the semiconductor structure further includes: a second conductive structure 281 between each of the capacitor structures 280 and the second doped region U2. The second conductive structure 281 is used to electrically connect the capacitor structure 280 and the second doped region U2.

In other embodiments, the semiconductor structure does not include a second conductive structure, and the capacitor structure is in direct contact with the second doped region.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 290 between the second conductive structures 281.

In this embodiment, the material of the second dielectric layer 290 includes a dielectric material including silicon oxide or a low K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In this embodiment, the semiconductor structure further includes: a conductive layer 282 between the capacitor structures 280. The conductive layer 282 is made of material with good conductivity and good filling capability, such as SiG and tungsten.

In this embodiment, the semiconductor structure further includes: and a second substrate 300 bonded to the first substrate 200, wherein the first surface 203 faces a surface of the second substrate 200.

Referring to fig. 22 and 23 on the basis of fig. 9 and 10, fig. 22 is a schematic top view structure along the direction M in fig. 23, fig. 23 is a schematic cross-sectional structure along the direction L1-L2 in fig. 22, after forming the capping dielectric layer 230, a plurality of second isolation structures 470 are formed in the first substrate 200, and the first surface 203 exposes the top surfaces of the second isolation structures 470.

In a direction perpendicular to the first face 203, a height P2 of the second isolation structure 470 is less than a height H1 of the first isolation layer 210.

The second isolation structures 470 are located between adjacent word line gate structures 220, and each second isolation structure 470 penetrates through 1 row of the active regions 201 along the third direction Z.

The second isolation structure 470 is used to separate adjacent second doping regions formed subsequently, so as to insulate the adjacent second doping regions.

In the present embodiment, the bottom surface of the second isolation structure 470 in the direction toward the second surface 204 is lower than half of the height of the word line gate structure 220. Accordingly, leakage current between adjacent word line gate structures 220 is further reduced, and reliability of the semiconductor structure is improved.

In the present embodiment, the material of the second isolation structure 470 includes a dielectric material, which includes silicon oxide or a low-K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In this embodiment, the method of forming the second isolation structure 470 includes: forming a fourth mask layer (not shown) on the first surface 203, wherein the fourth mask layer exposes partial surfaces of the active regions 201 and partial top surfaces of the first isolation layers 210; etching the first substrate 200 by using the fourth mask layer as a mask, and forming a plurality of second isolation openings (not shown) in the first substrate 200; forming a second layer of isolation material (not shown) within the second isolation opening, on the top surface of the first isolation layer 210 and on the first side 203 of the active region 201, the second layer of isolation material having a surface higher than the top surface of the first isolation layer 210; the second isolation material layer is planarized until the top surface of the first isolation layer 210 and the first side 203 of the active region 201 are exposed.

For ease of understanding, fig. 22 schematically shows: the projection 2011 of 2 rows of active regions 201 adjacent in the first direction X on the surface of the first substrate 200.

Referring to fig. 24, in the view direction of fig. 24 and fig. 22, after forming the second isolation structures 470, second doped regions Q2 are formed on the first side 203 of each active region 201.

In the first direction X, the second doping region Q2 is located at two sides of the second isolation structure 470, and in a direction perpendicular to the first face 203, the depth of the second doping region Q2 is smaller than the height P2 of the second isolation structure 470 (as shown in fig. 23).

Note that, for ease of understanding, fig. 24 schematically shows: the projection 2011 of 2 rows of active regions 201 adjacent in the first direction X on the surface of the first substrate 200.

In this embodiment, the method for forming the second doped region Q2 includes: after the second isolation structure 470 is formed, an ion implantation process is performed on the first surface 203 to implant dopant ions into the first substrate 200, so as to form the second doped region Q2.

The doped ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

Referring to fig. 25 and 26, fig. 25 is a schematic top view along the direction M in fig. 26, fig. 26 is a schematic cross-sectional view along the direction L1-L2 in fig. 25, and after forming the second doped region Q2, a plurality of capacitor structures 480 are formed on the active regions 201.

In this embodiment, several capacitor structures 480 are located on the first side 203.

In this embodiment, each 2 capacitor structures 480 are located on the first surface 203 of the 1 active region 201, and in the first direction X, the 2 capacitor structures 480 are respectively located on two sides of the second isolation structure 470 that penetrates through the 1 active region 201.

Specifically, each capacitor structure 480 is electrically connected to the second doped region Q2 on one of two sides of the second isolation structure 470. Thereby, the storage capacity of the memory is further increased.

In this embodiment, a projection of the capacitor structure 480 on the first surface 203 at least partially coincides with the second doped region Q2.

Since the projection of the capacitor structure 480 on the first surface 203 at least partially overlaps the second doped region Q2, the electrical connection between the capacitor structure 480 and the second doped region Q2 can be realized, the degree of freedom of the arrangement position and the structure shape of the capacitor structure 480 is large, and the capacitor structure 480 can have a larger volume to increase the capacity of the memory.

In this embodiment, the capacitor structure 480 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

In the present embodiment, before forming the capacitor structure 480, the second conductive structure 481 is formed on the second doped region Q2 on each side of the second isolation structure 470 along the first direction X.

The second conductive structure 481 is used to electrically connect the capacitor structure 480 and the second doped region Q2.

The process window size for forming the capacitive structure 480 can be increased by the second conductive structure 481. Specifically, the structural flexibility of the second conductive structure 481 is high, and therefore, by adjusting the structure of the second conductive structure 481, for example, by shifting the projection of the second conductive structure 481 on the first surface 203 with respect to the projection of the second doped region Q2 on the first surface 203, or by making the projection range of the second conductive structure 481 on the first surface 203 exceed the range of the second doped region Q2, the flexibility of the arrangement mode of the capacitor structure 480 can be further improved, and the limitation on the shape structure of the capacitor structure 480 can be reduced. Thus, the process window size for forming the capacitor structure 480 is increased. In addition, the risk of an open circuit between the capacitor structure 480 and the second doped region Q2 is also reduced by the second conductive structure 481.

In particular, a projection of the capacitive structure 480 on the first side 203 at least partially coincides with a projection of the second conductive structure 481 on the first side 203. The capacitive structure 480 may be offset in any direction with respect to the second conductive structure 481.

In this embodiment, the second conductive structure 481 is a conductive plug. The material of the second conductive structure 481 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In the present embodiment, the method of forming the second conductive structure 481 includes: forming a fourth dielectric layer 490 on the first side 203; forming a plurality of second conductive structure openings (not shown) in the fourth dielectric layer 490, wherein the second conductive structure openings expose a portion of the surface of the second doped region Q2; the second conductive structure 481 is filled with the material of the second conductive structure in the second conductive structure opening.

In this embodiment, the material of the fourth dielectric layer 490 includes a dielectric material including silicon oxide or a low K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In this embodiment, after the capacitor structures 480 are formed, a conductive layer 482 is formed between the capacitor structures 480, and a surface of the conductive layer 482 is higher than a surface of the capacitor structures 480. The conductive layer 482 includes a material with good conductivity and good filling capability, such as SiG and tungsten.

Note that the conductive layer 482 is not shown in fig. 25 for ease of understanding.

Referring to fig. 27 and 28, fig. 27 is a schematic top view along the direction N in fig. 28, and fig. 27 is a schematic cross-sectional view along the direction L3-L4 in fig. 28, providing a second substrate 500.

In this embodiment, the second substrate 500 has a logic circuit (not shown) therein. The logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

With continued reference to fig. 27 and 28, after the conductive layer 482 is formed, the first substrate 200 and the second substrate 500 are bonded with the first side 203 facing the surface of the second substrate 500.

The logic circuit is electrically connected to the word line gate structure 220 and the subsequently formed bit line structure, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220 and the bit line structure, respectively, to control writing and reading of the memory.

With continued reference to fig. 27 and 28, after bonding the first substrate 200 and the second substrate 300, the first substrate 200 is planarized from the second side 204 until the bottom surface of the first isolation layer 210 is exposed.

Referring to fig. 29, fig. 29 is a view similar to that of fig. 27. after the first substrate 200 is planarized from the second side 204, a first doped region Q1 is formed on the second side 204 of each active region 201.

In this embodiment, the method for forming the first doped region Q1 includes: after the first substrate 200 is planarized from the second side 204, an ion implantation process is performed on the second side 204 to implant dopant ions into the first substrate 200, so as to form the first doped region Q1.

Referring to fig. 30 and 31, fig. 30 is a schematic top view of the structure along the direction N in fig. 31, fig. 31 is a schematic cross-sectional view of the structure along the direction L3-L4 in fig. 30, after the first doped region Q1 is formed, 1 bit line structure 450 is formed on each row of active regions 201 arranged along the second direction Y, and the bit line structure 450 and the capacitor structure 480 are respectively located on two opposite surfaces of the first substrate 200.

On one hand, since the bit line structure 450 and the capacitor structure 480 are respectively formed on two opposite surfaces (the first surface 203 and the second surface 204) of the first substrate 200, and the word line grid structure 220 is formed in the first isolation layer 210 and the first substrate 200, the positions of the capacitor structure 480, the word line grid structure 220 and the bit line structure 450 do not need to be mutually avoided, so that the wiring modes of the word line grid structure 220 and the bit line structure 450 can be simplified, the degree of freedom of the arrangement position of the capacitor structure 480 is improved, and the difficulty of the manufacturing process is reduced.

Furthermore, the shape of the projection 2011 of the active region 201, the arrangement of the active regions 201, and the position and arrangement of the word line gate structure 220 can efficiently utilize the space in the direction perpendicular to the surface of the first substrate 200, thereby greatly saving the area occupied in the direction along the surface of the first substrate 200, effectively improving the density of the memory array unit, improving the storage capacity, and improving the performance of the semiconductor structure.

In addition, because 1 bit line structure 250 is formed on each row of active regions 201 arranged along the second direction Y, and an acute included angle α is formed between the second direction Y and the first direction X, the distance between adjacent bit line structures 250 is increased, thereby reducing the parasitic capacitance of the bit line structures 250 and improving the performance of the semiconductor structure.

In the present embodiment, the bit line structure 450 is located on the second side 204. And, each bit line structure 450 is electrically connected to the first doping regions Q1 of the 1 column of active regions 201 arranged in the second direction Y.

In the present embodiment, the maximum separation T3 (shown in fig. 9) between the edges of the projection 2011 in the vertical direction along the second direction Y is greater than WM, which is the line width of the bitline structure 450 in the vertical direction along the second direction Y. Therefore, short circuit risks between adjacent bit line structures are reduced, and reliability of the semiconductor structure is improved.

The material of the bitline structure 450 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In the present embodiment, the method for forming the bit line structures 450 includes: forming a third dielectric layer 460 on the second side 204; forming a second mask layer (not shown) on the surface of the third dielectric layer 460, wherein the second mask layer exposes a part of the surface of the third dielectric layer 460; etching the third dielectric layer 460 by using the second mask layer as a mask until the surface of the first doping region Q1 is exposed, and forming a plurality of bit line openings (not shown) in the third dielectric layer 460; forming a bit line material layer (not shown) in the bit line opening and on the surface of the third dielectric layer 460, wherein the surface of the bit line material layer is higher than the surface of the third dielectric layer 460; the bit line material layer is planarized until the surface of the third dielectric layer 460 is exposed.

In this embodiment, the process of forming the third dielectric layer 460 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In this embodiment, the etching process for forming the bit line opening includes at least one of a dry etching process and a wet etching process.

In the present embodiment, the process of forming the bit line material layer includes a metal plating process, a chemical vapor deposition process, and the like.

In the present embodiment, the process for planarizing the bit line material layer includes a chemical mechanical polishing process.

In this embodiment, the material of the third dielectric layer 460 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K (K less than 3.9) material. The low K material is used to further reduce the parasitic capacitance through the low dielectric constant material.

In other embodiments, a first conductive structure is formed on each first doped region prior to forming the bit line structure, the first conductive structure being used to electrically connect the bit line structure and the first doped region. The first conductive structure is a conductive plug, the material of the first conductive structure comprises a metal or silicon, and the metal comprises one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum in combination.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 30 and fig. 31, the semiconductor structure includes:

a first isolation layer 210 positioned between adjacent active regions 201;

a plurality of bit line structures 450, each bit line structure 450 being located on 1 column of active regions 201 arranged in the second direction Y;

a plurality of capacitor structures 480 located on the plurality of active regions 201, wherein the capacitor structures 480 and the bit line structures 450 are located on two opposite surfaces of the first substrate 200, respectively.

On one hand, since the bit line structure 450 and the capacitor structure 480 are respectively located on two opposite surfaces of the first substrate 200, and meanwhile, the word line gate structure 220 is located in the first isolation layer 210 and the first substrate 200, the wiring of the semiconductor structure is simpler, and the distance between the bit line structure 450 and the capacitor structure 480 is larger, so that the parasitic capacitance generated by the wiring, the parasitic capacitance generated between the bit line structure 450 and the capacitor structure 480, and the like are reduced, thereby reducing the difficulty in manufacturing the capacitor of the memory.

In addition, each bit line structure 450 is located on 1 row of active regions 201 arranged in the second direction Y, and the first direction X and the second direction Y form an acute included angle α, so that the distance between adjacent bit line structures 450 can be increased, thereby reducing the parasitic capacitance of the bit line structures 450, improving the performance of the semiconductor structure, and reducing the difficulty in manufacturing the capacitor of the memory.

For the detailed explanation of the first substrate 200, the word line gate structure 220, the first isolation layer 210 and the capping dielectric layer 230 in this embodiment, refer to the related explanation in the embodiments shown in fig. 2 to fig. 21, and are not repeated herein.

In particular, the first substrate 200 includes opposing first and

second sides

203, 204.

In the present embodiment, the plurality of capacitor structures 480 are located on the first surface 203, the bit line structures 450 are located on the second surface 204, and the second surface 204 exposes the bottom surface of the first isolation layer 210.

In the present embodiment, the maximum separation T3 (shown in fig. 9) between the edges of the projection 2011 in the vertical direction along the second direction Y is greater than WM (shown in fig. 30), which is the line width of the bitline structure 450 in the vertical direction along the second direction Y. Therefore, short circuit risks between adjacent bit line structures are reduced, and reliability of the semiconductor structure is improved.

In the present embodiment, the material of the bit line structure 450 includes a metal including one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, the semiconductor structure further includes: a plurality of second isolation structures 470 located within the first substrate 200, the first side 203 exposing top surfaces of the second isolation structures 470.

In a direction perpendicular to the first face 203, a height P2 (shown in fig. 23) of the second isolation structure 470 is less than a height H1 (shown in fig. 23) of the first isolation layer 210.

In this embodiment, the semiconductor structure further includes: a second doped region Q2 located at the first side 203 of each active region 201, the second doped region Q2 located at two sides of the second isolation structure 470 in the first direction X, and each capacitor structure 480 electrically connected with the second doped region Q2 at one of the two sides of the second isolation structure 470.

In a direction perpendicular to the first face 203, a depth of the second doped region Q2 is less than a height P2 of the second isolation structure 470 (as shown in fig. 23).

The second doping region Q2 has doping ions therein. The doped ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a second conductive structure 481 is located between each capacitive structure 480 and the second doped region Q.

In other embodiments, the semiconductor structure does not include a second conductive structure, and the capacitor structure is in direct contact with the second doped region. Thus, the process steps are reduced and the manufacturing efficiency is improved.

In this embodiment, the semiconductor structure further includes: a fourth dielectric layer 490 between the second conductive structures 481.

In this embodiment, the material of the fourth dielectric layer 490 includes a dielectric material including silicon oxide or a low K (K less than 3.9) material.

In this embodiment, the semiconductor structure further includes: the conductive layer 482 located between the capacitor structures 480 is also higher on the surface of the conductive layer 482 than on the surface of the capacitor structures 480 in the direction from the second side 204 to the first side 203. The conductive layer 482 includes a material with good conductivity and good filling capability, such as SiG and tungsten.

In this embodiment, the semiconductor structure further includes: the first doping regions Q1 located at the second side 204 of each active region 201, and each bit line structure 450 is electrically connected to the first doping regions Q1 of 1 column of active regions 201 arranged in the second direction Y.

The first doping region Q1 has doping ions therein. The doped ions comprise N-type ions or P-type ions, the N-type ions comprise phosphorus ions, arsenic ions or antimony ions, and the P-type ions comprise boron ions, boron fluorine ions or indium ions.

In this embodiment, the semiconductor structure further includes: a third dielectric layer 460 on the second side 204 and the bottom surface of the first isolation layer 210, and the bit line structure 450 is located in the third dielectric layer 460.

In other embodiments, the semiconductor structure further comprises: and the first conductive structure is positioned on each first doping region and is used for electrically connecting the bit line structure and the first doping region. The first conductive structure is a conductive plug, the material of the first conductive structure comprises a metal or silicon, and the metal comprises one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum in combination.

In this embodiment, the semiconductor structure further includes: and a second substrate 500 bonded to the first substrate 200, the first surface 203 facing a surface of the second substrate 500.

In this embodiment, the second substrate 500 has a logic circuit (not shown) therein.

In the present embodiment, the logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

The logic circuit is electrically connected to the word line gate structure 220 and the bit line structure 450, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220 and the bit line structure 450, respectively, to control writing and reading of the memory.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the array substrate comprises a first substrate and a second substrate, wherein the first substrate comprises a plurality of active regions which are arrayed along a first direction and a second direction, the first direction and the second direction form an acute included angle, the projection of each active region on the surface of the first substrate is a rhombus, a circle or an ellipse, and the diagonal line of the rhombus is parallel to or perpendicular to the first direction;

a first isolation layer between adjacent active regions;

the word line grid structures are arranged along a first direction and extend along a third direction, each word line grid structure penetrates through 2 adjacent rows of active regions in the first direction along the third direction, and the third direction is perpendicular to the first direction;

a plurality of bit line structures, each bit line structure being located on 1 column of active regions arranged in the second direction;

and the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate.

2. The semiconductor structure of claim 1, further comprising: and the second isolation structures are positioned in the first substrate, are positioned between adjacent word line gate structures, penetrate through 1 row of active regions along the third direction, and are lower than the first isolation layer in the direction vertical to the surface of the first substrate.

3. The semiconductor structure of claim 2, wherein the first substrate includes opposing first and second sides, the bitline structure being on the first side, the capacitance structure being on the second side, the second side exposing a bottom surface of the second isolation structure.

4. The semiconductor structure of claim 3, wherein the first doped region is located on a first side of each active region, and wherein each bitline structure is electrically connected to the first doped regions of 1 column of active regions arranged in the second direction.

5. The semiconductor structure of claim 3, wherein a top surface of the second isolation structure in a direction toward the first surface is higher than one-half of a height of the word line gate structure.

6. The semiconductor structure of claim 3, wherein 2 capacitive structures are located on the second side of 1 active region, and wherein the 2 capacitive structures are located on either side of a second isolation structure that extends through the 1 active region in the first direction.

7. The semiconductor structure of claim 6, wherein the second doped region is located on a second side of each active region, the second doped region is located on both sides of the second isolation structure in the first direction, a depth of the second doped region is less than a height of the second isolation structure in a direction perpendicular to the second side, and each capacitive structure is electrically connected to the second doped region on one of the two sides of the second isolation structure.

8. The semiconductor structure of claim 7, wherein a projection of the capacitive structure on the second face at least partially coincides with the second doped region.

9. The semiconductor structure of claim 2, wherein the first substrate includes opposing first and second sides, the capacitor structure being located on the first side, the bit line structure being located on the first side, the first side exposing a top surface of the second isolation structure.

10. The semiconductor structure of claim 9, wherein the first doped region is located at the second side of each active region, and wherein each bitline structure is electrically connected to the first doped regions of 1 column of active regions arranged in the second direction.

11. The semiconductor structure of claim 9, wherein a bottom surface of the second isolation structure in a direction toward the second surface is less than one-half of a height of the word line gate structure.

12. The semiconductor structure of claim 9, in which every 2 capacitive structures are located on a first side of 1 active region, and, in the first direction, the 2 capacitive structures are located on both sides of a second isolation structure that extends through the 1 active region.

13. The semiconductor structure of claim 12, wherein the second doped region is located on a first side of each active region, the second doped region is located on both sides of the second isolation structure in the first direction, a depth of the second doped region is less than a height of the second isolation structure in a direction perpendicular to the first side, and each capacitive structure is electrically connected to the second doped region on one of the two sides of the second isolation structure.

14. The semiconductor structure of claim 13, wherein a projection of the capacitive structure on the first side at least partially coincides with the second doped region.

15. The semiconductor structure of claim 4 or 10, further comprising: a first conductive structure located on each first doped region.

16. The semiconductor structure of claim 8 or 14, further comprising: a second conductive structure located between each capacitive structure and the second doped region.

17. The semiconductor structure of claim 1, wherein an acute included angle between the first direction and the second direction is in a range from 25 degrees to 65 degrees.

18. The semiconductor structure of claim 1, wherein in the third direction, adjacent active regions have a first spacing between centers of projections of the first substrate surface that is less than 2 times T1, the T1 being a maximum spacing in the third direction between centers and edges of projections of the active regions on the first substrate surface.

19. The semiconductor structure of claim 1, wherein in the first direction, adjacent active regions have a second spacing between centers of projections of the first substrate surface, the second spacing being less than 2 times T2, the T2 being a maximum spacing in the first direction between centers and edges of projections of the active regions on the first substrate surface.

20. The semiconductor structure of claim 1, wherein a top surface of the word line gate structure is lower than a top surface of the first isolation layer, the semiconductor structure further comprising: and the covering dielectric layer is positioned on the top surface of the word line gate structure and is also positioned in the first isolation layer.

21. A method of forming a semiconductor structure, comprising:

providing a first substrate, wherein the first substrate comprises a plurality of active regions arrayed along a first direction and a second direction, the first direction and the second direction form an acute included angle, the projection of each active region on the surface of the first substrate is a rhombus, a circle or an ellipse, and the diagonal of the rhombus is parallel to or perpendicular to the first direction;

forming a first isolation layer between adjacent active regions;

forming a plurality of mutually independent word line grid structures in the first substrate and the first isolation layer, wherein the word line grid structures are arranged along a first direction and extend along a third direction, each word line grid structure penetrates through 2 adjacent rows of active regions in the first direction along the third direction, and the third direction is perpendicular to the first direction;

after the word line gate structure is formed, 1 bit line structure is formed on each row of active regions arranged along the second direction;

after the word line grid structure is formed, a plurality of capacitor structures are formed on a plurality of active regions, and the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate.

22. The method of forming a semiconductor structure of claim 21, wherein the method of forming a number of the word line gate structures comprises: forming a plurality of first grooves in the plurality of active regions and the first isolation layer, wherein the plurality of first grooves are distributed along a first direction and extend along a third direction, the depth of each first groove is smaller than the height of the first isolation layer, and the inner wall surface of each first groove exposes the first isolation layer and 2 rows of active regions adjacent to each other in the first direction; and forming a plurality of word line gate structures in the plurality of first grooves.

23. The method of forming a semiconductor structure of claim 21, wherein a top surface of the word line gate structure is lower than a top surface of the first isolation layer, the method of forming a semiconductor structure further comprising: after forming a plurality of word line gate structures, forming a covering dielectric layer in the first groove, wherein the covering dielectric layer is positioned on the top surfaces of the word line gate structures.

24. The method of forming a semiconductor structure of claim 21, wherein the first substrate includes opposing first and second sides, the bitline structure being on the first side, the capacitance structure being on the second side.

25. The method of forming a semiconductor structure of claim 24, further comprising: after forming the word line gate structure and before forming the bit line structure, a first doped region is formed at a first side of each active region.

26. The method of forming a semiconductor structure of claim 25, further comprising: providing a second substrate; bonding the first substrate and the second substrate after forming the bit line structure, wherein the first surface faces to the surface of the second substrate.

27. The method of forming a semiconductor structure of claim 26, further comprising: after the first substrate and the second substrate are bonded, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; and after the first substrate is planarized from the second surface of the first substrate, forming a plurality of second isolation structures in the first substrate, wherein the second isolation structures are exposed from the second surface, the height of each second isolation structure is smaller than that of the first isolation layer in the direction perpendicular to the second surface, the second isolation structures are positioned between the adjacent word line gate structures, and each second isolation structure penetrates through 1 row of active regions along the third direction.

28. The method of forming a semiconductor structure of claim 27, further comprising: after the second isolation structure is formed and before a plurality of capacitor structures are formed, a second doped region is formed on the second surface of each active region, the second doped regions are located on two sides of the second isolation structure in the first direction, and the depth of the second doped region is smaller than the height of the second isolation structure in the direction perpendicular to the second surface.

29. The method of forming a semiconductor structure of claim 21, wherein the first substrate includes opposing first and second faces, the capacitor structure being located on the first face, the bit line structure being located on the second face.

30. The method of forming a semiconductor structure of claim 29, further comprising: after the word line grid structures are formed and before the capacitor structures are formed, a plurality of second isolation structures are formed in the first substrate, the second isolation structures are exposed out of the first surface, the height of each second isolation structure is smaller than that of the corresponding first isolation layer in the direction perpendicular to the first surface, the second isolation structures are located between the adjacent word line grid structures, and each second isolation structure penetrates through 1 row of active regions in the third direction.

31. The method of forming a semiconductor structure of claim 30, further comprising: after the second isolation structure is formed and before the capacitor structure is formed, a second doped region is formed on the first surface of each active region, the second doped regions are located on two sides of the second isolation structure in the first direction, and the depth of the second doped region is smaller than the height of the second isolation structure in the direction perpendicular to the first surface.

32. The method of forming a semiconductor structure of claim 31, further comprising: providing a second substrate; and bonding the first substrate and the second substrate after the capacitor structure is formed, wherein the first surface faces to the surface of the second substrate.

33. The method of forming a semiconductor structure of claim 32, further comprising: after the first substrate and the second substrate are bonded, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; after planarizing the first substrate from the second side of the first substrate, and prior to forming the bit line structures, a first doped region is formed at the second side of each active region.

34. The method of forming a semiconductor structure of claim 25 or 33, further comprising: first conductive structures are formed on each of the first doped regions prior to forming the bitline structures.

35. The method of forming a semiconductor structure of claim 28 or 31, further comprising: and before forming the capacitor structure, forming a second conductive structure on the second doped region on each side of the second isolation structure along the first direction.