CN113539794B - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN113539794B
CN113539794B CN202010322713.5A CN202010322713A CN113539794B CN 113539794 B CN113539794 B CN 113539794B CN 202010322713 A CN202010322713 A CN 202010322713A CN 113539794 B CN113539794 B CN 113539794B
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mask
layer
units
unit
mask unit
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CN113539794A (en
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李天慧
于星
梁慧
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Photosensitive Polymer And Photoresist Processing (AREA)
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Abstract

The invention relates to a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming a first mask unit, a second mask unit and a third mask unit, performing ion implantation on the second mask unit based on the first mask unit and the third mask unit, and forming at least one implantation region and at least one non-implantation region in the second mask unit to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation. The invention can combine the exposure-solidification-exposure-etching process with the inclined ion implantation process, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative development method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the miniaturization of the pattern feature size, does not need special technological process in the whole process, and has simple whole process, low cost and high productivity.

Description

Semiconductor structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
As semiconductor device dimensions continue to shrink, the feature sizes of photolithography approach and even exceed the physical limits of optical lithography, which presents more serious manufacturing process challenges to semiconductor fabrication techniques, and particularly to photolithography. The Double Pattern (Double Pattern) technology is widely applied to the 28 nanometer node technology, can greatly reduce the influence of optical proximity effect, and lightens the problem of single-mode shrinkage (SINGLE PATTERN SHRINKAGE) so as to realize smaller graph feature size (Critical dimension, CD). The double patterning technology may include a LELE (Lithe-Etch-Lithe-Etch, exposure-Etch-expose-Etch) double patterning method, a LFLE (Litho-Freeze-Litho-Etch) double patterning method, and a Self-aligned double patterning (Self-Aligned Double Patterning, SADP) method.
However, in the existing process of preparing the semiconductor device structure by the double-pattern technology, the structure of realizing smaller nodes tends to have complex process steps and preparation flow, higher cost and longer preparation period. After the integrated circuit chip process enters into the node of 7nm and below, the size of the integrated circuit chip after the photoetching technology is applied is difficult to be further reduced as expected, and the requirement of further shrinking the line width of the manufacturing process cannot be met. The technology based on the three-time and four-time patterns greatly increases the cost and limits the application range.
Therefore, it is necessary to provide a semiconductor structure based on dual patterns and a method for fabricating the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used for solving the problems of complex process steps and manufacturing procedures for manufacturing a node device structure with smaller technology in the prior art, low process efficiency, and the like.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate;
Forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units which are arranged at intervals and first gaps between adjacent first mask units, and the first gaps expose the semiconductor substrate;
Forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units which are arranged at intervals and second gaps between adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed by the first gaps, the second gaps expose the semiconductor substrate, the upper surface of each second mask unit is lower than the upper surface of each first mask unit, and each first mask unit passes through the corresponding second gap;
forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units which are arranged at intervals and third gaps between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
and performing oblique ion implantation on the second mask unit based on shielding of the first mask unit and the third mask unit, and forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit so as to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
Optionally, the first mask layer and the third mask layer are formed through a photolithography process, wherein the step of forming a barrier layer on the surface of the first mask unit is further included after forming the first mask layer.
Optionally, forming the second mask layer through a spin-coating process; the material of the second mask layer comprises a silicon doped anti-reflection layer or a silicon oxide layer.
Optionally, the upper surface of the third mask unit is not lower than the upper surface of the first mask unit.
Optionally, the semiconductor substrate comprises a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, and the step of transferring the pattern on the new etching mask layer to the hard mask layer is further included after the new etching mask layer is formed.
Optionally, the material of the first mask layer is the same as the material of the third mask layer, and the materials of the first mask layer and the third mask layer include photoresist.
Optionally, the first mask units are uniformly arranged at intervals, the third mask units are uniformly arranged at intervals, the first mask units and the third mask units are alternately arranged at intervals, and the widths of the first mask units, the third mask units and the non-injection region are equal.
Optionally, the first gap and the third gap have the same width, and the first mask unit is located at the center of the third gap.
Optionally, positive oblique ion implantation is adopted to form the implantation region, and the implantation region is removed after ion implantation, wherein the first mask unit, the non-implantation region and the second mask unit corresponding to the lower part of the third mask unit form the new etching mask layer.
Optionally, negative inclined ion implantation is adopted to form the implantation region, and the non-implantation region is removed after ion implantation is carried out, wherein the non-implantation region is removed, and the second mask units corresponding to the lower parts of the first mask unit and the third mask unit are removed at the same time, and the implantation region forms the new etching mask layer.
The invention also provides a semiconductor structure, which is preferably prepared based on the preparation method of the semiconductor structure, and can be prepared by adopting other methods, wherein the semiconductor structure comprises the following components:
a semiconductor substrate;
the first mask layer is positioned on the semiconductor substrate and comprises a plurality of first mask units which are arranged at intervals and first gaps between adjacent first mask units, and the first gaps expose the semiconductor substrate;
The second mask layer is positioned on the semiconductor substrate and comprises a plurality of second mask units which are arranged at intervals and second gaps between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed by the first gaps, the second gaps expose the semiconductor substrate, the upper surface of each second mask unit is lower than the upper surface of each first mask unit, and each first mask unit penetrates through the corresponding second gap;
the third mask layer is positioned on the second mask layer and comprises a plurality of third mask units which are arranged at intervals and third gaps between every two adjacent third mask units, wherein the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
The second mask unit further comprises at least one implanted region and at least one non-implanted region subjected to ion implantation to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit.
Optionally, the upper surface of the third mask unit is not lower than the upper surface of the first mask unit; and a blocking layer is also formed on the surface of the first mask unit.
Optionally, the material of the first mask layer is the same as the material of the third mask layer, and the material of the first mask layer and the material of the third mask layer include photoresist; the material of the second mask layer comprises a silicon doped anti-reflection layer or a silicon oxide layer.
As described above, the semiconductor structure and the method for manufacturing the same of the present invention can use the combination of the process of exposure-solidification-exposure-etching and the process of oblique ion implantation, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative development method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the miniaturization of the pattern feature size, does not need special technological process in the whole process, and has simple whole process, low cost and high productivity.
Drawings
Fig. 1 shows a process flow diagram of the preparation of a semiconductor structure of the present invention.
Fig. 2 is a schematic diagram of a semiconductor substrate provided in the preparation of a semiconductor structure according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating formation of a first mask material layer in the fabrication of a semiconductor structure according to an embodiment of the invention.
Fig. 4 (a) is a schematic structural diagram illustrating formation of a first mask layer in preparation of a semiconductor structure according to an embodiment of the present invention.
Fig. 4 (b) is a schematic diagram showing a structure of a barrier layer formed in the preparation of a semiconductor structure according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram illustrating formation of a second mask layer in preparation of a semiconductor structure according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a structure for providing a third mask material layer in the preparation of a semiconductor structure according to an embodiment of the invention.
Fig. 7 is a schematic structural diagram illustrating formation of a third mask layer in preparation of a semiconductor structure according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a structure for performing tilted ion implantation in the preparation of a semiconductor structure according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a structure for forming a new etching mask layer in the preparation of a semiconductor structure according to an embodiment of the invention.
FIG. 10 is a schematic diagram illustrating another embodiment of a new etching mask layer formed in the fabrication of a semiconductor structure.
FIG. 11 is a schematic diagram illustrating a patterned hard mask layer formed in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 12 (a) and 12 (b) show the reaction scheme for forming a silicon-containing polymer layer on the surface layer of the first mask unit using HMDS as a silylating agent in the preparation of the semiconductor structure of the embodiment of the present invention.
Fig. 13 (a) shows the relationship between the etching time and the etching thickness after ion implantation of the second mask unit and the different concentrations of ar+ ions.
Fig. 13 (b) shows the variation of the initial etching rate and the film remaining percentage for the second mask unit as the concentration of the implanted ions increases.
Fig. 14 shows an etched structure image formed after oblique ion implantation for Ar ions.
Description of element reference numerals
100. Semiconductor substrate
100A semiconductor substrate
100B hard mask layer
101. A first mask material layer
102. First mask layer
102A first mask unit
102B first gap
102C barrier layer
103. Second mask layer
103A second mask unit
103B second gap
104. Third mask material layer
105. Third mask layer
105A third mask unit
105B third gap
106. Implantation region
107. Non-implanted regions
108. Masking zone
109. Novel etching mask layer
110. Patterning hard mask layer
S1 to S5 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a method for preparing a semiconductor structure, which includes the following steps:
S1: providing a semiconductor substrate;
S2: forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units which are arranged at intervals and first gaps between adjacent first mask units, and the first gaps expose the semiconductor substrate;
S3: forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units which are arranged at intervals and second gaps between adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed by the first gaps, the second gaps expose the semiconductor substrate, the upper surface of each second mask unit is lower than the upper surface of each first mask unit, and each first mask unit passes through the corresponding second gap;
S4: forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units which are arranged at intervals and third gaps between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
S5: and performing ion implantation on the second mask unit based on the first mask unit and the third mask unit, and forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit so as to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
The semiconductor structure and the method of manufacturing the same of the present invention will be described in detail below with reference to the accompanying drawings. The preparation method of the semiconductor structure provided by the invention is not limited to the above-mentioned sequence of steps, and can be adjusted according to common knowledge in the art, and the embodiment only provides an example of the preparation method of the semiconductor structure of the invention.
First, as shown in S1 and fig. 2 in fig. 1, step S1 is performed to provide the semiconductor substrate 100. The semiconductor base 100 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, or the like. In other embodiments, the semiconductor substrate 100 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, among others. In addition, the semiconductor substrate 100 may be a structure formed of a single material layer, or may be a stacked structure, such as a silicon/germanium-silicon stack. The semiconductor substrate 100 may be an ion doped substrate, may be P-doped, or may be N-doped. The semiconductor substrate 100 may further have a plurality of semiconductor devices formed therein.
As an example, the semiconductor base 100 includes a semiconductor substrate 100a and a hard mask layer 100b formed on the semiconductor substrate 100a, and a pattern on an etching mask layer may be transferred onto the hard mask layer 100b, and the semiconductor substrate 100a is etched based on the patterned hard mask layer 100 b. The material of the hard mask layer 100b includes, but is not limited to, carbon. In addition, the semiconductor substrate 100a may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, or the like, and may be a single-layer material layer or a structure formed of multiple-layer material layers. In this example, the semiconductor substrate 100a is selected to be Si.
Next, as shown in S2 and fig. 3, fig. 4 (a) and fig. 4 (b) in fig. 1, step S2 is performed to form a first mask layer 102 on the semiconductor substrate 100, where the first mask layer 102 includes a plurality of first mask units 102a arranged at intervals and first gaps 102b between adjacent first mask units 102a, and the first gaps 102b expose the semiconductor substrate 100. The first mask layer 102 may be formed by a photolithography process, in an example, the first mask material layer 101 may be formed on the semiconductor substrate 100 first, and then the first mask layer 102 may be formed by a photolithography process based on exposure and development, and optionally, the material of the first mask material layer 101 may include, but is not limited to, a photoresist, which may be a positive photoresist or a negative photoresist, and the first mask material layer 101 may be formed on the surface of the semiconductor substrate 100 by a common means such as spin coating, spray coating, and the like.
In an example, the first mask units 102a are arranged at uniform intervals, and in addition, the height, width, number of the first mask units 102a and the width of the first gaps 102b may be designed according to practical requirements.
In addition, as an example, the step of solidifying (freeze) the first mask unit 102a is further included after forming the first mask layer 102, and after the solidifying process, a barrier layer 102c is formed on the surface of the first mask unit 102 a. The method for solidification can be as follows: 1) Chemical curing, i.e., coating a layer of chemically cured material on the surface of the photoresist, wherein the cured material is composed of resin, a cross-linking agent and a solvent. After baking and rinsing, the wafer leaves an extremely thin crosslinked layer outside the lithography machine pattern, constituting the barrier layer. 2) High temperature cross-linking curing, i.e. adding a temperature activated cross-linking agent into the first layer of photoresist (i.e. the first mask material layer), wherein the activation temperature must be higher than the soft baking (PAB) and post-exposure baking (PEB) temperatures of the photoresist, and after the first layer of photoresist develops, the photoresist pattern is baked at a higher temperature and cross-linking reaction occurs. The crosslinked photoresist image is not affected by the second photolithography process. 3) Ultraviolet curing, namely, the photoresist pattern (namely, the first mask unit) formed by first photoetching is irradiated by 172nm ultraviolet light, and then baking is carried out. 172nm light has only a limited penetration depth in 193nm photoresist and all of the energy at exposure is absorbed by the photoresist surface. These energies will cause the organic polymer on the photoresist surface to split, generating free radicals. These radicals re-react to form crosslinks, curing the photoresist pattern. Of course, other solidification (freeze) methods may be used, and are not limited thereto.
In another example, the material of the first mask material layer 101 is a positive photoresist, which contains a resin and a photoacid generator, wherein the resin structure has an acid-labile or acid-cleavable organic group, and after exposure and baking, the acid-labile or acid-cleavable group in the resin breaks down, and changes from hydrophobic to hydrophilic, so that its solubility in an organic solvent is reduced, while the unexposed portion still maintains the property of high solubility in an organic solvent. By utilizing one characteristic of the positive photoresist, the present embodiment uses a negative developing technique (Negative Tone Develop, NTD) to develop the first mask material layer 101 after exposure and baking, and uses an organic solvent to remove the unexposed area of the first mask material layer. For example, ketone, ether, ester, alcohol, hydrocarbon or amide solvents are used. For example, in this embodiment, an alcohol solvent such as a mixed solution of one or more of 2-heptanone, 4-heptanone, 2-hexanone, 5-methyl-2-hexanone, 2-octanone, 2-nonanone, acetone, cyclohexanone, methylcyclohexanone, acetophenone, acetylacetone, methylethyl ketone, methyl isobutyl ketone, and the like is preferable. Of course, a normal developing method may be used, which is not limited thereto.
Immersing the first mask material layer after baking into the alcohol solvent to fully dissolve the unexposed area. The negative tone development technique can be completed at room temperature, does not require complicated process conditions, and can form fine patterns of a draft resolution. In addition, the technology adopts organic solvent for development, the organic solvent has good solubility to organic matters on the surface of the substrate, the cleanliness of the surface of the substrate is high after development, the organic residues are less, and the pollution to the subsequent process is avoided.
After the negative development, the unexposed area in the first mask material layer 101 is removed, and the exposed area is reserved, so as to form a pattern structure, thereby obtaining the first mask layer 102. After the pattern structure is formed, a silylation process is performed on the pattern structure, that is, the first mask unit 102a is subjected to a silylation process. In the exposure process, the exposed area of the first mask material layer 101 undergoes a photoacid diffusion reaction when receiving light, wherein the photoacid generator generates acid, and the baking process further performs the photoacid diffusion reaction to form a polymer containing hydroxyl (-OH) and/or carboxyl (-COOH) in the pattern structure. And then, when the silylation treatment is carried out, a silicon-containing polymer layer is formed on the surface of the pattern structure. Common silylating agents include Hexamethyldisilazane (HMDS), trimethylchlorosilane (trimethylchlorosilane, TMCS), hexamethyldisilazane (HMDSZ), or other suitable silylating agents. In a preferred embodiment of this embodiment, HMDS is selected as the silylating agent, and the surface layer of the patterned structure undergoes a silylation reaction when the patterned structure is exposed to a gas phase HMDS atmosphere to form a silicon-containing polymer layer on the surface layer. And simultaneously controlling the reaction time and the reaction temperature of the silylation reaction to control the thickness of the silicon-containing polymer layer. In a preferred embodiment, to ensure that the silylation reaction proceeds while ensuring that the photoresist layer within the pattern structure is not damaged, the temperature of the silylation reaction is controlled to be less than 200 ℃, for example, the reaction temperature is controlled to be between 100 ℃ and 200 ℃, more preferably, the reaction temperature is controlled to be between 120 ℃ and 150 ℃, and even more preferably, the reaction temperature is controlled to be about 150 ℃. The reaction time is controlled between 50 seconds and 200 seconds, thereby producing a silicon-containing polymer layer with a thickness of more than 5nm, preferably between 5nm and 10nm, on the surface layer of the pattern structure. The reaction scheme for forming a silicon-containing polymer layer on the surface layer of the pattern structure using the HMDS as a silylating agent described above is shown in fig. 12a and 12 b.
The thickness of the silicon-containing polymer is controlled by controlling the reaction temperature and time in the process of the silylation treatment, and the photoresist layer below the silicon-containing polymer layer can be prevented from being damaged by high temperature, so that the integrity of the first pattern structure is ensured, the line width of the first pattern structure is controlled, and the uniformity and accuracy of the line width of the later etching are ensured.
After the silicon-containing polymer layer is formed, the silicon-containing polymer layer is subjected to a gas treatment to react silicon in the silicon-containing polymer layer with the gas and form a barrier layer 102c, as shown in fig. 4 (b). In this embodiment, the silicon-containing polymer layer is subjected to oxidation treatment, oxygen is introduced into the silicon-containing polymer layer, and the reaction temperature is controlled to cause oxidation reaction between silicon in the silicon-containing polymer and the oxygen to generate the silicon dioxide layer. In the oxidation treatment, in order to ensure that the surface layer oxidation reaction is performed and that the photoresist layer of the inner layer is not damaged, the temperature of the oxidation reaction is controlled to be 150 ℃ or less, for example, the reaction temperature is controlled to be 100 ℃ to 150 ℃, and more preferably, the reaction temperature is controlled to be 130 ℃. In addition, the time of oxidation can be controlled to control the thickness of the resulting silicon dioxide barrier layer. In a preferred embodiment of this embodiment, the reaction time is controlled between 50 seconds and 200 seconds. In this embodiment, the thickness of the resulting silicon dioxide barrier layer is greater than 3nm, preferably between 3nm and 5nm.
The barrier layer 102c is formed on the surface layer of the pattern structure (the first mask unit 102 a) through the above process, and the photoresist is wrapped, so that the first mask unit 102a is frozen, and the first mask unit 102a is not damaged in the subsequent process. The freezing process can well control the thickness of the silicon-containing polymer layer and the silicon dioxide barrier layer generated on the surface layer of the first mask unit 102a by controlling the reaction time and the reaction temperature of the silylation treatment and the oxidation treatment, so that the line width of the first mask unit 102a can be controlled, the line width uniformity of the first mask unit 102a is realized, and the line width uniformity and the accuracy of the later etching are ensured.
Next, as shown in S3 in fig. 1 and fig. 5, step S3 is performed, where a second mask layer 103 is formed on the semiconductor substrate 100, where the second mask layer 103 includes a plurality of second mask units 103a arranged at intervals and second gaps 103b located between adjacent second mask units 103a, where the second mask units 103a are correspondingly formed on the semiconductor substrate 100 exposed by the first gaps 102b, the second gaps 103b are exposed by the semiconductor substrate 100, and the exposure is not limited to a strict sense, but may be referred to as exposing the semiconductor substrate 100 at a portion of the semiconductor substrate 100 where the second mask units 103a are not formed, but other material layers may be formed on the semiconductor substrate 100, where the first mask units 102a pass through the corresponding second gaps 103b, and the upper surface of the second mask units 103a is lower than the upper surface of the first mask units 102 a. In this embodiment, the height of the second mask unit 103a is between 1/5 and 4/5 of the height of the first mask unit 102a, and the height of the second mask unit 103a may be selected to be smaller than 1/2 of the height of the first mask unit 102a, so as to facilitate subsequent ion implantation and new mask preparation.
In an example, an second mask layer 103 is provided, that is, the second mask layer 103 is formed directly on the semiconductor substrate 100, the second mask layer 103 is formed on the semiconductor substrate 100 around the first mask unit 102a, that is, the second mask layer 103 is formed on the semiconductor substrate 100 exposed by the first gap 102b, as shown in fig. 5, the material layer located in the first gap 102b forms a plurality of second mask units 103a, and the position of the first mask unit 102a forms the second gap 103b. Of course, in other embodiments, the positions, the number and the widths of the second mask units 103a and the second gaps 103b may be designed according to actual requirements.
In an example, the material of the second mask layer 103 includes, but is not limited to, siO2 or SiARC (silicon-containing anti-reflective coating), wherein the Si-containing BARC has a much faster etching rate than the photoresist during the F ion etching, and can provide a higher etching selectivity. For example, the primary material of SiARC is an organosiloxane, which is a highly branched siloxane and is pendent with functional groups that absorb a specific wavelength. The material can be selected according to the requirement of the subsequent ion implantation and the formation of a new etching mask layer. May be formed by spin coating.
Next, as shown in S4 in fig. 1 and fig. 6-7, step S4 is performed to form a third mask layer 105 on the second mask layer 103, where the third mask layer 105 includes a plurality of third mask units 105a arranged at intervals and third gaps 105b between adjacent third mask units 105a, the third mask units 105a are correspondingly formed on the second mask units 103a, and the first mask units 102a are located in the corresponding third gaps 105 b.
The third mask layer 105 may be formed by a photolithography process, in an example, the third mask material layer 104 may be formed on the second mask layer 103 first, and then the third mask layer 105 may be formed by a photolithography process based on exposure and development, optionally, a material of the third mask material layer 104 may be the same as a material of the first mask material layer 101, for example, but not limited to photoresist, and in an example, a height of the third mask layer may be greater than or equal to a height of the first mask unit 102a and the second mask unit 103 a.
As an example, the height of the third mask unit 105a may be equal to or greater than the height of the first mask unit 102a, and then the position of the ion implantation region may be adjusted by adjusting the inclination angle of the ion implantation, and in a preferred example, the first mask unit 102a is flush with the upper surface of the third mask unit 105 a. So as to facilitate subsequent inclined ion implantation to form patterns with intermediate spacing.
Finally, as shown in S5 in fig. 1 and fig. 8-11, step S5 is performed to perform ion implantation on the second mask unit 103a based on the first mask unit 102a and the third mask unit 105a, and at least one implantation region 106 and at least one non-implantation region 107 are formed in the second mask unit 103a between the first mask unit 102a and the third mask unit 105a, so as to form a new etching mask layer based on the second mask unit 103a, the first mask unit 102a and the third mask unit 105a after ion implantation.
In this step, the second mask unit 103a is subjected to ion implantation by performing oblique ion implantation (Tilted ion implantation, TII) based on the shielding of the third mask unit 105a formed and the first mask unit 102a formed before, so as to form an implantation region 106 in the second mask unit 103a, and a non-implantation region 107 is formed in a portion where implantation is not performed, so that the second mask unit 103a has a portion located below the third mask unit 105a except for the implantation region 106 and the non-implantation region 107, and a shielding region 108 is defined. In this step, the angle of the inclined ion implantation, the implantation dose, the implantation energy, and the like are designed according to the actual structural requirements.
In an example, as shown in fig. 9, a negative oblique ion implantation (negative-tone) is used to form the implantation region 106, and the non-implantation region 107 is removed after the ion implantation, where the non-implantation region 107 is removed, and the first mask unit 102a and the second mask unit 103a corresponding to the lower portion of the third mask unit 105a, that is, the shielding region 108, are removed at the same time, so that only the implantation region 106 formed by the implantation is remained in the above manner, and thus, a plurality of implantation regions 106 form the new etching mask layer 109. In an example, the materials of the first mask unit 102a and the third mask unit 105a are selected as photoresist, the material of the second mask unit 103a is selected as SiARC, the ions for performing the oblique ion implantation are selected as ar+, but not limited thereto, the process of removing the non-implantation region 107, the first mask unit 102a and the shielding region 108 may be to remove the photoresist materials of the first mask unit 102a, the barrier layer 102c and the third mask unit 105a by using an O2 plasma, and then select a wet etching, and the etching solution is selected as HF diluted with 200:1 (water: HF) to etch the non-implantation region 107.
In another example, as shown in fig. 10, a positive-angled ion implantation (positive-tone) is used to form the implantation region 106, and the implantation region 106 is removed after the ion implantation, where the first mask unit 102a, the non-implantation region 107, and the second mask unit 103a (i.e., the shielding region 108) corresponding to the lower portion of the third mask unit 105a remain, so as to form the new etching mask layer 109. In an example, the materials of the first mask unit 102a and the third mask unit 105a are selected to be photoresist, the material of the second mask unit 103a is selected to be SiO2, the ions for performing the oblique ion implantation are selected to be ar+, but not limited thereto, the process of removing the implantation region 106 may be wet etching, and the etching solution is selected to etch the implantation region 106 with HF diluted with 10:1 (water: HF).
In an example, the first mask units 102a are uniformly spaced, the third mask units 105a are uniformly spaced, the first mask units 102a and the third mask units 105a are alternately spaced, and the first mask units 102a are located at a center position of the third gap 105b between the adjacent third mask units 105a, so as to form the uniformly spaced first mask units 102a and the third mask units 105a, and in a further alternative example, the widths of the first mask units 102a, the third mask units 105a, and the non-implanted regions 107 are equal. In addition, after the barrier layer is formed on the surface of the first mask unit 102a, the width and height thereof are up to the size after the barrier layer is formed.
In addition, as shown in fig. 11, the semiconductor base 100 includes a semiconductor substrate 100a and a hard mask layer 100b formed on the semiconductor substrate 100a, in this example, the pattern on the new etching mask layer 109 formed as described above is transferred into the hard mask layer 100b, and a patterned hard mask layer 110 is formed to perform etching down based thereon. In the above-described manner of the present invention, the feature pitch (pitch) is reduced to 1/4 of the original pitch with respect to the first mask layer 102 formed on the semiconductor substrate 100. In addition, the present invention also provides a comparative example in which 3 pairs (6) of mask patterns are formed by LELELE (Litho-inch-Litho-inch-Litho-inch), and 7 mask patterns can be formed by using the method of the present invention, for example, using the above LFLE (Litho-freeze-Litho-inch) process in combination with oblique ion implantation, and it can be seen that the present invention reduces 1 lithography and 2 etchings with respect thereto. In addition, based on the scheme of the invention, the first mask layer can be obtained by performing first exposure and development through one photomask, then when the third mask layer is obtained, the photomask is still used, and WAFER STAGE (wafer platform) is quantitatively moved, so that patterns with fixed intervals and equal size can be obtained through two exposures.
In addition, as shown in fig. 13, an etching schematic diagram of the second mask unit 103a (selected as SiARC material) after ar+ ion implantation is provided, wherein wet etching is selected in the etching process, and the etching solution is selected as HF diluted with 200:1 (water: HF). Fig. 13 (a) shows the relationship between etching time and etching thickness after ion implantation is not performed and different concentrations of ar+ ions are performed. It can be seen that after ion implantation with a certain concentration, the thickness of the material layer which can be etched away gradually increases and gradually becomes stable along with the increase of the ion implantation concentration in the same time; fig. 13 (b) shows that as the doping concentration increases, the initial etch rate gradually decreases, such as the rate at which SiARC ion implantation begins to etch, the percentage of film remaining gradually increases, and gradually stabilizes. Further, as shown in fig. 14, an etched structure image formed after oblique ion implantation (TII) performed as Ar ions is shown, and the upper graph shows that uniformity (uniformity) of the TII pattern even at 9nm is controllable.
As shown in fig. 8, and referring to fig. 1-7 and fig. 9-12, the present invention further provides a semiconductor structure, which includes:
A semiconductor substrate 100;
The first mask layer 102 is located on the semiconductor substrate, and includes a plurality of first mask units 102a arranged at intervals and first gaps 102b located between adjacent first mask units, where the first gaps 102b expose the semiconductor substrate 100;
The second mask layer 103 is located on the semiconductor substrate, the second mask layer includes a plurality of second mask units 103a arranged at intervals and second gaps 103b located between adjacent second mask units, the second mask units 103a are correspondingly formed on the semiconductor substrate 100 exposed by the first gaps 102b, the second gaps expose the semiconductor substrate, the upper surface of the second mask units 103a is lower than the upper surface of the first mask units 102a, and the first mask units pass through the corresponding second gaps;
The third mask layer 105 is located on the second mask layer, and the third mask layer includes a plurality of third mask units 105a arranged at intervals and third gaps 105b located between adjacent third mask units, where the third mask units 105a are correspondingly formed on the second mask units 103a, and the first mask units are located in the corresponding third gaps;
The second mask unit further includes at least one implanted region 106 and at least one non-implanted region 107 that are ion implanted to form a new etch mask layer 109 based on the second mask unit, the first mask unit, and the third mask unit.
As an example, the height of the third mask unit 105a may be equal to or greater than the height of the first mask unit 102a, and in a preferred example, the first mask unit 102a is flush with the upper surface of the third mask unit 105 a. So as to facilitate subsequent inclined ion implantation to form patterns with intermediate spacing.
As an example, the material of the first mask layer 102 includes photoresist, the material of the second mask layer 103 includes a silicon doped anti-reflective layer or a silicon oxide layer, and the material of the third mask layer 105 includes photoresist.
In summary, the semiconductor structure and the preparation method thereof can combine the exposure-solidification-exposure-etching process with the inclined ion implantation process, thereby simplifying the process steps, saving the cost and improving the process efficiency. The invention makes the pattern by the exposure and negative development method of the positive photoresist, can effectively improve the pattern precision, provides effective guarantee for the miniaturization of the pattern feature size, does not need special technological process in the whole process, and has simple whole process, low cost and high productivity. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (13)

1. A method of fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate;
Forming a first mask layer on the semiconductor substrate, wherein the first mask layer comprises a plurality of first mask units which are arranged at intervals and first gaps between adjacent first mask units, and the first gaps expose the semiconductor substrate;
Forming a second mask layer on the semiconductor substrate, wherein the second mask layer comprises a plurality of second mask units which are arranged at intervals and second gaps between adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed by the first gaps, the second gaps expose the semiconductor substrate, the upper surface of each second mask unit is lower than the upper surface of each first mask unit, and each first mask unit passes through the corresponding second gap;
forming a third mask layer on the second mask layer, wherein the third mask layer comprises a plurality of third mask units which are arranged at intervals and third gaps between adjacent third mask units, the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
and performing oblique ion implantation on the second mask unit based on shielding of the first mask unit and the third mask unit, and forming at least one implantation region and at least one non-implantation region in the second mask unit between the first mask unit and the third mask unit so as to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit after ion implantation.
2. The method of claim 1, wherein the forming the first mask layer and the third mask layer by a photolithography process, wherein the forming the first mask layer further comprises forming a barrier layer on a surface of the first mask unit.
3. The method of fabricating a semiconductor structure of claim 1, wherein the second mask layer is formed by a spin-on process; the material of the second mask layer comprises a silicon doped anti-reflection layer or a silicon oxide layer.
4. The method of claim 1, wherein an upper surface of the third mask unit is not lower than an upper surface of the first mask unit.
5. The method of claim 1, wherein the semiconductor substrate comprises a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, and further comprising the step of transferring the pattern on the new etch mask layer to the hard mask layer after forming the new etch mask layer.
6. The method of claim 1, wherein the material of the first mask layer is the same as the material of the third mask layer, and the material of the first mask layer and the third mask layer comprises photoresist.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein the first mask units are uniformly spaced apart, the third mask units are uniformly spaced apart, and the first mask units and the third mask units are alternately spaced apart, and the widths of the first mask units, the third mask units, and the non-implanted region are equal.
8. The method of claim 1, wherein the first gap and the third gap have a width equal to each other, and the first mask unit is located at a center of the third gap.
9. The method of any one of claims 1-8, wherein positive angled ion implantation is used to form the implanted region and the implanted region is removed after ion implantation, wherein the first mask unit, the non-implanted region, and the corresponding second mask unit under the third mask unit form the new etch mask layer.
10. The method of any one of claims 1-8, wherein the implantation region is formed by negative oblique ion implantation, and the non-implantation region is removed after the ion implantation, wherein the non-implantation region is removed, and the second mask unit corresponding to the first mask unit and the third mask unit is removed at the same time, and the implantation region forms the new etching mask layer.
11. A semiconductor structure, the semiconductor structure comprising:
a semiconductor substrate;
the first mask layer is positioned on the semiconductor substrate and comprises a plurality of first mask units which are arranged at intervals and first gaps between adjacent first mask units, and the first gaps expose the semiconductor substrate;
The second mask layer is positioned on the semiconductor substrate and comprises a plurality of second mask units which are arranged at intervals and second gaps between the adjacent second mask units, the second mask units are correspondingly formed on the semiconductor substrate exposed by the first gaps, the second gaps expose the semiconductor substrate, the upper surface of each second mask unit is lower than the upper surface of each first mask unit, and each first mask unit penetrates through the corresponding second gap;
the third mask layer is positioned on the second mask layer and comprises a plurality of third mask units which are arranged at intervals and third gaps between every two adjacent third mask units, wherein the third mask units are correspondingly formed on the second mask units, and the first mask units are positioned in the corresponding third gaps;
The second mask unit further comprises at least one implanted region and at least one non-implanted region subjected to ion implantation to form a new etching mask layer based on the second mask unit, the first mask unit and the third mask unit.
12. The semiconductor structure of claim 11, wherein an upper surface of the third mask unit is not lower than an upper surface of the first mask unit; and a blocking layer is also formed on the surface of the first mask unit.
13. The semiconductor structure of any of claims 11-12, wherein a material of the first mask layer is the same as a material of the third mask layer, the materials of the first mask layer and the third mask layer including photoresist; the material of the second mask layer comprises a silicon doped anti-reflection layer or a silicon oxide layer.
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